A four-switch Buck-Boost converter with soft-switching double closed-loop control

Abstract

The present invention discloses a four-switch Buck-Boost converter based on soft-switching double closed-loop control, belonging to the field of power electronic conversion. The four-switch Buck-Boost converter includes an input DC power supply unit, a first Buck arm, an energy storage unit, a second Boost arm, an output filter capacitor, and an output DC load connected in sequence; the soft-switching double closed-loop control loop is composed of an input voltage sampling unit, an output voltage sampling unit, an inductor current sampling unit, an output current sampling unit, a loop compensation unit, a conduction time calculation unit, a control strategy logic unit, a PWM unit, and a half-bridge drive unit connected in sequence. The present invention can achieve soft-switching control of the four-switch Buck-Boost converter, and accumulates the calculation results of the conduction time calculator and the loop compensation unit to realize two-stage regulation of the output voltage, having the advantages of high output voltage accuracy, fast transient response, etc.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronic conversion, and particularly relates to a four-switch Buck-Boost converter with soft-switching double closed-loop control. Background Art

[0002] DC-DC conversion technology applies power semiconductor devices to convert the DC bus voltage into the voltages required by various DC loads, and is widely used in national defense, aerospace, industrial radar, intelligent buildings, various laboratories and daily life.

[0003] So far, domestic and foreign power electronics researchers' research on non-isolated DC-DC converters has mainly focused on hard-switching converters such as Buck, Boost, and Buck-Boost. The switching losses of hard-switching converters increase with the increase of frequency, which limits the increase of the operating frequency of hard-switching converters, and further limits the improvement of the power density of hard-switching converters. The emergence of soft-switching technology solves the problem of high-frequency operation, and promotes the further development of converters towards miniaturization and high power density.

[0004] After the four-switch Buck-Boost converter that can realize the step-up and step-down functions and obtain the in-phase output voltage was proposed, its control strategy has become a research hotspot. In the initial stage of research, the hard-switching control strategy was mainly used. At first, the Buck-Boost control strategy was adopted, and its advantage compared with the traditional Buck-Boost is that it can realize the in-phase of the input and output voltages, which is called single-mode control. This control strategy has low efficiency; subsequently, according to the relationship between the input voltage and the output voltage, the Buck control strategy and the Boost control strategy were respectively proposed, but when the input voltage and the output voltage are relatively close, there is a problem of repeated switching of the control strategy; the three-mode control solves this problem. When the input and output voltages are relatively close, the Buck-Boost control strategy is adopted to realize the smooth switching between control modes, and compared with the single-mode control, the local efficiency is improved.

[0005] To further improve the efficiency, a soft-switching control strategy for a four-switch Buck-Boost converter with the inductor current as the control object was proposed. This control strategy includes four working modes. By adjusting the duration of each mode, step-up and step-down control can be realized, and at the same time, soft-switching of all switching tubes can be realized. This mode involves complex calculations, and usually the look-up table method is used to adjust the duty cycle of each mode according to the changes of the input voltage, output voltage and output current. However, when the input voltage range is wide, the output voltage is adjustable and the load current is large, the look-up table method requires a large amount of memory, and the transient response is slow. At the same time, there is a risk of poor consistency of the converter characteristics. Summary of the Invention

[0006] The object of the present invention is to provide a four-switch Buck-Boost converter with soft-switching double closed-loop control to solve the problems in the background technology.

[0007] To solve the above technical problems, the present invention provides a four-switch Buck-Boost converter with soft-switching double closed-loop control, including an input DC power supply unit, a first Buck arm, an energy storage unit, a second Boost arm, an output filter capacitor, and an output DC load connected in sequence;

[0008] The input DC power supply unit is a DC power supply Vin, and its negative pole is connected to the ground;

[0009] The first Buck arm includes a first power switch tube S1 and a second power switch tube S2; the drain terminal of the first power switch tube S1 is connected to the positive pole of the DC power supply Vin, and the source terminal is connected to the drain terminal of the second power switch tube S2, and the source terminal of the second power switch tube S2 is grounded;

[0010] The output filter capacitor is a capacitor Co, and the output DC load is a resistor RL; the resistor RL is connected in parallel between the positive and negative terminals of the capacitor Co;

[0011] The second Boost arm includes a third power switch tube S3 and a fourth power switch tube S4; the drain terminal of the third power switch tube S3 is connected to one end of the resistor RL, and the source terminal is connected to the drain terminal of the fourth power switch tube S4, and the source terminal of the fourth power switch tube S4 is grounded;

[0012] The energy storage unit includes an energy storage inductor L, and the energy storage inductor L is used to connect the first Buck arm and the second Boost arm. One end of the energy storage inductor L is connected to the source terminal of the first power switch tube S1 and the drain terminal of the second power switch tube S2, and the other end is connected to the source terminal of the third power switch tube S3 and the drain terminal of the fourth power switch tube S4.

[0013] In one embodiment, the four-switch Buck-Boost converter with soft-switching double closed-loop control further includes a soft-switching double closed-loop control loop, which is composed of an input voltage sampling unit, an output voltage sampling unit, an inductor current sampling unit, an output current sampling unit, a loop compensation unit, a conduction time calculation unit, a control strategy logic unit, a PWM unit, and a half-bridge drive unit connected in sequence;

[0014] The input voltage sampling unit includes voltage-dividing resistors R1 and R2. One end of the voltage-dividing resistor R1 is connected to the positive pole of the DC power supply Vin, and the other end is connected to one end of the voltage-dividing resistor R2, and the other end of the voltage-dividing resistor R2 is connected to the negative pole of the DC power supply Vin;

[0015] The output voltage sampling unit includes voltage dividing resistors R3 and R4. One end of the voltage dividing resistor R3 is connected to the drain terminal of the third power switch tube S3, and the other end is connected to one end of the voltage dividing resistor R4. The other end of the voltage dividing resistor R4 is connected to the negative pole of the input DC power supply unit;

[0016] The inductor current sampling unit includes a sampling resistor R5, a sampling capacitor C1, voltage conditioning resistors R6 to R9, and a first differential operational amplifier Diff1. One end of the sampling resistor R5 is connected to one end of the energy storage inductor L, the source terminal of the first power switch tube S1, and the drain terminal of the second power switch tube S2, and the other end is connected to one end of the sampling capacitor C1. The other end of the sampling capacitor C1 is connected to the other end of the energy storage inductor L, the source terminal of the third power switch tube S3, and the drain terminal of the fourth power switch tube S4. The other end of the sampling capacitor C1 is connected to one end of the voltage conditioning resistor R6. The other end of the voltage conditioning resistor R6 is connected to the voltage conditioning resistor R7 and the inverting input terminal of the first differential operational amplifier Diff1. The other end of the voltage conditioning resistor R7 is connected to the output terminal of the first differential operational amplifier Diff1. The connection point of the sampling resistor R5 and the sampling capacitor C1 is connected to one end of the voltage conditioning resistor R8. The other end of the voltage conditioning resistor R8 is connected to one end of the voltage conditioning resistor R9 and the non-inverting input terminal of the first differential operational amplifier Diff1. The other end of the voltage conditioning resistor R9 is grounded;

[0017] The output current sampling unit includes a sampling resistor R10, voltage conditioning resistors R11 to R13, and a second differential operational amplifier Diff2. One end of the sampling resistor R10 is connected to the negative terminal of the capacitor Co and one end of the voltage conditioning resistor R11. The other end of the voltage conditioning resistor R11 is connected to the voltage conditioning resistor R12 and the inverting input terminal of the second differential operational amplifier Diff2. The other end of the voltage conditioning resistor R12 is connected to the output terminal of the second differential operational amplifier Diff2. The other end of the sampling resistor R10 is connected to the negative pole of the DC power supply Vin and one end of the voltage conditioning resistor R13. The other end of the voltage conditioning resistor R13 is connected to the non-inverting input terminal of the second differential operational amplifier Diff2;

[0018] The loop compensation unit includes a transconductance operational amplifier Gm, a compensation resistor R14, compensation capacitors C1 and C2. The inverting input terminal of the transconductance operational amplifier Gm is connected between the voltage dividing resistors R3 and R4, the non-inverting input terminal is connected to the reference voltage Vref, and the output terminal is connected to one end of the compensation resistor R14 and the compensation capacitor C3. The other end of the compensation capacitor C3 is grounded. The other end of the compensation resistor R14 is grounded through the compensation capacitor C2;

[0019] The on-time calculation unit includes an on-time calculator, voltage-dividing resistors R15 and R16; a first input terminal of the on-time calculator is connected to the connection point of the voltage-dividing resistors R1 and R2, a second input terminal is connected to the connection point of the voltage-dividing resistors R15 and R16, and a third input terminal is connected to the output terminal of the second differential operational amplifier Diff2; one end of the voltage-dividing resistor R15 is connected to the bias voltage Vbias1, and the other end is grounded through the voltage-dividing resistor R16; the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal of the on-time calculator are all connected to the access control strategy logic unit;

[0020] The control strategy logic unit includes adders Sum1 to Sum2, timers Timer1 to Timer2, a multiplexer MUX1, a comparator Comp1, flip-flops FF1 to FF2; a first input terminal of the adder Sum1 is connected to the output terminal of the transconductance operational amplifier Gm, a second input terminal is connected to the first output terminal of the on-time calculator, and a third input terminal is connected to the third output terminal of the on-time calculator;

[0021] A first input terminal of the multiplexer MUX1 is connected to the output terminal of the transconductance operational amplifier Gm, a second input terminal is connected to the zero potential, a control terminal is connected to the second output terminal of the on-time calculator, and an output terminal is connected to the first input terminal of the adder Sum2; a second input terminal of the adder Sum2 is connected to the third output terminal of the on-time calculator;

[0022] A first input terminal of the timer Timer1 is connected to the clock signal CLK, and a second input terminal is connected to the output terminal of the adder Sum1; a first input terminal of the timer Timer2 is connected to the clock signal CLK, and a second input terminal is connected to the output terminal of the adder Sum2;

[0023] The negative electrode of the comparator Comp1 is connected to the output terminal of the first differential operational amplifier Diff1, and the positive electrode is connected to the fourth output terminal of the on-time calculator; the S terminal of the flip-flop FF1 is connected to the clock signal CLK, and the R terminal is connected to the output terminal of the timer Timer1; the S terminal of the flip-flop FF2 is connected to the output terminal of the timer Timer2, and the R terminal is connected to the output terminal of the comparator Comp1;

[0024] The PWM unit includes PWM modulators PWM1 to PWM2, the output terminal of the flip-flop FF1 is connected to the input terminal of the PWM modulator PWM1, and the output terminal of the flip-flop FF2 is connected to the input terminal of the PWM modulator PWM2;

[0025] The half-bridge drive unit includes a half-bridge driver HBD1 and a half-bridge driver HBD2; two output terminals of the PWM modulator PWM1 are connected to the half-bridge driver HBD1, and two output terminals of the PWM modulator PWM2 are connected to the half-bridge driver HBD2; four output terminals of the half-bridge driver HBD1 are respectively connected to the gate terminal, source terminal of the first power switch S1, the gate terminal of the second power switch S2, and the negative pole of the DC power supply Vin, and four output terminals of the half-bridge driver HBD2 are respectively connected to the gate terminal, source terminal of the third power switch S3, the gate terminal of the fourth power switch S4, and the negative pole of the DC power supply Vin.

[0026] In one embodiment, the on-time calculator solves according to the input voltage sampling value, the output voltage set value, and the output current sampling value, calculates the on-time of the power switch, and simultaneously determines the working mode of the converter.

[0027] In one embodiment, the PWM modulators PWM1 and PWM2 have the same structure, and respectively include resistors R17 to R18, capacitors C4 to C5, inverters NOT1 to NOT4, switching transistors M1 to M2, a NAND gate NAND1, an AND gate AND1, NOR gates NOR1 to NOR2;

[0028] The first terminal of resistor R17, the first terminal of resistor R18, the input terminals of inverter NOT1, the input terminals of inverter NOT1, the first input terminal of NAND gate NAND1, the first input terminal of AND gate AND1, the second input terminal of NOR gate NOR1, and the second input terminal of NOR gate NOR2 are all connected;

[0029] The second terminal of resistor R17 is simultaneously connected to the first terminal of capacitor C4, the drain terminal of switching transistor M1, and the input terminal of inverter NOT2, and the second terminal of capacitor C4 is grounded; the output terminal of inverter NOT1 is connected to the gate terminal of switching transistor M1, and the source terminal of switching transistor M1 is grounded; the output terminal of inverter NOT2 is connected to the second input terminal of NAND gate NAND1, the output terminal of NAND gate NAND1 is connected to the second input terminal of AND gate AND1, and the output terminal of AND gate AND1 is one output terminal of the PWM modulator;

[0030] The second terminal of resistor R18 is simultaneously connected to one end of capacitor C5, the source terminal of switching transistor M2, and the input terminal of inverter NOT4, and the other end of capacitor C5 is connected to the bias voltage Vbias2; the output terminal of inverter NOT4 is connected to the first input terminal of NOR gate NOR1, the output terminal of NOR gate NOR1 is connected to the first input terminal of NOR gate NOR2, and the output terminal of NOR gate NOR2 is the other output terminal of the PWM modulator.

[0031] Compared with the prior art, a four-switch Buck-Boost converter with soft-switching double closed-loop control provided by the present invention has the following beneficial effects:

[0032] (1) Taking the inductor current as one of the control objects to achieve soft-switching control of all switching tubes;

[0033] (2) Introducing a loop compensation unit into the voltage loop, and together with the conduction time calculator, realizing two-stage regulation of the output voltage, so as to obtain higher-precision output voltage and faster transient response characteristics;

[0034] (3) The control structure is simple and easy to be realized digitally. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 FIG. is a schematic structural diagram of a four-switch Buck-Boost converter with soft-switching double closed-loop control provided by the present invention.

[0036] Figure 2 FIG. is a structural diagram of a pulse width modulation unit with dead zone function in the control loop.

[0037] Figure 3 FIG. is a schematic diagram of the inductor current waveform when the input voltage is higher than the output voltage.

[0038] Figure 4 FIG. is a schematic diagram of the inductor current waveform when the input voltage is lower than the output voltage.

[0039] Figure 5 FIG. is a schematic diagram of the comparison of the transient characteristics and steady-state error of the control strategy between the present invention and the existing look-up table method. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] The following further describes in detail a four-switch Buck-Boost converter with soft-switching double closed-loop control proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0041] A four-switch Buck-Boost converter with soft-switching double closed-loop control provided by the present invention adopts two-stage regulation of the output voltage. The conduction time calculator calculates the conduction times t1 and t2 of the power switch tubes according to the sampled value of the input voltage, the set value of the output voltage, and the sampled value of the output current, so as to realize the rough adjustment of the output voltage. The sampled signal of the output voltage and the reference voltage are second-order compensated to obtain Δt, and according to the buck-boost mode, Δt is superimposed on t1 or t2, thereby realizing the precise adjustment of the output voltage and improving the output voltage accuracy and transient characteristics at the same time.

[0042] Combined withFigure 1 As shown in the figure, a four-switch Buck-Boost converter with soft-switching double closed-loop control of the present invention is composed of an input DC power supply unit 1, a first Buck arm 2, an energy storage unit 3, a second Boost arm 4, an output filter capacitor 5, and an output DC load 6 connected in sequence; this converter can achieve step-up conversion or step-down conversion of DC voltage, and output a DC voltage with the same polarity as the input voltage, which is suitable for DC voltage conversion occasions where the input voltage varies within a wide range. The four-switch Buck-Boost converter with soft-switching double closed-loop control further includes a soft-switching double closed-loop control loop, which is composed of an input voltage sampling unit 7, an output voltage sampling unit 8, an inductor current sampling unit 9, an output current sampling unit 10, a loop compensation unit 11, a conduction time calculation unit 12, a control strategy logic unit 13, a PWM unit 14, and a half-bridge drive unit 15 connected in sequence; when the load current suddenly changes, the conduction time calculation unit 12 determines the working mode according to the input voltage sampling value, the output voltage setting value, and the output current sampling value as the gating signal of the selector, and at the same time calculates the new t1 and t2 to achieve rough adjustment of the output voltage; the loop compensation unit 11 further adjusts based on the error value between the input voltage sampling value and the reference voltage, so that the output voltage approaches the target voltage, realizing fine adjustment of the output voltage, thereby realizing the DC voltage conversion function with high output voltage accuracy and good transient characteristics.

[0043] As Figure 2 shown, the rising-edge dead time and the falling-edge dead time are adjusted by Figure 2 the values of resistors R17, R18 and capacitors C4, C5 in

[0044] When the input terminal IN jumps from low level to high level, the switch tube M2 conducts rapidly. The voltage at one end of the capacitor C5 is fixed, and the voltage at the other end (i.e., point B) jumps rapidly to high level, making the output terminal OUT2 jump rapidly to low level. The input terminal IN charges the capacitor C5 through the resistor R18, and the voltage of the capacitor C5 rises slowly. When the voltage of the capacitor C5 rises to a high level determined by the inverter NOT2, the output terminal OUT1 jumps to high level. Thus, when the input terminal IN jumps upward, the output terminal OUT2 jumps rapidly to low level, and the output terminal OUT1 jumps to high level after the voltage of the capacitor C5 rises to a high level, obtaining the rising-edge dead time tdead1.

[0045] When the input terminal IN jumps from a high level to a low level, the switching transistor M1 conducts rapidly, and the capacitor C5 discharges rapidly through the switching transistor M1. The voltage of the capacitor C5 drops rapidly to a low level, causing the output terminal OUT1 to jump rapidly to a low level. The capacitor C4 discharges slowly through the resistor R17, and the voltage of the capacitor C4 drops slowly. When the voltage drops to a level where the inverter NOT4 determines it to be low, the output terminal OUT2 jumps to a high level. Thus, when the input terminal IN jumps downward, the output terminal OUT1 jumps rapidly to a low level, and the output terminal OUT2 jumps to a high level after the voltage of the capacitor C4 drops to a low level, obtaining the falling-edge dead time tdead2.

[0046] As Figure 3 and Figure 4 To illustrate the soft-switching condition, the valley value of the inductor current is -Izvs. Izvs needs to ensure that the junction capacitance of the power switching transistor is charged and discharged within the dead time, so as to achieve soft switching of the power switching transistor. The relationship between Izvs, the dead time tdead, the junction capacitance Cds of the power switching transistor, the input voltage Vin, and the output voltage Vo needs to satisfy Equation 1:

[0047]

[0048] Combined with Figure 3 To illustrate the inductor current waveform when Vo ≤ Vin, at the beginning of the switching period, the inductor current starts to rise from -Izvs, and the slope satisfies Equation (2). When it rises to Izvs, t1 ends, so as to meet the minimum effective value of the inductor current to reduce the overall conduction loss. After t1 ends, the inductor current continues to rise, and the slope satisfies Equation (3) until t2 ends. When t3 starts, the inductor current starts to decline, and the slope satisfies Equation (4) until it drops to -Izvs and t3 ends. The inductor current remains at -Izvs until the next switching period starts.

[0049]

[0050]

[0051]

[0052] t1 and t2 are calculated by the conduction time calculator, where t1 satisfies Equation (5):

[0053]

[0054] Taking t2 as the independent variable, t3 and t4 satisfy Equations (6) and (7) according to the relationship among t2, Vo, and Vin:

[0055]

[0056] t4(t2,V o, V in ) = T s -t1(V in ) - t2 - t3(t2, V o , V in ) (7)

[0057] The output current Io is a function of t2, the output voltage Vo, and the input voltage Vin. The conduction time calculator needs to calculate the value of t2 according to Equation (8) based on the input voltage, output voltage, and output current.

[0058]

[0059] Combined with the attached Figure 4 Explain the inductor current waveform when Vo > Vin. At the start of the switching period, the inductor current starts to rise from -Izvs with a slope satisfying Equation (2) until the end of t1. At the start of t2, the inductor current starts to fall with a slope satisfying Equation (3) and ends at Izvs when t2 ends. At the start of t3, the inductor current continues to fall with a slope satisfying Equation (4) and ends at -Izvs when t3 ends. At the start of t4, the inductor current maintains -Izvs until the start of the next switching period.

[0060] Among them, t3 satisfies Equation (9):

[0061]

[0062] t1 and t2 are calculated by the conduction time calculator. Taking t1 as the independent variable, then t2 and t4 satisfy Equations (10) and (11) with respect to t1, Vo, and Vin:

[0063]

[0064] t4(t1, V o , V in ) = T s -t1 - t2(t1, V o , V in ) - t3(V o ) (11)

[0065] The output current Io is a function of t1, the output voltage, and the input voltage. The calculator needs to calculate the value of t1 according to Equation (4) based on the input voltage, output voltage, and output current.

[0066]

[0067] Combined with Figure 5This is a comparison of the transient characteristics of the present invention and the prior art when the load current changes suddenly. The target output voltage is set to 12V, and the load current changes suddenly from 10A to 12A at 6ms. In State 1, due to the limitation of the memory capacity, there are certain accuracy problems with the prior art look-up table method, and there is a static error of 0.1V. The static error of the present invention is less than 5mV. When the load changes suddenly, both the look-up table method and the present invention adjust the values of t1 and t2 simultaneously. However, the look-up table method reaches a new steady-state value of 11.85V after 0.51μs, with a static error of 0.15V. After the loop compensation unit 11 in the present invention monitors the decrease in the output voltage, it quickly increases the value of t2, so as to reach a new steady-state value of 11.98V after 0.18μs, and the static error is only 0.02V.

[0068] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A four-switch Buck-Boost converter with soft-switching double closed-loop control, characterized in that, It includes an input DC power supply unit (1), a first Buck leg (2), an energy storage unit (3), a second Boost leg (4), an output filter capacitor (5), and an output DC load (6) connected in sequence; The input DC power supply unit (1) is a DC power supply Vin, whose negative terminal is connected to the ground; The first Buck leg (2) includes a first power switch S1 and a second power switch S2; the drain terminal of the first power switch S1 is connected to the positive terminal of the DC power supply Vin, the source terminal is connected to the drain terminal of the second power switch S2, and the source terminal of the second power switch S2 is grounded; The output filter capacitor (5) is a capacitor Co, and the output DC load (6) is a resistor RL; the resistor RL is connected in parallel between the positive terminal and the negative terminal of the capacitor Co; The second Boost leg (4) includes a third power switch S3 and a fourth power switch S4; the drain terminal of the third power switch S3 is connected to one end of the resistor RL, the source terminal is connected to the drain terminal of the fourth power switch S4, and the source terminal of the fourth power switch S4 is grounded; The energy storage unit (3) includes an energy storage inductor L, and the energy storage inductor L is used to connect the first Buck leg (2) and the second Boost leg (4). One end of the energy storage inductor L is connected to the source terminal of the first power switch S1 and the drain terminal of the second power switch S2, and the other end is connected to the source terminal of the third power switch S3 and the drain terminal of the fourth power switch S4; The four-switch Buck-Boost converter with soft-switching double closed-loop control further includes a soft-switching double closed-loop control loop, which is composed of an input voltage sampling unit (7), an output voltage sampling unit (8), an inductor current sampling unit (9), an output current sampling unit (10), a loop compensation unit (11), a conduction time calculation unit (12), a control strategy logic unit (13), a PWM unit (14), and a half-bridge drive unit (15); The input voltage sampling unit (7) includes voltage-dividing resistors R1 and R2. One end of the voltage-dividing resistor R1 is connected to the positive terminal of the DC power supply Vin, the other end is connected to one end of the voltage-dividing resistor R2, and the other end of the voltage-dividing resistor R2 is connected to the negative terminal of the DC power supply Vin; The output voltage sampling unit (8) includes voltage-dividing resistors R3 and R4. One end of the voltage-dividing resistor R3 is connected to the drain terminal of the third power switch S3, the other end is connected to one end of the voltage-dividing resistor R4, and the other end of the voltage-dividing resistor R4 is connected to the negative terminal of the input DC power supply unit (1); The inductor current sampling unit (9) includes a sampling resistor R5, a sampling capacitor C1, voltage conditioning resistors R6 to R9, and a first differential operational amplifier Diff1. One end of the sampling resistor R5 is connected to one end of the energy storage inductor L, the source terminal of the first power switch S1, and the drain terminal of the second power switch S2, and the other end is connected to one end of the sampling capacitor C1. The other end of the sampling capacitor C1 is connected to the other end of the energy storage inductor L, the source terminal of the third power switch S3, and the drain terminal of the fourth power switch S4. The other end of the sampling capacitor C1 is connected to one end of the voltage conditioning resistor R6, and the other end of the voltage conditioning resistor R6 is connected to the voltage conditioning resistor R7 and the inverting input terminal of the first differential operational amplifier Diff1. The other end of the voltage conditioning resistor R7 is connected to the output terminal of the first differential operational amplifier Diff1. The connection point of the sampling resistor R5 and the sampling capacitor C1 is connected to one end of the voltage conditioning resistor R8, and the other end of the voltage conditioning resistor R8 is connected to one end of the voltage conditioning resistor R9 and the non-inverting input terminal of the first differential operational amplifier Diff1. The other end of the voltage conditioning resistor R9 is grounded. The output current sampling unit (10) includes a sampling resistor R10, voltage conditioning resistors R11 to R13, and a second differential operational amplifier Diff2. One end of the sampling resistor R10 is connected to the negative terminal of the capacitor Co and one end of the voltage conditioning resistor R11, and the other end of the voltage conditioning resistor R11 is connected to the voltage conditioning resistor R12 and the inverting input terminal of the second differential operational amplifier Diff2. The other end of the voltage conditioning resistor R12 is connected to the output terminal of the second differential operational amplifier Diff2. The other end of the sampling resistor R10 is connected to the negative terminal of the DC power supply Vin and one end of the voltage conditioning resistor R13, and the other end of the voltage conditioning resistor R13 is connected to the non-inverting input terminal of the second differential operational amplifier Diff2. The loop compensation unit (11) includes a transconductance operational amplifier Gm, compensation resistors R14, and compensation capacitors C1, C2. The inverting input terminal of the transconductance operational amplifier Gm is connected between the voltage dividing resistors R3 and R4, the non-inverting input terminal is connected to the reference voltage Vref, and the output terminal is connected to one end of the compensation resistor R14 and the compensation capacitor C3. The other end of the compensation capacitor C3 is grounded. The other end of the compensation resistor R14 is grounded through the compensation capacitor C2. The conduction time calculation unit (12) includes a conduction time calculator, voltage dividing resistors R15 and R16. The first input terminal of the conduction time calculator is connected to the connection point of the voltage dividing resistors R1 and R2, the second input terminal is connected to the connection point of the voltage dividing resistors R15 and R16, and the third input terminal is connected to the output terminal of the second differential operational amplifier Diff2. One end of the voltage dividing resistor R15 is connected to the bias voltage Vbias1, and the other end is grounded through the voltage dividing resistor R16. The first output terminal, the second output terminal, the third output terminal, and the fourth output terminal of the conduction time calculator are all connected to the access control strategy logic unit (13). The control strategy logic unit (13) includes adders Sum1 to Sum2, timers Timer1 to Timer2, a multiplexer MUX1, a comparator Comp1, and flip-flops FF1 to FF2. The first input terminal of adder Sum1 is connected to the output terminal of the transconductance operational amplifier Gm, the second input terminal is connected to the first output terminal of the on-time calculator, and the third input terminal is connected to the third output terminal of the on-time calculator. The first input terminal of multiplexer MUX1 is connected to the output terminal of the transconductance operational amplifier Gm, the second input terminal is connected to the zero potential, the control terminal is connected to the second output terminal of the on-time calculator, and the output terminal is connected to the first input terminal of adder Sum2. The second input terminal of adder Sum2 is connected to the third output terminal of the on-time calculator. The first input terminal of timer Timer1 is connected to the clock signal CLK, and the second input terminal is connected to the output terminal of adder Sum1. The first input terminal of timer Timer2 is connected to the clock signal CLK, and the second input terminal is connected to the output terminal of adder Sum2. The negative terminal of comparator Comp1 is connected to the output terminal of the first differential operational amplifier Diff1, and the positive terminal is connected to the fourth output terminal of the on-time calculator. The S terminal of flip-flop FF1 is connected to the clock signal CLK, and the R terminal is connected to the output terminal of timer Timer1. The S terminal of flip-flop FF2 is connected to the output terminal of timer Timer2, and the R terminal is connected to the output terminal of comparator Comp1. The PWM unit (14) includes PWM modulators PWM1 to PWM2. The output terminal of flip-flop FF1 is connected to the input terminal of PWM modulator PWM1, and the output terminal of flip-flop FF2 is connected to the input terminal of PWM modulator PWM2. The half-bridge drive unit (15) includes a half-bridge driver HBD1 and a half-bridge driver HBD2. The two output terminals of PWM modulator PWM1 are connected to half-bridge driver HBD1, and the two output terminals of PWM modulator PWM2 are connected to half-bridge driver HBD2. The four output terminals of half-bridge driver HBD1 are respectively connected to the gate terminal, source terminal of the first power switch S1, the gate terminal of the second power switch S2, and the negative terminal of the DC power supply Vin. The four output terminals of half-bridge driver HBD2 are respectively connected to the gate terminal, source terminal of the third power switch S3, the gate terminal of the fourth power switch S4, and the negative terminal of the DC power supply Vin.

2. The four-switch Buck-Boost converter with soft-switching double closed-loop control according to claim 1, wherein The on-time calculator solves based on the input voltage sampling value, output voltage setting value, and output current sampling value, calculates the on-time of the power switch, and simultaneously determines the operating mode of the converter.

3. The four-switch Buck-Boost converter with soft-switching double closed-loop control according to claim 2, characterized in that, The PWM modulator PWM1 and the PWM modulator PWM2 have the same structure, and respectively include resistors R17 to R18, capacitors C4 to C5, inverters NOT1 to NOT4, switching transistors M1 to M2, a NAND gate NAND1, an AND gate AND1, and NOR gates NOR1 to NOR2. The first terminal of resistor R17, the first terminal of resistor R18, the input terminal of inverter NOT1, the input terminal of inverter NOT1, the first input terminal of NAND gate NAND1, the first input terminal of AND gate AND1, the second input terminal of NOR gate NOR1, and the second input terminal of NOR gate NOR2 are all connected. The second terminal of resistor R17 is simultaneously connected to the first terminal of capacitor C4, the drain of switch M1, and the input terminal of inverter NOT2. The second terminal of capacitor C4 is grounded. The output terminal of inverter NOT1 is connected to the gate of switch M1, and the source of switch M1 is grounded. The output terminal of inverter NOT2 is connected to the second input terminal of NAND gate NAND1. The output terminal of NAND gate NAND1 is connected to the second input terminal of AND gate AND1. The output terminal of AND gate AND1 is an output terminal of the PWM modulator. The second terminal of resistor R18 is simultaneously connected to one end of capacitor C5, the source of switch M2, and the input terminal of inverter NOT4. The other end of capacitor C5 is connected to bias voltage Vbias2. The output terminal of inverter NOT4 is connected to the first input terminal of NOR gate NOR1. The output terminal of NOR gate NOR1 is connected to the first input terminal of NOR gate NOR2. The output terminal of NOR gate NOR2 is the other output terminal of the PWM modulator.

Images