A signal folding amplifier based on a capacitive digital-to-analog converter and a signal chain circuit thereof

Abstract

The application relates to a signal folding amplifier based on a capacitive digital-to-analog converter and a signal chain circuit thereof, which comprises a low-noise amplifier, a threshold detection circuit, a digital logic circuit and a capacitive digital-to-analog converter feedback network; the threshold detection circuit generates downward, holding and upward signals according to the comparison result of the amplitude of the low-noise amplifier output signal and high and low threshold voltages; the digital logic circuit counts the downward, holding or upward signals by minus one, unchanged or plus one to obtain a counting signal; the capacitive digital-to-analog converter feedback network is used for feeding back the low-noise amplifier output signal to the input end and controlling the output signal folding counting signal folding steps, so that the low-noise amplifier output signal is not saturated. The beneficial effect is that the design is simple, the response speed is fast, the input and output amplitudes are large, the input signal amplitude is large, and the output signal is not saturated under the condition of large gain.

Description

Technical field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a signal folding amplifier based on a capacitive digital-to-analog converter and a signal chain circuit thereof. [Background Technology]

[0002] When detecting some weak useful signals, signal chain circuits are often accompanied by large-amplitude interference signals (for example, interference signals introduced by chest rise and fall caused by breathing when detecting ECG signals). The differential-mode components in these large-amplitude interference signals cannot be eliminated by improving the common-mode rejection ratio, and filtering can only eliminate differential-mode interference signals outside the frequency band of weak useful signals. The differential-mode interference signals overlapping with the frequency band of weak useful signals cannot be eliminated. The amplitude of the differential-mode interference signals overlapping with the frequency band of weak useful signals is often one to two orders of magnitude larger than that of the weak useful signals. When the amplifier at the front end of the signal chain has a high gain, the signal chain circuit is extremely prone to saturation, resulting in the loss of useful signals.

[0003] In order to solve the problem of weak useful signal detection under large interference, the traditional signal chain circuit has a commonly used circuit structure as shown in the following figure. Figures 1-3 shown. Figure 1 This is a schematic diagram of the signal chain circuit architecture based on automatic gain control technology. Figure 1 As shown, the first conventional signal chain circuit uses the output of a low-precision analog-to-digital converter to control the gain of a programmable gain amplifier (PGA) to prevent circuit saturation. However, this signal chain circuit design is complex, and the feedback loop introduced through multiple circuit modules increases the response delay of the signal chain system. When the gain of the PGA is modulated to a low level, the amplification factor of weak useful signals is low, and the use of a low-precision PGA introduces significant error in the quantization of weak useful signals. The PGA gain can be increased, but this can lead to saturation of the signal chain, resulting in signal loss. Therefore, the PGA gain should be as large as possible while ensuring that the output is not saturated. Figure 2 This is a schematic diagram of the signal chain circuit architecture based on the digital-to-analog converter compensation technology. Figure 2 As shown, the second traditional signal chain circuit uses the output result of a low-precision analog-to-digital converter to be processed by a digital logic circuit and input into a digital-to-analog converter. The input large-amplitude differential-mode interference is subtracted from the output of the digital-to-analog converter at the input of the system. Ultimately, there is only a weak useful signal at the input end of the high-gain amplifier. However, the signal chain circuit design is complex, and the introduced feedback loop increases the response delay through multiple circuit modules. The digital logic circuit needs to distinguish the interference signal from the useful signal, which requires complex algorithms and circuits to achieve. Figure 3 This is a schematic diagram of the signal chain circuit architecture based on a high-precision analog-to-digital converter. Figure 3As shown, the third conventional signal chain circuit is realized by using a low-gain amplifier and a high-precision analog-to-digital converter in cascade. The use of the low-gain amplifier can ensure that the signal chain will not be saturated, but higher precision is required for the analog-to-digital converter in cascade, usually 24-bit analog-to-digital converter, which increases the design complexity of the signal chain circuit, increases the power consumption and area.

[0004] The present application aims at the technical problem that the differential mode interference signal overlapping with the weak useful signal band makes the signal chain circuit extremely easy to be saturated, and makes technical improvements to the signal folding amplifier. SUMMARY

[0005] The purpose of the present application is to provide a signal folding amplifier with simple design, fast response, large allowed input and output amplitudes, and output signal not saturated under the condition of large input signal amplitude and large gain.

[0006] To achieve the above-mentioned purpose, the technical solution adopted by the present application is a signal folding amplifier based on a capacitive digital-to-analog converter, used for collecting weak useful signals under large amplitude interference signals, comprising a low-noise amplifier, a threshold detection circuit, a digital logic circuit and a capacitive digital-to-analog converter feedback network; when the amplitude of the output signal of the low-noise amplifier is higher than the high threshold voltage, the threshold detection circuit generates a downward signal under the drive of the synchronous clock; when the amplitude of the output signal of the low-noise amplifier is between the high threshold voltage and the low threshold voltage, the threshold detection circuit generates a hold signal under the drive of the synchronous clock; when the amplitude of the output signal of the low-noise amplifier is lower than the low threshold voltage, the threshold detection circuit generates an upward signal under the drive of the synchronous clock; the digital logic circuit counts the downward, hold or upward signal by minus 1, unchanged or plus 1 under the drive of the synchronous clock to obtain a count signal; the capacitive digital-to-analog converter feedback network is used to feedback the output signal of the low-noise amplifier to the input end of the low-noise amplifier, control the output signal of the low-noise amplifier to fold the count signal by a folding step, so that the output signal of the low-noise amplifier will not be saturated; the output of the signal folding amplifier includes the output signal of the low-noise amplifier and the count signal of the digital logic circuit.

[0007] Preferably, the threshold detection circuit comprises a high threshold comparator for high threshold voltage detection and a low threshold comparator for low threshold voltage detection; the positive input end of the high threshold comparator is connected to the high threshold voltage, the negative input end of the low threshold comparator is connected to the low threshold voltage, and the negative input end of the high threshold comparator and the positive input end of the low threshold comparator are commonly connected to the output end of the low-noise amplifier.

[0008] Preferably, the high threshold comparator and the low threshold comparator are driven by the same clock and are triggered for comparison at the rising edge of the clock; the down signal generated by the threshold detection circuit is 10, the hold signal is 11, and the up signal is 01.

[0009] Preferably, the digital logic circuit consists of an N-bit up-down counter and an N to 2 N The decoder is composed of a decoder; the N-bit up-down counter is a binary code counter, and the clock signal that drives the N-bit up-down counter to count synchronously has the same frequency as the clock signal that drives the threshold detection circuit to compare synchronously; the input end of the N-bit up-down counter is connected to the output end of the threshold detection circuit, the threshold detection circuit outputs 10, the N-bit up-down counter decreases by 1, the threshold detection circuit outputs 11, the N-bit up-down counter remains unchanged, the threshold detection circuit outputs 01, the N-bit up-down counter increases by 1; the N to 2 N The decoder input is connected to the output of the N-bit counter and is used to translate the input N-bit binary code into the corresponding 2 N Bit thermometer code.

[0010] Preferably, the capacitive digital-to-analog converter feedback network includes 2 N A thermometer code capacitance digital-to-analog converter and a feedback capacitor C connected between the negative input terminal and the output terminal of the low noise amplifier f ; said 2 N The 2-bit thermometer code capacitance digital-to-analog converter includes N The capacitor C0, the 2 N The first end of the capacitor C0 is connected to the negative input end of the low noise amplifier, and the two N The second end of the capacitor C0 is connected to 2 N A low reference voltage selection switch connects the low reference voltage V L , respectively through 2 N A high reference voltage selection switch connects the high reference voltage V H , the N to 2 N Decoder output 2 N The two bit thermometer codes are used to control the N The second end of capacitor C0 selects the low reference voltage V L Or high reference voltage V H .

[0011] Preferably, the capacitive digital-to-analog converter feedback network further includes a DC bias feedback resistor R connected between the negative input terminal and the output terminal of the low noise amplifier. f , the DC bias feedback resistor R f Composed of PMOS transistors, R f The resistance value is determined by the size of the PMOS transistor.

[0012] Preferably, the low noise amplifier positive input is a signal input, the low noise amplifier has input and output rail-to-rail capability, and has high intrinsic gain within the allowed input range.

[0013] Preferably, the closed loop gain A of the signal folding amplifier is 2 L is 2 N C0 / C f +1, and the folding step size Delta of the signal folding amplifier is C0 / C f *(V H -V L .

[0014] Preferably, when the signal folding amplifier is reset, the N-bit add-subtract counter is reset to the value 2 N-1 , and the number of thermometer code 0 and 1 output by the N-to-2 N decoder is both 2 N-1 .

[0015] Still another object of the present application is to provide a signal chain circuit of a signal folding amplifier which is simple in design, fast in response, has large allowed input and output amplitudes, is unsaturated, and has large gain.

[0016] To achieve the above object, the present application adopts the technical scheme of a signal chain circuit of a signal folding amplifier based on a capacitive digital-to-analog converter, the first stage using the above signal folding amplifier based on a capacitive digital-to-analog converter, and then cascading a fixed gain amplifier and a low-precision low-effective-bit digital-to-analog converter to amplify and quantize the analog signal.

[0017] The signal folding amplifier based on a capacitive digital-to-analog converter and the signal chain circuit thereof of the present application have the following beneficial effects compared with the prior art: the threshold detection circuit and the anti-saturation circuit are used in the amplifier circuit, and the capacitive digital-to-analog converter controlled by the digital logic circuit is combined, replacing the circuit mechanism in the conventional signal chain which needs multiple modules to prevent saturation of the signal chain; 1, the signal folding amplifier has improved allowed input signal range while maintaining high gain; 2, the signal folding amplifier can detect the output signal in real time, and the corresponding speed is faster; 3, the signal chain circuit using the signal folding amplifier does not need complex gain control circuit, feedback loop and high-precision analog-to-digital converter, which can reduce the design complexity of the entire signal chain and reduce the required area and power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a schematic diagram of a signal chain circuit architecture based on automatic gain control technology.

[0019] Figure 2is a signal chain circuit architecture schematic diagram based on digital-to-analog converter compensation technology.

[0020] Figure 3 is a signal chain circuit architecture schematic diagram based on high-precision analog-to-digital converter.

[0021] Figure 4 is a signal folding amplifier principle block diagram based on capacitive digital-to-analog converter.

[0022] Figure 5 is a signal chain circuit architecture schematic diagram of a signal folding amplifier based on capacitive digital-to-analog converter.

[0023] Figure 6 is a signal folding amplifier principle diagram based on capacitive digital-to-analog converter.

[0024] Figure 7 is a signal folding amplifier capacitive digital-to-analog converter circuit based on capacitive digital-to-analog converter.

[0025] Figure 8 is a signal folding amplifier feedback resistor circuit based on PMOS transistor based on capacitive digital-to-analog converter.

[0026] Figure 9 is an output waveform diagram of a traditional amplifier under large input amplitude.

[0027] Figure 10 is an output waveform diagram of a signal folding amplifier based on capacitive digital-to-analog converter under large input amplitude.

[0028] The reference signs and components involved in the drawings are as follows: 1, low noise amplifier, 11, low noise amplifier positive input, 12, low noise amplifier output, 13, low noise amplifier negative input, 2, threshold detection circuit, 21, high threshold synchronous comparator, 22, low threshold synchronous comparator, 23, high threshold voltage input port, 24, low threshold voltage input port, 3, digital logic circuit, 31, N-bit add-subtract counter, 32, N-to-2 N decoder, 33, digital signal output port, 4, capacitive digital-to-analog converter feedback network, 41, 2 N bit thermometer code capacitive digital-to-analog converter, 411, capacitive array, 412, analog reference voltage selector, 42, low reference voltage input, 43, high reference voltage input, 44, feedback capacitor, 45, feedback resistor, 451, PMOS transistor.

DETAILED DESCRIPTION

[0029] The application will be further described below in conjunction with the embodiments and with reference to the accompanying drawings.

[0030] Embodiment

[0031] The embodiment realizes a signal folding amplifier based on a capacitive digital-to-analog converter.

[0032] The embodiment is simple in design, fast in response, large in allowable input and output amplitudes and large in gain, and the output signal is still not saturated under the condition of large input signal amplitude and large gain.

[0033] The embodiment realizes a signal folding amplifier based on a capacitive digital-to-analog converter, and the output signal is not saturated.

[0034] Figure 4 The embodiment realizes a signal folding amplifier based on a capacitive digital-to-analog converter, and the output signal is not saturated. Figure 4 The embodiment realizes a signal folding amplifier based on a capacitive digital-to-analog converter, and the output signal is not saturated. N The embodiment realizes a signal folding amplifier based on a capacitive digital-to-analog converter, and the output signal is not saturated.

[0035] Figure 5 The embodiment realizes a signal folding amplifier based on a capacitive digital-to-analog converter, and the output signal is not saturated. Figure 5 The embodiment realizes a signal folding amplifier based on a capacitive digital-to-analog converter, and the output signal is not saturated. Figure 1,2,3), which does not pass through the feedback of multiple circuit modules in the signal chain system, reduces the response time; because the signal folding amplifier does not saturate the output voltage while maintaining high gain, the precision of the analog-to-digital converter required by the entire signal chain circuit is reduced; because the output voltage of the signal folding amplifier circuit is set within a specified threshold window, a fixed gain amplifier can be used instead of a programmable gain amplifier, reducing the design difficulty of the system and reducing the area and power consumption requirements of the system.

[0036] Figure 6 A signal folding amplifier based on a capacitive digital-to-analog converter is provided. As shown in the accompanying drawings Figure 6 , the output of the signal folding amplifier based on the capacitive digital-to-analog converter is composed of two parts, namely the analog output of the low noise amplifier 1 and the digital output of the N-bit addition and subtraction counter 31 in the digital logic circuit 3.

[0037] The signal folding amplifier based on the capacitive digital-to-analog converter has a low noise amplifier 1 whose positive input end 11 serves as an analog signal input end; the low noise amplifier 1 circuit has input and output rail-to-rail capability (i.e. the input and output voltages can be any voltage between zero voltage and power supply voltage), and has high intrinsic gain within the allowed input range to ensure the accuracy requirements of the closed-loop gain (A L ) and the signal folding step (Δ). The closed-loop gain (A L ) is determined by the capacitance ratio, and the proportional two-part capacitors are the total capacitance of the capacitor array 411 in the 2 N -bit thermometer code capacitive digital-to-analog converter 41 (2 N C0) and the feedback capacitor 44 (C f ); the closed-loop gain (A L ) of the signal folding amplifier is 2 N C0 / C f +1; the signal folding step (Δ) is determined by the capacitance ratio, and the proportional two-part capacitors are the single capacitor (C0) of the capacitor array 411 in the 2 N -bit thermometer code capacitive digital-to-analog converter 41 and the feedback capacitor 44 (C f ); the signal folding step (Δ) is C0 / C f *(V H -V L ); the low noise amplifier 1 and the capacitive digital-to-analog converter feedback network 4 determine the closed-loop gain (A L ) of the signal folding amplifier, and the signal input to the signal folding amplifier is amplified by a specified closed-loop gain (A LThe other end of the feedback capacitor 44 is connected to the output end 12 of the low-noise amplifier 1.

[0038] Figure 8 A signal folding amplifier based on a capacitive digital-to-analog converter is provided. The signal folding amplifier based on a capacitive digital-to-analog converter comprises a low-noise amplifier 1, a threshold detection circuit 2, a digital logic circuit 3, and a capacitive digital-to-analog converter feedback network 4. The low-noise amplifier 1 comprises a positive input end 11, a negative input end 13, and an output end 12. The threshold detection circuit 2 is connected to the output end 12 of the low-noise amplifier 1. The digital logic circuit 3 is connected to the output end of the threshold detection circuit 2. The capacitive digital-to-analog converter feedback network 4 comprises a DC bias feedback resistor 45 and a feedback capacitor 44. One end of the DC bias feedback resistor 45 is connected to the negative input end 13 of the low-noise amplifier 1, and the other end of the DC bias feedback resistor 45 is connected to the output end 12 of the low-noise amplifier 1. The DC bias feedback resistor 45 is composed of a PMOS transistor 451, and the resistance of the DC bias feedback resistor 45 is determined by the size of the PMOS transistor 451. One end of the feedback capacitor 44 is connected to the negative input end 13 of the low-noise amplifier 1, and the other end of the feedback capacitor 44 is connected to the output end 12 of the low-noise amplifier 1. Figure 8 f

[0039] The threshold detection circuit 2 is composed of two synchronous comparators (a high threshold voltage comparator 21 and a low threshold voltage comparator 22), which are responsible for detecting the high threshold voltage and the low threshold voltage of the threshold window, respectively. The difference between the high threshold voltage and the low threshold voltage is the range of the output of the low-noise amplifier 1. The positive input end of the high threshold voltage comparator 21 is the high threshold voltage input port 23. The negative input end of the low threshold voltage comparator 22 is the low threshold voltage input port 24. The negative input port of the high threshold voltage comparator 21 and the positive input port of the low threshold voltage comparator 22 are connected to the output end 12 of the low-noise amplifier 1. The high threshold voltage comparator 21 and the low threshold voltage comparator 22 are driven by the same clock, and comparison is triggered at the rising edge of the clock.

[0040] The digital logic circuit 3 is connected to the output end of the threshold detection circuit 2, and receives the output of the two comparators in the threshold detection circuit 2. The digital logic circuit 3 comprises an N-bit add-subtract counter 31 and an N-to-2N decoder 32. The output of the threshold detection circuit 2 is input into the N-bit add-subtract counter 31. The output of the N-bit add-subtract counter 31 is input into the N-to-2N decoder 32. The N-to-2N decoder 32 outputs a signal corresponding to the output of the threshold detection circuit 2. N ​​The decoder 32 is composed of the above-mentioned N-bit up-down counter 31. The input end is connected to the output end of the threshold detection circuit 2. According to the output result of the threshold detection circuit 2, three counting modes are generated: up counting (adding one to the original counting result), down counting (subtracting one from the original counting result) and holding the result unchanged (holding the original counting result). The above-mentioned N-bit up-down counter 31 is a synchronous counter and requires a clock signal to drive. The clock signal has the same frequency as the clock that drives the synchronous comparison in the threshold detection circuit 2 (it is a synchronous clock). The above-mentioned N-bit up-down counter 31 is a binary code counter, and its N bit can represent 2 N The above-mentioned N-bit counter 31 has a reset function. When the reset signal is enabled, the counter is reset to the value 2 N-1 ; N to 2 above N The input end of the decoder 32 is connected to the output end of the N-bit counter 31, which can translate the input N-bit binary code into the corresponding 2 N Bit thermometer code.

[0041] The digital logic circuit 3 mentioned above has N to 2 N When the decoder 32 is initially reset, 0 and 1 each account for half; the circuit enters the working state after the reset is completed. Assume N = 2, the counter is 01 when it is initially reset, and the corresponding thermometer code is 2 2 The thermometer code is initially reset to 0011. A 2-bit counter has four possible results: 00, 01, 10, and 11, corresponding to the thermometer codes 0001, 0011, 0111, and 1111, respectively. If the counter is currently 01 and the counter increments by 1, the result after incrementing the counter is 10, and the corresponding thermometer code changes from 0011 to 0111. If the counter is currently 01 and the counter decrements by 1, the result after decrementing the counter is 00, and the corresponding thermometer code changes from 0011 to 0001.

[0042] N to 2 N The decoder combines the N bit input with the 2 N A circuit with one-to-one correspondence between bit outputs. For example, N = 2 bits, and there are four 2-bit inputs: 00, 01, 10, and 11; N The bit outputs are 0001, 0011, 0111 and 1111; that is, the 2-bit number is converted to 2 2 The number of bits. There is no upper limit on the number of capacitors; it depends entirely on the design requirements. If N = 1, there are only two capacitors in the capacitor array.

[0043] Figure 7 This is a signal folding amplifier based on a capacitive digital-to-analog converter. Figure 7 As shown, this embodiment is a signal folding amplifier based on a capacitive digital-to-analog converter, the above 2N The capacitance digital-to-analog converter 41 has a total of 2 N capacitors, wherein the lower plate of each capacitor is connected to the analog reference voltage selector 412, 2 N There are 2 in total in the 41-bit thermometer code capacitance digital-to-analog converter N An analog reference voltage selector 412; the above 2 N The digital signal control terminals of the analog reference voltage selectors 412 are connected to the two N Each thermometer code has a one-to-one correspondence, and each thermometer code serves as a digital signal control input of an analog reference voltage selector 412. N The capacitors in the capacitor array 411 of the thermometer code capacitive digital-to-analog converter 41 have one end connected to the negative input terminal 13 of the low noise amplifier 1, and the other end of each capacitor is connected to an analog reference voltage selector 412; the above-mentioned analog reference voltage selector 412 has an analog signal output terminal and two analog signal input terminals (corresponding to the voltage V H With V L ), a digital signal input terminal (switch selection control digital signal); the above-mentioned analog reference voltage selector 412 can select one of the two voltages of the analog signal input terminal and transmit it to the analog signal output terminal under the control of the input digital signal; the two voltages input by the above-mentioned analog reference voltage selector 412 are respectively the low reference voltage 42 (V L ) and high reference voltage 43(V H ).

[0044] This embodiment is a signal folding amplifier based on a capacitive digital-to-analog converter. Before the signal folding amplifier starts working, the reset signal is enabled to reset the N-bit up-down counter 31 to a value of 2. N-1 , then N to 2 N The thermometer code output by the decoder is 0…01…1 (the number of 0 and 1 is 2 N-1 For example, when N=3, the thermometer code at the initial reset is 00001111, 4 0s corresponding to the control of 4 electrode plates connected to the high reference voltage, and 4 1s corresponding to the control of 4 electrode plates connected to the low reference voltage. ), then 2 N 2 of the capacitance array 411 in the bit thermometer code capacitance digital-to-analog converter 41 N 2 of the capacitors N-1 The lower plate of each capacitor is connected to the high reference voltage 43 (V H ), while the other 2 N-1 The lower plate of each capacitor is connected to a low reference voltage 42 (V L ), the input signal is amplified by 2 N C0 / Cf +1 from the low noise amplifier 1 output terminal 12, as the threshold detection circuit 2 input, when the comparator drive clock to come, high threshold voltage comparator 21 and low threshold voltage comparator 22 to low noise amplifier 1 output terminal 12 judgment, such as low noise amplifier 1 output 12 signal is located within the threshold window, the threshold detection circuit 2 output results for 11, indicating that no threshold, such as low noise amplifier 1 output terminal 12 output exceeds the high threshold voltage, the threshold detection circuit 2 output 10, indicating that the output signal exceeds (higher) set threshold, such as low noise amplifier 1 output terminal 12 output is lower than the low threshold voltage, the threshold detection circuit 2 output 01, indicating that the output signal exceeds (lower) set threshold. N-bit plus-minus counter 31 in digital logic circuit 3 according to the threshold detection circuit 2 output results, in the upward counting (in the original count result plus one), down counting (in the original count result minus one) and keep the result unchanged (keep the original count result) three kinds of counting mode to choose one, if received 11, the counter remains unchanged, if received 01, the counter plus one, if received 10, the calculator minus one. N-bit plus-minus counter 31 calculation results are N to 2 N decoder 32 into the corresponding thermometer code, to control 2 N bit thermometer code capacitor digital-to-analog converter 41 in the capacitor array 411 of the 2 N capacitor lower plate reference voltage, when 2 N bit thermometer code capacitor digital-to-analog converter 4 in any one capacitor array 411 capacitor lower plate by high reference voltage 43 to low reference voltage 42, the low noise amplifier 1 analog output terminal 12 will drop a Δ voltage, when 2 N bit thermometer code capacitor digital-to-analog converter 4 in any one capacitor array 411 capacitor lower plate by low reference voltage 42 to high reference voltage 43, the low noise amplifier 1 analog output terminal 12 will rise a Δ voltage, where Δ voltage for C0 / C f *(V H -V LFor example, when N=2 and the thermometer code is 0011, the corresponding counter result is 01, that is, at this time, two of the four capacitor lower plates are connected to the high reference voltage 43 and two are connected to the low reference voltage 42, that is, at this time (two highs and two lows); when the counter is incremented by one based on 01, the thermometer code becomes 0111, and the corresponding counter result is 10, that is, at this time (three highs and one low), and the capacitance of one capacitor array 411 is converted from the low reference voltage 42 to the high reference voltage 43, so the analog output terminal 12 of the low noise amplifier 1 increases by a Δ voltage; when the counter is decremented by one based on 01, the thermometer code becomes 0001, and the corresponding counter result is 00, that is, at this time (one high and three lows), and the capacitance of one capacitor array 411 is converted from the high reference voltage 43 to the low reference voltage 42, so the analog output terminal 12 of the low noise amplifier 1 decreases by a Δ voltage. In this way, the analog signal output by the low noise amplifier 1 is controlled and always maintained within the set threshold window.

[0045] The present embodiment is a signal folding amplifier based on a capacitive digital-to-analog converter, which uses a threshold detection circuit 2 and an anti-saturation circuit in the amplifier circuit, and combines the capacitive digital-to-analog converter controlled by a digital logic circuit 3, replacing the circuit mechanism in the traditional signal chain circuit that requires multiple modules to cooperate to prevent signal chain saturation; it has the following beneficial effects: 1. While maintaining high gain, the signal folding amplifier also improves its allowable input signal range; 2. The output signal can be detected in real time inside the signal folding amplifier, and its corresponding speed is faster; 3. The signal chain circuit using the signal folding amplifier does not require a complex gain control circuit, a feedback loop and a high-precision analog-to-digital converter, which can reduce the design complexity of the entire signal chain and reduce the required area and power consumption.

[0046] Figure 9 This is the output waveform of a traditional amplifier under large input amplitude. Figure 10 This is a signal folding amplifier based on a capacitive digital-to-analog converter with a large input amplitude. Figure 9 , Attachment Figure 10 As shown in the figure, the waveform of the output signal of the traditional amplifier and the signal folding amplifier is compared when a large amplitude signal is input; Figure 9 It can be seen that the output waveform of the traditional amplifier, its maximum output signal allowed is limited by the power supply voltage, the analog output signal is saturated near the power supply voltage and ground, and an error is introduced between the analog output signal and the ideal output signal, resulting in the loss of some information; Figure 10It can be seen that the output waveform using the signal folding amplifier, the analog output signal is limited to the specified threshold window, and the problem of signal saturation does not occur, avoiding the loss of key information. When the analog output signal is detected to exceed the threshold each time, a delta voltage is added or subtracted to the output signal, pulling the output analog signal back into the threshold window. The delta voltage is determined by the ratio of the capacitance. The digital logic circuit records the application direction of the delta voltage each time. The N-bit digital signal output by the digital logic circuit is combined with the analog signal output by the signal folding amplifier, which can be used for signal reconstruction.

[0047] The above only describes the preferred embodiments of the present application. It should be noted that those skilled in the art can make several improvements and supplements without departing from the principles of the present application. These improvements and supplements should also be considered within the scope of protection of the present application.

Claims

1. A signal folding amplifier based on a capacitive digital-to-analog converter, used for collecting weak useful signals under large amplitude interference signals, characterized in that: The signal folding amplifier comprises a low noise amplifier, a threshold detection circuit, a digital logic circuit and a capacitive digital-to-analog converter feedback network; when the amplitude of the output signal of the low noise amplifier is higher than a high threshold voltage, the threshold detection circuit generates a down signal under the drive of a synchronous clock; when the amplitude of the output signal of the low noise amplifier is between the high threshold voltage and a low threshold voltage, the threshold detection circuit generates a hold signal under the drive of the synchronous clock; when the amplitude of the output signal of the low noise amplifier is lower than the low threshold voltage, the threshold detection circuit generates an up signal under the drive of the synchronous clock; the digital logic circuit counts the down, hold or up signal by minus 1, unchanged or plus 1 under the drive of the synchronous clock to obtain a count signal; the capacitive digital-to-analog converter feedback network is used for feeding back the output signal of the low noise amplifier to the input end of the low noise amplifier, and controlling the output signal of the low noise amplifier to fold the count signal by a folding step length, so that the output signal of the low noise amplifier will not be saturated; the signal folding amplifier output comprises the output signal of the low noise amplifier and the count signal of the digital logic circuit.

2. The signal folding amplifier based on a capacitive digital-to-analog converter according to claim 1, characterized in that: The threshold detection circuit comprises a high threshold comparator for high threshold voltage detection and a low threshold comparator for low threshold voltage detection; the high threshold comparator is connected to the high threshold voltage at the positive input end, the low threshold comparator is connected to the low threshold voltage at the negative input end, and the negative input end of the high threshold comparator and the positive input end of the low threshold comparator are commonly connected to the output end of the low noise amplifier.

3. The signal folding amplifier based on a capacitive digital-to-analog converter according to claim 2, characterized in that: The high threshold comparator and the low threshold comparator are driven by the same clock, and the comparison is triggered at the rising edge of the clock; the down signal generated by the threshold detection circuit is 10, the hold signal is 11, and the up signal is 01.

4. The signal folding amplifier based on a capacitive digital-to-analog converter according to claim 3, characterized in that: The digital logic circuit comprises an N-bit add-subtract counter and an N-to-2 N decoder; the N-bit add-subtract counter is a binary code counter; the clock signal for synchronously counting the N-bit add-subtract counter and the clock signal for synchronously comparing the threshold detection circuit have the same frequency; the input end of the N-bit add-subtract counter is connected with the output end of the threshold detection circuit; when the threshold detection circuit outputs 10, the N-bit add-subtract counter decreases by 1; when the threshold detection circuit outputs 11, the N-bit add-subtract counter remains unchanged; when the threshold detection circuit outputs 01, the N-bit add-subtract counter increases by 1; the N-to-2 N decoder is connected with the output end of the N-bit counter, and is used for translating the input N-bit binary code into the corresponding 2 N bit's thermometer code.

5. The signal folding amplifier based on a capacitive digital-to-analog converter according to claim 4, characterized in that: The capacitive digital-to-analog converter feedback network includes 2 N A thermometer code capacitance digital-to-analog converter and a feedback capacitor C connected between the negative input terminal and the output terminal of the low noise amplifier f ; said 2 N The 2-bit thermometer code capacitance digital-to-analog converter includes N The capacitor C0, the 2 N The first end of the capacitor C0 is connected to the negative input end of the low noise amplifier, and the two N The second end of the capacitor C0 is connected to 2 N A low reference voltage selection switch connects the low reference voltage V L , respectively through 2 N A high reference voltage selection switch connects the high reference voltage V H , the N to 2 N Decoder output 2 N The two bit thermometer codes are used to control the N The second end of capacitor C0 selects the low reference voltage V L Or high reference voltage V H .

6. The signal folding amplifier based on a capacitive digital-to-analog converter according to claim 5, characterized in that: The capacitive digital-to-analog converter feedback network further comprises a DC bias feedback resistor R f , connected in series between the low noise amplifier negative input and the output f The DC bias feedback resistor R f is composed of a PMOS transistor, and the resistance value is determined by the size of the PMOS transistor.

7. The signal folding amplifier based on a capacitive digital-to-analog converter according to claim 5, characterized in that: The positive input end of the low noise amplifier is the signal input end, the low noise amplifier has input and output rail-to-rail capability, and has high intrinsic gain within the allowed input range.

8. The signal folding amplifier based on a capacitive digital-to-analog converter according to claim 7, characterized in that: The closed loop gain A of the signal folding amplifier L is 2 N C0 / C f +1; the folding step size Delta of the signal folding amplifier is C0 / C f *(V H -V L ).

9. The signal folding amplifier based on a capacitive digital-to-analog converter according to claim 8, characterized in that: The signal folding amplifier is reset, and the N-bit add-subtract counter is reset to 2 N-1 The number of thermometer code 0 and 1 output by the decoder is 2 N N-1 each.​ 10. A signal chain circuit for a signal folding amplifier based on a capacitive digital-to-analog converter, characterized by: The first stage uses the capacitive digital-to-analog converter-based signal folding amplifier described in any one of claims 1 to 9, and then cascades a fixed gain amplifier and a low-precision low effective bit digital-to-analog converter to amplify and quantize the analog signal.

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