High-isolation undersampling phase detector and undersampling phase-locked loop
By introducing two sampling paths and a voltage holder into the undersampled phase detector, combined with a fixed resistor, the problem of insufficient isolation in the prior art is solved, and a phase-locked loop design with high isolation and low complexity is realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-09-29
- Publication Date
- 2026-03-31
AI Technical Summary
Existing charge-sampling undersampled phase detectors require a three-stage structure to increase the isolation between them and the voltage-controlled oscillator, which increases implementation complexity and chip power consumption.
The system employs a structure with two main sampling paths and two dummy sampling paths. The main sampling path and the dummy sampling path are controlled to sample alternately by a clock generation circuit. Combined with a voltage holder and a fixed resistor, the impact on the VCO load capacitance is reduced.
It improves the isolation between the sampler and the VCO, reduces design complexity and power consumption, enhances the linearity of the phase detector, and reduces reference spurious signals in the PLL loop.
Smart Images
Figure CN115459765B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of phase-locked loop technology, and more specifically, to a high-isolation undersampled phase detector and an undersampled phase-locked loop. Background Technology
[0002] Undersampled phase-locked loops (PLLs) can effectively compress in-band noise, resulting in a high-purity output clock signal. The structure of an undersampled PLL is as follows: Figure 1 As shown, the undersampling phase detector, as a core module of the undersampling phase-locked loop, directly samples the voltage-controlled oscillator. The sampling process causes changes in the oscillator's load capacitance. LC (capacitor-inductor) type voltage-controlled oscillators are quite sensitive to changes in their load capacitance. Therefore, the undersampling phase detector needs to meet a certain degree of isolation.
[0003] Undersampled phase detectors can be divided into two types: voltage sampling and charge sampling. Unlike voltage samplers, charge samplers do not directly sample at the zero-crossing point of the VCO (Voltage-Controlled Oscillator) output signal. Instead, they convert the VCO output signal into a current signal over a period of time and integrate this current signal across a capacitor, i.e., charge sampling. Compared to voltage sampling structures, charge sampling structures can better reduce the impact on the VCO, resulting in a cleaner VCO output signal. Existing charge sampling type undersampled phase detectors include... Figure 2 As shown.
[0004] The principle of the existing charge sampling undersampled phase detector: The charge sampling undersampled phase detector can be divided into three stages. The first stage directly samples the VCO output, and the sampling result is stored on CS1. The second stage has the same structure as the first stage and is mainly used to further isolate the third stage from the VCO. The third stage holds the output signal of the second stage, thereby ensuring that the sampling result remains unchanged within a reference clock cycle.
[0005] The timing sequence of the charge sampling undersampled phase detector is as follows: Figure 3 As shown, when φrst is high, switches S1 and S4 are off, and switches S2, S3, S5, and S6 are on, setting the differential outputs of the first and second stage samplers to VDD. When φref is high, switches S1 and S4 are on, and switches S2, S3, S5, and S6 are off. The first and second stage samplers convert the input differential signal into a current signal to charge and discharge capacitors CS1 and CS2, i.e., perform charge sampling. When φrs is high, switches S7 and S8 are on, and the second-stage sampling result is transmitted to CS3 through switches S7 and S8, remaining unchanged for one input reference clock cycle.
[0006] For the first-stage sampler, when switches S2 and S3 are off, sampling capacitors CS1 and CS2 will respectively interact with the gate-drain capacitances C of M1 and M2.GD The capacitors are connected in series, forming part of the capacitor in the LC oscillator. When switches S2 and S3 are turned on, the sampling capacitor C... S1 and C S2 Switches S2 and S3 will be bypassed. Therefore, the VCO's oscillation frequency will change periodically, generating reference spurious signals at the undersampled PLL output. Existing charge-sampling undersampled phase detectors require a three-stage structure to increase isolation from the VCO, increasing implementation complexity and chip power consumption / area. Summary of the Invention
[0007] To address the shortcomings of existing technologies, the purpose of this invention is to provide a high-isolation undersampled phase detector and an undersampled phase-locked loop.
[0008] A high-isolation undersampled phase detector according to the present invention includes: a charge sampler and a clock generation circuit. The charge sampler includes two main sampling paths and two dummy sampling paths. The two main sampling paths are respectively connected to the VCON acquisition terminal and the VCOP acquisition terminal of the differential output voltage signal of a voltage-controlled oscillator. The output terminal of the main sampling path outputs differential voltage signals outp and outn. The two dummy sampling paths are respectively connected to the VCON acquisition terminal and the VCOP acquisition terminal. The clock generation module is connected to the main sampling paths and the dummy sampling paths, and outputs a clock control signal to cause the main sampling paths and the dummy sampling paths to alternately sample the differential output voltage signal of the oscillator.
[0009] Preferably, the main sampling path includes MOSFETs M1, M2, and M3, and capacitor Cs1. The gate of MOSFET M1 is connected to the differential output voltage signal of a voltage-controlled oscillator. The source of MOSFET M1 is grounded. The drain of MOSFET M1 is connected to the source of MOSFET M2. The drain of MOSFET M2 is connected to the source of MOSFET M3, one end of capacitor Cs1, and a voltage holder. The other end of capacitor Cs1 is grounded. The drain of MOSFET M3 is connected to VDD. The gate of MOSFET M2 is connected to a clock generation circuit. The gate of MOSFET M3 is also connected to a clock generation circuit.
[0010] The dummy sampling path includes MOSFET M4, MOSFET M5, and capacitor Cs2. The source of MOSFET M4 is connected to the drain of MOSFET M1. The drain of MOSFET M4 is connected to the source of MOSFET M5 and one end of capacitor Cs2. The other end of capacitor Cs2 is grounded. The drain of MOSFET M5 is connected to VDD. The gate of MOSFET M5 is connected to the clock generation circuit. The gate of MOSFET M4 is connected to the clock generation circuit. Capacitors Cs1 and Cs2 have the same capacitance.
[0011] Preferably, it further includes a voltage holder, the output of the main sampling path is connected to the input of the voltage holder, and the output of the voltage holder outputs differential voltage signals outp and outn.
[0012] Preferably, the voltage holder includes MOSFETs M6, M7, M8, and M9, resistors R0 and R1, and capacitor Cs3. The gate of MOSFET M6 is connected to the gate of MOSFET M9 and the drain of MOSFET M2. The source of MOSFET M6 is grounded. The drain of MOSFET M6 is connected to the source of MOSFET M7. The drain of MOSFET M7 is connected to one end of resistor R0. The other end of resistor R0 is connected to one end of resistor R1 and one end of capacitor Cs3. The other end of resistor R1 is connected to the source of MOSFET M8. The drain of MOSFET M8 is connected to the source of MOSFET M9. The gate of MOSFET M7 is connected to a clock generation circuit. The gate of MOSFET M8 is connected to a clock generation circuit. One end of capacitor Cs3 is the differential voltage signal output terminal, and the other end of capacitor Cs3 is grounded.
[0013] Preferably, the main sampling path further includes a resistor R2, and the dummy sampling path further includes a resistor R3. The resistor R2 replaces the MOS transistor M3, and the resistor R3 replaces the MOS transistor M5. One end of the resistor R2 is connected to the drain of the MOS transistor M2, and the other end of the resistor R2 is connected to VDD. One end of the resistor R3 is connected to the drain of the MOS transistor M4, and the other end of the resistor R3 is connected to VDD.
[0014] Preferably, the clock generation circuit generates signals φrst, φref, φrs, φref_bar, and φrs_bar, respectively. φrst and φref are high-level non-overlapping clock signals, φref_bar is the complementary clock signal of φref, φrs is a high-level non-overlapping clock signal of φref and φrst, and φrs_bar is the complementary clock signal of φrs. The φrst signal is input to the gate of MOSFET M3, the φref signal is input to the gate of MOSFET M2, the φrs signal is input to the gate of MOSFET M7, the φref_bar signal is input to the gates of MOSFETs M4 and M5, and the φrs_bar signal is input to the gate of MOSFET M8.
[0015] Preferably, the clock generation circuit includes a first NOT gate, a first NAND gate, a second NAND gate, a first delay module, a second delay module, a second NOT gate, a third NOT gate, a fourth NOT gate, a delay chain D1, a fifth NOT gate, a sixth NOT gate, a third NAND gate, a delay chain D2, a seventh NOT gate, a fourth NAND gate, a first NOR gate, and an eighth NOT gate.
[0016] The input of the first NOT gate is connected to one input of the second NAND gate, the output of the first NOT gate is connected to one input of the first NAND gate, the output of the first NAND gate is connected to the input of the first delay module, the output of the second NAND gate is connected to the input of the second delay module, the output of the first delay module is connected to the input of the second NOT gate and the other input of the second NAND gate, the output of the second delay module is connected to the input of the third NOT gate and the other input of the first NAND gate, the output of the third NOT gate is connected to the input of the fourth NOT gate, and the output of the second NOT gate is connected to the input of delay chain D1. One input of the third NAND gate and one input of the sixth NOT gate; the output of delay chain D1 is connected to the input of the fifth NOT gate; the output of the fifth NOT gate is connected to the other input of the third NAND gate; the output of the third NAND gate is connected to the input of delay chain D2 and one input of the fourth NAND gate; the output of delay chain D2 is connected to the input of the seventh NOT gate; the output of the seventh NOT gate is connected to the other input of the fourth NAND gate; the output of the fourth NAND gate is connected to one input of the first NOR gate; the output of the sixth NOT gate is connected to the other input of the first NOR gate; and the output of the first NOR gate is connected to the input of the eighth NOT gate.
[0017] The input terminal of the first NOT gate receives the ref signal, the output terminal of the third NOT gate outputs the φrs signal, the output terminal of the fourth NOT gate outputs the φrs_bar signal, the output terminal of the third NAND gate outputs the φrst signal, the output terminal of the first NOR gate outputs the φref signal, and the output terminal of the eighth NOT gate outputs the φref_bar signal.
[0018] The present invention provides an undersampled phase-locked loop, comprising the high-isolation undersampled phase detector described above.
[0019] Compared with the prior art, the present invention has the following beneficial effects:
[0020] 1. This invention adds a dummy path to the main sampling path, thereby ensuring that during sampling capacitor switching, the input transistor gate-drain capacitance C is maintained. GD The capacitance value coupled to the VCO load remains unchanged, thereby increasing the isolation between the sampler and the VCO.
[0021] 2. In this invention, the input signal is directly connected to the gate terminal of the voltage holder's input transistor. When the clock signal controls the voltage holder to switch between follow and hold states, the change in load capacitance will be coupled to the input terminal through the gate-drain capacitance of the input transistor. In contrast, with traditional voltage holders, the change in load capacitance is directly reflected at the input terminal. Therefore, compared to traditional structures, this structure can further enhance the isolation between the voltage holder and the VCO.
[0022] 3. The output node of the voltage holder is connected in series with a fixed resistor, so that the output impedance is mainly contributed by the fixed resistor. This reduces the nonlinear effect of the output impedance change due to the change of MOSFET state, and improves the linearity of the voltage holder's input-output transfer characteristic curve and the phase detector.
[0023] 4. Because the second-stage voltage holder in this invention has good isolation performance, only two stages are needed to achieve the sample-and-hold function. Compared with the traditional three-stage structure, this reduces the design complexity. Attached Figure Description
[0024] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:
[0025] Figure 1 Here is a block diagram of the SS-PLL structure in the prior art;
[0026] Figure 2 This is based on the existing charge sampling type undersampling phase detector structure;
[0027] Figure 3 This is a timing diagram of a charge-sampling type undersampled phase detector in the prior art;
[0028] Figure 4 This is a structural diagram of the charge sampling type undersampling phase detector disclosed in this invention;
[0029] Figure 5 This invention discloses a single-ended structure for a charge sampling type undersampled phase detector.
[0030] Figure 6 This is a timing diagram of the charge sampling type undersampling phase detector disclosed in this invention;
[0031] Figure 7 This is a circuit diagram of the clock generation system disclosed in this invention;
[0032] Figure 8 This is a structural diagram of the second type of charge sampling undersampling phase detector disclosed in this invention;
[0033] Figure 9 The timing sequence and generation circuit required for the second phase detector disclosed in this invention are shown.
[0034] Explanation of reference numerals in the attached figures:
[0035] First NOT gate 1, Fifth NOT gate 9
[0036] First NAND gate 2, Sixth NOT gate 10
[0037] Second NAND gate 3; Third NAND gate 11
[0038] First delay module 4, seventh NOT gate 12
[0039] Second Delay Module 5 Fourth NAND Gate 13
[0040] Second NOT gate 6; First NOR gate 14
[0041] Third NOT gate 7, Eighth NOT gate 15
[0042] Fourth NOT gate 8 Detailed Implementation
[0043] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.
[0044] Example 1
[0045] This invention discloses a high-isolation undersampling phase detector, the overall structure of which is as follows: Figure 4 As shown, the overall structure is differential. The inputs are the differential output voltage signals VCOP and VCON of the VCO, and the outputs are the differential voltage signals outp and outn. The overall structure consists of three parts: the first part is the first stage of the phase detector: a charge sampler; the second part is the second stage of the phase detector: a voltage holder; and the third part is the clock generation circuit of the phase detector.
[0046] Specifically, the charge sampler includes two main sampling paths and two dummy sampling paths. The two main sampling paths are connected to the VCON and VCOP acquisition terminals of the differential output voltage signal of the voltage-controlled oscillator, respectively. The output terminal of the main sampling path is connected to a voltage holder. The two dummy sampling paths are connected to the VCON and VCOP acquisition terminals, respectively. The clock generation module is connected to the main sampling paths and the dummy sampling paths, and outputs a clock control signal to make the main sampling paths and the dummy sampling paths alternately sample the differential output voltage signal of the oscillator.
[0047] For ease of analysis, we will discuss the single-ended structure of this invention, including the novel charge-sampling undersampled phase detector single-ended structure and timing control, as follows: Figure 5 , Figure 6 As shown.
[0048] The main sampling path includes MOSFETs M1, M2, and M3, and capacitor Cs1. The gate of MOSFET M1 is connected to the differential output voltage signal of the voltage-controlled oscillator. The source of MOSFET M1 is grounded. The drain of MOSFET M1 is connected to the source of MOSFET M2. The drain of MOSFET M2 is connected to the source of MOSFET M3, one end of capacitor Cs1, and the voltage holder. The other end of capacitor Cs1 is grounded. The drain of MOSFET M3 is connected to VDD. The gate of MOSFET M2 is connected to the clock generation circuit. The gate of MOSFET M3 is also connected to the clock generation circuit.
[0049] The dummy sampling path includes MOSFETs M4 and M5, and capacitor Cs2. The source of MOSFET M4 is connected to the drain of MOSFET M1. The drain of MOSFET M4 is connected to the source of MOSFET M5 and one end of capacitor Cs2. The other end of capacitor Cs2 is grounded. The drain of MOSFET M5 is connected to VDD. The gate of MOSFET M5 is connected to the clock generation circuit. The gate of MOSFET M4 is connected to the clock generation circuit. Capacitors Cs1 and Cs2 have the same specifications.
[0050] The voltage holder includes MOSFETs M6, M7, M8, and M9, resistors R0 and R1, and capacitor Cs3. The gate of MOSFET M6 is connected to the gate of MOSFET M9 and the drain of MOSFET M2. The source of MOSFET M6 is grounded. The drain of MOSFET M6 is connected to the source of MOSFET M7. The drain of MOSFET M7 is connected to one end of resistor R0. The other end of resistor R0 is connected to one end of resistor R1 and one end of capacitor Cs3. The other end of resistor R1 is connected to the source of MOSFET M8. The drain of MOSFET M8 is connected to the source of MOSFET M9. The gates of MOSFETs M7 and M8 are connected to the clock generation circuit. One end of capacitor Cs3 is the differential voltage signal output terminal, and the other end of capacitor Cs3 is grounded. The voltage holder has two sets of outputs, which output differential voltage signals outp and outn respectively.
[0051] like Figure 7As shown, the clock generation circuit generates signals φrst, φref, φrs, φref_bar, and φrs_bar respectively. φrst and φref are high-level non-overlapping clock signals, φref_bar is the complementary clock signal of φref, φrs is the high-level non-overlapping clock of φref and φrst, and φrs_bar is the complementary clock signal of φrs. The φrst signal is input to the gate of MOSFET M3, φref is input to the gate of MOSFET M2, φrs is input to the gate of MOSFET M7, φref_bar is input to the gates of MOSFETs M4 and M5, and φrs_bar is input to the gate of MOSFET M8.
[0052] Specifically, the clock generation circuit includes a first NOT gate 1, a first NAND gate 2, a second NAND gate 3, a first delay module 4, a second delay module 5, a second NOT gate 6, a third NOT gate 7, a fourth NOT gate 8, a delay chain D1, a fifth NOT gate 9, a sixth NOT gate 10, a third NAND gate 11, a delay chain D2, a seventh NOT gate 12, a fourth NAND gate 13, a first NOR gate 14, and an eighth NOT gate 15;
[0053] The input of the first NOT gate 1 is connected to one input of the second NAND gate 3. The output of the first NOT gate 1 is connected to one input of the first NAND gate 2. The output of the first NAND gate 2 is connected to the input of the first delay module 4. The output of the second NAND gate 3 is connected to the input of the second delay module 5. The output of the first delay module 4 is connected to the input of the second NOT gate 6 and the other input of the second NAND gate 3. The output of the second delay module 5 is connected to the input of the third NOT gate 7 and the other input of the first NAND gate 2. The output of the third NOT gate 7 is connected to the input of the fourth NOT gate 8. The output of the second NOT gate 6 is connected to the input of the delay chain D1, one input of the third NAND gate 11, and the input of the sixth NOT gate 10. The output of the delay chain D1 is connected to the input of the fifth NOT gate 9. The output of the fifth NOT gate 9 is connected to the other input of the third NAND gate 11. The output of the third NAND gate 11 is connected to the input of the delay chain D2 and one input of the fourth NAND gate 13. The output of the delay chain D2 is connected to the input of the seventh NOT gate 12. The output of the seventh NOT gate 12 is connected to the other input of the fourth NAND gate 13. The output of the fourth NAND gate 13 is connected to one input of the first NOR gate 14. The output of the sixth NOT gate 10 is connected to the other input of the first NOR gate 14. The output of the first NOR gate 14 is connected to the input of the eighth NOT gate 15.
[0054] The input terminal of the first NOT gate 1 receives the ref signal, the output terminal of the third NOT gate 7 outputs the φrs signal, the output terminal of the fourth NOT gate 8 outputs the φrs_bar signal, the output terminal of the third NAND gate 11 outputs the φrst signal, the output terminal of the first NOR gate 14 outputs the φref signal, and the output terminal of the eighth NOT gate 15 outputs the φref_bar signal.
[0055] The principles of the phase detector will be explained in the following sections, which will consist of the first stage, the second stage, and the clock generation circuit.
[0056] 1. Charge Sampler: The input is the VCO output signal. The first-stage charge sampler directly samples the charge of the VCO output signal, and the sampling result is stored in the sampling capacitor C. S1 Above. MOSFETs M1, M2, and M3, capacitor C. S1 This forms the main path for the first-stage charge sampling, consisting of MOSFETs M1, M4, and M5, and capacitor C. S2 This forms the dummy path for charge sampling. The dummy path consists of MOSFET M4, MOSFET M5, and capacitor C. S2 The specifications and capacitance values of the MOSFETs are respectively related to those of MOSFETs M2 and M3 in the main path, and capacitor C. S1 The MOSFET specifications and capacitor values are equal. The φrst and φref controlling the first-stage charge sampler are high-level non-overlapping clock signals, and φref_bar is the complementary clock signal to φref. The addition of the dummy path is mainly to reduce the C in the original structure. S1 The impact of capacitor switching on the VCO load capacitance. The first-stage charge sampling process can be divided into three states, namely phases φ1, φ2, and φ3.
[0057] In phase φ1, φref is low, φrst is high, φref_bar is high, MOSFETs M2, M3, and M5 are off, MOSFET M4 is on, and capacitor C... S2 Parasitic capacitance C of MOSFET M1 GD They are connected in series to form part of the VCO load capacitor.
[0058] At phase φ2, φref is low, φrst is low, and φref_bar is high; MOSFETs M3 and M4 are turned on, and capacitor C... S1 Set to VDD, capacitor C S2 The parasitic capacitance C of MOSFET M1 GD They are connected in series to form part of the VCO load capacitor.
[0059] At phase φ3, φref is high, φrst is high, and φref_bar is low. MOSFETs M2 and M5 are turned on, while MOSFETs M3 and M4 are turned off. Capacitor C... S2 Set to VDD, capacitor C S1 The gate-drain capacitance C of MOSFET M1 GD They are connected in series to form part of the VCO load capacitor.
[0060] In summary, when the first-stage circuit switches between the three phases φ1, φ2, and φ3, there will always be a sampling capacitor C. S1 or capacitor C S2 and the gate-drain capacitance C of MOSFET M1 GD The first-stage circuit proposed in this invention can effectively reduce the impact of the sampling process on the VCO by connecting the components in series to form part of the VCO load capacitor.
[0061] 2. Voltage Holder: The input is the output signal of the first-stage charge sampler, connected to MOSFETs M6 and M9 respectively. The clock φrs controlling the second-stage voltage holder is a high-level non-overlapping clock of φref and φrst, and φrs_bar is the complementary clock signal of φrs. The second-stage voltage holder holds the sampled output signal of the first stage, thus ensuring that the phase detector output remains unchanged within one input reference clock cycle. The operation of the second-stage voltage holder can be divided into two operating states, phases φ4 and φ5.
[0062] In the first phase φ4, the voltage holder is in follower mode. At this time, φrs is high, φrs_bar is low, MOSFETs M7 and M8 are turned on, and the voltage is held in capacitor C. S1 The voltage signal on the capacitor C will be converted into a current signal by MOSFETs M6 and M9. S3 During charging and discharging, since φref and φrst are low when φrs is high, C S1 The voltage signal on the capacitor C remains unchanged. Therefore, when MOSFETs M6 and M9 are connected to capacitor C... S3 After the charging and discharging reaches a stable state, C S3 The voltage signal on it will remain unchanged.
[0063] In the second phase φ5, the voltage holder is in the holding state. At this time, φrs is low, φrs_bar is high, MOSFETs M7 and M8 are off, and capacitor C... S3 The voltage signal on the circuit will remain unchanged when φrs is high until φrs changes from low to high again, at which point the second-stage voltage holder will re-enter phase φ4.
[0064] MOSFETs M6 and M9 isolate the output of the first stage from the sampling capacitor C. S2 That is, the sampling capacitor C S2 The sampling capacitor needs to be connected in series with the gate-drain capacitors of MOSFETs M6 and M9 to reflect the output of the first stage. Therefore, compared with the original third-stage hold circuit, the second-stage hold circuit proposed in this invention can better isolate the sampling capacitor and VCO.
[0065] Resistors R0 / R1 are connected in series with MOSFETs M7 and M8. When M7 / M8 is turned on, the output impedance of the voltage holder is mainly contributed by resistors R0 / R1, which is a fixed resistor. When M7 / M8 operates in different states, its output impedance exhibits significant nonlinearity. The addition of R0 / R1 reduces this nonlinearity and improves the linearity of the voltage holder's input-output voltage transfer characteristic curve, thus resulting in higher linearity for the entire charge sampling phase detector. In addition, resistor R0 can suppress the clock feedthrough effect caused by the gate clock switching of MOSFETs M7 and M8, thereby reducing PLL loop reference spurious signals.
[0066] 3. Clock generation circuit: The clock generation circuit is as follows... Figure 6 As shown, the input ref signal generates a high-level non-overlapping clock. One path generates φrs and φrs_bar, while the other path, through module two, generates a signal φrst with a duty cycle of (1-A), where the value of A is proportional to the sum of the delays of delay chain D1 and the inverter. Then, φrst, through module two, generates a signal φref_bar with a duty cycle of (1-B) and its inverted signal, where the value of B is proportional to the sum of the delays of delay chain D2 and the inverter. φrst, φref, and φref_bar will act on the first-stage charge sampler, while φrs and φrs_bar will act on the second-stage voltage holder. The red module is added to ensure that φref and φrs are high-level non-overlapping clocks; that is, when φrs is about to transition from low to high, φref is forcibly set to GND.
[0067] Compared with existing charge sampling type undersampling phase detectors, the phase detector disclosed in this embodiment has the following advantages:
[0068] a. For the charge sampler, a dummy path is added to the main sampling path to ensure that during sampling capacitor switching, the input transistor gate-drain capacitance C is used. GD The capacitance value coupled to the VCO load remains unchanged, thereby increasing the isolation between the sampler and the VCO.
[0069] b. For a voltage latch, the input signal is directly connected to the gate of the latch's input transistor. When the clock signal controls the voltage latch to switch between follow and hold states, changes in the load capacitance will be coupled to the input terminal through the gate-drain capacitance of the input transistor. In contrast, with a traditional voltage latch, changes in load capacitance are directly reflected at the input terminal. Therefore, compared to the traditional structure, this structure can further enhance the isolation between the latch and the VCO.
[0070] c. In the voltage holder, the output node is connected in series with a fixed resistor, so that the output impedance is mainly contributed by the fixed resistor. This reduces the nonlinear effect of the output impedance change due to the change of MOSFET state, and improves the linearity of the voltage holder's input-output transfer characteristic curve and the phase detector.
[0071] d. Because the second-stage voltage holder has better isolation performance, only two stages are needed to achieve the sample-and-hold function. Compared with the traditional three-stage structure, this reduces the design complexity.
[0072] Example 2
[0073] This embodiment serves as a parallel alternative to Embodiment 1.
[0074] Reference Figure 8 As shown, in this embodiment, the voltage holder is removed, and resistors R2 and R3 are added. MOSFET M3 is replaced by resistor R2, and MOSFET M5 is replaced by resistor R3. One end of resistor R2 is connected to the drain of MOSFET M2, and the other end is connected to VDD. One end of resistor R3 is connected to the drain of MOSFET M4, and the other end is connected to VDD. φref and φref_bar are complementary signals. C S1 and C S2 They are equal, R2 and R3 are equal, and R 2,3 *C S1,2 >>1 / ω vco ω vco This refers to the angular frequency of the VCO output signal. The operation of this scheme can be divided into two phases, which will be explained in the following sections.
[0075] In the first phase, when φref is high and φref_bar is low, M2 is on, M4 is off, the main sampling path is open, and the dummy path is off. Capacitor C S1 Because the gate-drain capacitances of M2 and M1 are connected in series, due to R 2,3 *C S1,2 >>1 / ω vco In the first phase, the VCO's output voltage will be converted into current through M1 and applied to capacitor C. S1 Integrate, and R2 with respect to C S1The effect is negligible. In the second phase, φref is low and φref_bar is high, M2 is off, M4 is on, the main sampling path is off, and the dummy path is on. Capacitor C S2 By connecting the gate-drain capacitors of M4 and M1 in series, the impact of switch switching on the VCO load capacitance during sampling is reduced, thus reducing reference spurious signals. Due to the time constant R... 2,3 *C S1,2 (>>1 / ω vco The capacitance C is very large; even if the main sampling path is turned off, the capacitance C... S1 The change in the sampled differential voltage value remains very small, meaning the phase information obtained by the phase detector will remain unchanged. Therefore, this scheme does not require a voltage holder, further reducing circuit complexity.
[0076] The required timing sequence and its timing generation circuit are as follows: Figure 9 As shown, after the rising edge of the ref signal arrives, a pulse signal φref with a duty cycle of C will be generated. The value of the duty cycle C is proportional to the value of the delay D3. After passing through an inverter, φref can be used to obtain the φref_bar signal.
[0077] The charge sampler disclosed in this embodiment adds a dummy path to the original sampling path to ensure that capacitor switching during sampling does not affect the VCO load capacitor, thereby improving the isolation between the sampling capacitor and the VCO. Due to the time constant R... 2,3 *C S1,2 (>>1 / ω vco The capacitance C is very large, so even if the main sampling path is disconnected, the capacitance C... S1,2 The difference in voltage value is also very small. Therefore, the parallel replacement scheme only requires one stage of circuitry to complete the sample-and-hold function, reducing the design complexity.
[0078] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.
Claims
1. A high-isolation undersampling phase detector, comprising: The application relates to a charge sampler and a clock generation circuit, wherein the charge sampler comprises two main sampling channels and two dummy sampling channels, the two main sampling channels are connected with a VCON collection end and a VCOP collection end of a differential output voltage signal of a voltage-controlled oscillator respectively, the main sampling channel outputs a differential voltage signal outp and outn, the two dummy collection channels are connected with the VCON collection end and the VCOP collection end respectively, and the clock generation module is connected with the main sampling channel and the dummy sampling channel and outputs a clock control signal to make the main sampling channel and the dummy sampling channel alternately sample the differential output voltage signal of the oscillator. The main sampling channel comprises MOS tubes M1, M2, M3 and a capacitor Cs1, the gate of the MOS tube M1 is connected with the differential output voltage signal of the voltage-controlled oscillator, the source of the MOS tube M1 is grounded, the drain of the MOS tube M1 is connected with the source of the MOS tube M2, the drain of the MOS tube M2 is connected with the source of the MOS tube M3, one end of the capacitor Cs1 and a voltage keeper, the other end of the capacitor Cs1 is grounded, the drain of the MOS tube M3 is connected with VDD, the gate of the MOS tube M2 is connected with the clock generation circuit, and the gate of the MOS tube M3 is connected with the clock generation circuit. The dummy sampling channel comprises MOS tubes M4, M5 and a capacitor Cs2, the source of the MOS tube M4 is connected with the drain of the MOS tube M1, the drain of the MOS tube M4 is connected with the source of the MOS tube M5 and one end of the capacitor Cs2, the other end of the capacitor Cs2 is grounded, the drain of the MOS tube M5 is connected with VDD, the gate of the MOS tube M5 is connected with the clock generation circuit, the gate of the MOS tube M4 is connected with the clock generation circuit, and the capacitor Cs1 and the capacitor Cs2 have the same capacity. The application further comprises a voltage keeper, the output end of the main sampling channel is connected with the input end of the voltage keeper, and the voltage keeper outputs the differential voltage signal outp and outn.
2. The high-isolation undersampling phase detector of claim 1, wherein: The voltage keeper comprises MOS tubes M6, M7, M8, M9, resistors R0 and R1 and a capacitor Cs3, the gate of the MOS tube M6 is connected with the gate of the MOS tube M9 and the drain of the MOS tube M2 respectively, the source of the MOS tube M6 is grounded, the drain of the MOS tube M6 is connected with the source of the MOS tube M7, the drain of the MOS tube M7 is connected with one end of the resistor R0, the other end of the resistor R0 is connected with one end of the resistor R1 and one end of the capacitor Cs3, the other end of the resistor R1 is connected with the source of the MOS tube M8, the drain of the MOS tube M8 is connected with the source of the MOS tube M9, the gate of the MOS tube M7 is connected with the clock generation circuit, the gate of the MOS tube M8 is connected with the clock generation circuit, one end of the capacitor Cs3 is a differential voltage signal output end, and the other end of the capacitor Cs3 is grounded.
3. The high-isolation undersampling phase detector of claim 2, wherein: 4. The high-isolation undersampling phase detector of claim 1, wherein: The main sampling path further comprises a resistor R2, the dummy sampling path further comprises a resistor R3, the resistor R2 replaces the MOS transistor M3, the resistor R3 replaces the MOS transistor M5, one end of the resistor R2 is connected to the drain of the MOS transistor M2, the other end of the resistor R2 is connected to VDD, one end of the resistor R3 is connected to the drain of the MOS transistor M4, and the other end of the resistor R3 is connected to VDD.
5. The high-isolation undersampling phase detector of claim 1, wherein: The clock generating circuits respectively generate rst、 ref、 rs、 ref_bar and The rs_bar signal, the rst and The ref signals are high-level, non-overlapping clock signals. ref_bar is The complementary clock signal of ref, rs is ref、 rst is a high-level non-overlapping clock. rs_bar is The complementary clock signal of rs, the The rst signal is input to the gate of MOS transistor M3, the The ref input is the gate of MOS transistor M2, the The rs signal is input to the gate of MOS transistor M7, the The ref_bar signal is input to the gate of MOS transistor M4 and the gate of MOS transistor M5. The rs_bar signal is input to the gate of MOSFET M8.
6. The high-isolation undersampling phase detector of claim 5, wherein: The clock generating circuit comprises a first NAND gate, a first NAND gate, a second NAND gate, a first delay module, a second delay module, a second NAND gate, a third NAND gate, a fourth NAND gate, a delay chain D1, a fifth NAND gate, a sixth NAND gate, a third NAND gate, a delay chain D2, a seventh NAND gate, a fourth NAND gate, a first NOR gate, and an eighth NAND gate; The input end of the first NAND gate is connected to one input end of the second NAND gate, the output end of the first NAND gate is connected to one input end of the first NAND gate, the output end of the first NAND gate is connected to the input end of the first delay module, the output end of the second NAND gate is connected to the input end of the second delay module, the output end of the first delay module is connected to the input end of the second NAND gate and the other input end of the second NAND gate, the output end of the second delay module is connected to the input end of the third NAND gate and the other input end of the first NAND gate, the output end of the third NAND gate is connected to the input end of the fourth NAND gate, the output end of the second NAND gate is connected to the input end of the delay chain D1, one input end of the third NAND gate, and the input end of the sixth NAND gate, the output end of the delay chain D1 is connected to the input end of the fifth NAND gate, the output end of the fifth NAND gate is connected to the other input end of the third NAND gate, the output end of the third NAND gate is connected to the input end of the delay chain D2 and one input end of the fourth NAND gate, the output end of the delay chain D2 is connected to the input end of the seventh NAND gate, the output end of the seventh NAND gate is connected to the other input end of the fourth NAND gate, the output end of the fourth NAND gate is connected to one input end of the first NOR gate, the output end of the sixth NAND gate is connected to the other input end of the first NOR gate, and the output end of the first NOR gate is connected to the input end of the eighth NAND gate. The input end of the first NOT gate inputs a ref signal, and the output end of the third NOT gate outputs rs signal, and the output end of the fourth NOT gate outputs rs_bar signal, and the output end of the third NAND gate outputs rst signal, and the output end of the first NOR gate outputs ref signal, and the output end of the eighth NOT gate outputs ref_bar signal.
7. An under-sampled phase-locked loop characterized by: The high-isolation under-sampling phase detector of any one of claims 1-6.
Citation Information
Patent Citations
Phase-locked loop low in stray and quick in locking
CN106603070A