Fast frequency locking synthesizer based on frequency phase compensation

Abstract

This invention provides a fast frequency locking synthesizer based on frequency and phase compensation. The input of a frequency and phase detector is connected to the output of a frequency divider, and the output of the frequency and phase detector is connected to the input of a charge pump. The output of the charge pump is connected to the input of a loop filter, and the output of the loop filter is connected to the input of a voltage-controlled oscillator (VCO). The output of the VCO is connected to the inputs of a frequency-to-digital converter (FDDC), the frequency divider, and the phase-to-digital converter (PDC). The output of the PDC is connected to the input of the frequency divider. This invention proposes an innovative reconfigurable system structure that achieves frequency and phase compensation with a non-intrusive design, enabling fast locking, low noise, and high precision.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and more specifically, to a fast frequency locking synthesizer based on frequency phase compensation. Background Technology

[0002] Modern electronic systems require precise clocks for timing, synchronization, and other functions. Radio frequency (RF) modules, in particular, rely on high-precision, low-noise clocks to perform wireless communication tasks. Crystal oscillators dominate the reference clock field due to their superior frequency stability and accuracy. However, due to manufacturing limitations, crystal oscillators cannot provide high-frequency clocks. Currently, phase-locked loops (PLLs) are commonly used to generate high-quality, high-frequency clocks. These PLLs lock the output frequency of a voltage-controlled oscillator (VCO) to a reference clock through loop feedback, achieving performance characteristics such as zero frequency difference during locking, low noise, and high precision.

[0003] Specific application scenarios require frequency hopping functionality, and the frequency switching time of the PLL determines the efficiency of system operating mode transitions. Traditional PLLs typically have a small loop bandwidth, which offers advantages such as reduced output frequency noise and improved loop stability in the locked state. However, for the locking process, a small bandwidth means a longer locking time. For example, in a storage interface system, the frequency hopping time needs to be less than 2 microseconds, while the locking time of traditional PLLs is generally on the order of tens of microseconds, making it difficult to meet the system's frequency hopping speed requirements. Therefore, to meet the stringent frequency hopping time requirements, the traditional PLL locking method must be improved. Simultaneously, the improved solution needs to maintain high precision and low noise even in the locked state.

[0004] The traditional PLL locking method works as follows: the loop detects the phase difference between the divided clock and the reference clock and feeds it back to the voltage-controlled oscillator (VCO). By adjusting the frequency, the phase error is compensated for, ultimately achieving frequency and phase convergence. However, phase is the integral of frequency, which exhibits hysteresis. The loop's method of compensating for phase error by adjusting the output frequency cannot achieve simultaneous frequency and phase convergence. When the loop adjusts the frequency to the target frequency, the loop phase error is at its maximum. The loop then samples the phase error and continues to increase the frequency to compensate for it. When the loop phase error is cleared, a difference exists again between the output frequency and the target frequency, causing the phase error to expand in the opposite direction. When the loop frequency and output frequency are the same again, both the frequency and phase errors are small and negligible, and the PLL can be considered to have completed locking.

[0005] Current research commonly employs multi-bandwidth switching to accelerate the locking process. This involves using a large bandwidth during the locking phase to expedite the loop's locking, and a smaller bandwidth near or after locking to achieve better normal operating performance. While this approach still adheres to the PLL's locking mechanism and reduces locking time, it still struggles to meet more stringent locking time requirements. Multi-bandwidth switching typically requires an additional phase difference detection module and various charge pump and loop filter operating modes. This intrusive design increases circuit complexity and reduces the PLL's performance during normal operation.

[0006] In systems with frequency hopping requirements, the locking speed of the frequency synthesizer determines the efficiency of the system switching operating modes. Traditional phase-locked loops and currently popular multi-bandwidth switching schemes all use loop feedback to achieve frequency and phase alignment between the output clock and the reference clock. However, the loop feedback method is limited by the hysteresis characteristics of frequency and phase, making it difficult to complete convergence in a short time.

[0007] Patent document CN113872592A discloses a phase-locked loop (PLL) frequency synthesizer, comprising: a prescaler for receiving a clock signal input from an external circuit and dividing the clock signal; a PLL circuit for receiving the divided clock signal output from the prescaler and outputting 2N clock signals with sequentially changing phases; and an N-fold frequency multiplier circuit, including an OR gate, an N-stage XOR gate, and an N-stage AND gate, for receiving the 2N clock signals with sequentially changing phases output from the PLL circuit and multiplying the 2N clock signals to output a final clock signal with an N-fold frequency multiplier as the clock signal output by the PLL frequency synthesizer. However, this patent document still has the drawback of failing to meet the stringent frequency hopping time requirements. Summary of the Invention

[0008] In view of the shortcomings of the prior art, the purpose of this invention is to provide a fast frequency locking synthesizer based on frequency phase compensation.

[0009] According to the present invention, a fast frequency locking synthesizer based on frequency and phase compensation includes: a frequency and phase detector, a charge pump, a locking algorithm module, a loop filter, a voltage-controlled oscillator, a frequency divider, a frequency-to-digital converter, and a phase-to-digital converter.

[0010] The input terminal of the frequency and phase detector is connected to the output terminal of the frequency divider, and the output terminal of the frequency and phase detector is connected to the input terminal of the charge pump.

[0011] The output terminal of the charge pump is connected to the input terminal of the loop filter, and the output terminal of the loop filter is connected to the input terminal of the voltage-controlled oscillator.

[0012] The output terminal of the voltage-controlled oscillator is connected to the input terminal of the frequency-to-digital converter, the input terminal of the frequency divider, and the input terminal of the phase-to-digital converter, respectively.

[0013] The output of the phase-to-digital converter is connected to the input of the frequency divider;

[0014] The input terminal of the locking algorithm module is connected to the feedback signal terminal of the frequency-to-digital converter and the phase-to-digital converter; the output terminal of the locking algorithm module is connected to the control terminal of the loop filter resistor, the enable terminal of the frequency-to-digital converter, and the enable terminal of the phase-to-digital converter.

[0015] Preferably, the loop filter includes resistor R1, resistor R2, capacitor C0, capacitor C1, and capacitor C2;

[0016] One end of capacitor C0 is connected to one end of resistor R1 and one end of resistor R2, respectively, and serves as the input terminal of the loop filter; the other end of capacitor C0 is connected to one end of capacitor C1 and one end of capacitor C2, respectively, and is grounded.

[0017] The other end of resistor R1 is connected to the other end of capacitor C1; the other end of resistor R2 is connected to the other end of capacitor C2, and serves as the output terminal of the loop filter.

[0018] Preferably, the loop filter further includes a switch K1, which is connected in parallel to the resistor R1.

[0019] Preferably, the loop filter further includes a switch K2, which is connected in parallel to the resistor R2.

[0020] Preferably, the frequency-to-digital converter includes a first AND gate, a NOT gate, a first counter, and a D flip-flop;

[0021] The first AND gate is connected to the first counter, the first counter is connected to the D flip-flop, and the D flip-flop is connected to the NOT gate;

[0022] The first AND gate is connected to the strobe clock signal output to the first counter. After the first counter is full, it outputs a signal to the D flip-flop. After a delay, the D flip-flop transmits the signal to the NOT gate. The NOT gate outputs a signal to the first AND gate.

[0023] Preferably, the phase-to-digital converter includes a second AND gate, a second counter, and a digital module;

[0024] The second AND gate is connected to the second counter, and the second counter is connected to the digital module;

[0025] The second AND gate selects the clock signal to the second counter, which is connected to the digital module for signal processing. The digital module outputs phase information.

[0026] Preferably, the locking algorithm module infers the current locking state based on frequency and phase information and provides corresponding control signals.

[0027] Preferably, the locking process includes a frequency compensation stage and a phase compensation stage;

[0028] During the frequency compensation phase, the system is reconfigured into an FLL form, and the frequency of the VCO is detected by the FDC and fed back to the charge pump to charge and discharge the capacitor.

[0029] During the phase compensation stage, the system is reconstructed from FLL to PLL, the phase is manipulated, the PFD performs phase detection on the reference frequency and the divided frequency, and the phase difference is output as a pulse voltage signal.

[0030] Preferably, during the frequency compensation stage, the output current of the charge pump is set to the maximum mode to complete the frequency compensation.

[0031] When the VCO frequency is the same as the target frequency, the FDC transmits feedback information to the lock detection module, reporting that frequency compensation is complete, and the lock detection module adjusts the system to phase compensation mode.

[0032] Preferably, in the phase compensation stage, the system inputs the pulse voltage signal and the frequency of the VCO output after frequency division to the PDC for phase difference detection;

[0033] The phase difference signal output by the PDC in digital form is calculated and converted into the transient division ratio of the frequency divider. The transient division ratio modulates the transient period of the divided clock, and the difference between the transient period and the normal period is the compensated phase difference; the phase error compensation is completed within one period.

[0034] If the frequency compensation result remains unchanged within one cycle, the loop is in a locked state with both frequency and phase errors at 0. The PDC outputs a feedback signal to the locking algorithm module to report that the frequency compensation is complete, and the system will enter the normal locking state of loop control.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] 1. This invention directly compensates for frequency and phase, and can break through the limitations of loop feedback schemes to achieve fast locking; First, this invention uses a frequency-locked loop structure to detect the frequency of the output clock and feed it back to the voltage-controlled oscillator to achieve fast alignment of the output frequency with the target frequency. Second, it uses phase detection and changing the division ratio of the frequency divider to align the phase in one step, thereby completing fast locking.

[0037] 2. The frequency synthesizer of the present invention can greatly improve the efficiency of system switching operating modes and further improve system performance;

[0038] 3. The present invention adopts a non-intrusive design. After frequency and phase compensation is completed to achieve locking, the module that assists in fast locking on the loop will not interfere with the normal operation of the loop. The frequency synthesizer can still achieve excellent performance of low noise and high precision when operating normally.

[0039] 4. This invention uses a novel locking method to overcome the shortcomings of traditional loop correction where phase and frequency errors cannot be zeroed; that is, it adopts the divide-and-conquer approach, first calibrating the frequency and then using a one-step phase calibration method to achieve the fastest locking speed. Attached Figure Description

[0040] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0041] Figure 1 This is a structural diagram of the fast frequency locking synthesizer based on frequency phase compensation of the present invention;

[0042] Figure 2 A schematic diagram of the FLL structure during frequency compensation;

[0043] Figure 3 A schematic diagram of the PLL structure during phase compensation;

[0044] Figure 4 This is a timing diagram for phase compensation;

[0045] Figure 5 This is a schematic diagram illustrating the change of frequency and phase over time during the locking process.

[0046] Figure 6 This is a schematic diagram of the loop filter structure;

[0047] Figure 7 This is a schematic diagram of the structure of a frequency-to-digital converter;

[0048] Figure 8 This is a schematic diagram of the phase-to-digital converter.

[0049] Figure 9 This is a schematic diagram of the working mode of the locking algorithm. Detailed Implementation

[0050] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0051] Example 1:

[0052] like Figures 1-9 As shown, this embodiment provides a fast frequency locking synthesizer based on frequency and phase compensation, including: a frequency and phase detector, a charge pump, a locking algorithm module, a loop filter, a voltage-controlled oscillator (VCO), a frequency divider, a frequency-to-digital converter (FDC), and a phase-to-digital converter (PDC). The input of the frequency and phase detector is connected to the output of the frequency divider. The output of the frequency and phase detector is connected to the input of the charge pump. The output of the charge pump is connected to the input of the loop filter. The output of the loop filter is connected to the input of the VCO. The output of the VCO is connected to the inputs of the FDC, the frequency divider, and the PDC, respectively. The output of the PDC is connected to the input of the frequency divider. The input of the locking algorithm module is connected to the feedback signals of the FDC and PDC, and the output is connected to the loop filter resistor control, the enable terminal of the FDC, and the enable terminal of the PDC. The locking algorithm module infers the current locking state based on frequency and phase information and provides corresponding control signals.

[0053] The frequency-to-digital converter includes a first AND gate, a NOT gate, a first counter, and a D flip-flop. The first AND gate is connected to the first counter, the first counter is connected to the D flip-flop, the D flip-flop is connected to the NOT gate, the first AND gate is connected to the strobe clock signal output to the first counter, the first counter outputs a signal to the D flip-flop after it is full, the D flip-flop passes the signal to the NOT gate after a delay, and the NOT gate outputs a signal to the first AND gate.

[0054] The phase-to-digital converter includes a second AND gate, a second counter, and a digital module. The second AND gate is connected to the second counter, the second counter is connected to the digital module, the second AND gate selects the clock signal to the second counter, the second counter is connected to the digital module for signal processing, and the digital module outputs phase information.

[0055] The loop filter includes resistors R1 and R2, and capacitors C0, C1, and C2. One end of capacitor C0 is connected to one end of resistors R1 and R2, serving as the input terminal of the loop filter. The other end of capacitor C0 is connected to one end of capacitors C1 and C2, and grounded. The other end of resistor R1 is connected to the other end of capacitor C1, and the other end of resistor R2 is connected to the other end of capacitor C2, serving as the output terminal of the loop filter. The loop filter also includes switches K1 and K2, which are connected in parallel with resistor R2.

[0056] Working principle:

[0057] This embodiment employs a fast convergence scheme with frequency and phase compensation. Compared to the traditional scheme where frequency and phase errors cannot be simultaneously reduced to zero, this application uses a divide-and-conquer approach to compensate for both frequency and phase separately, thereby achieving the fastest loop convergence. Traditional schemes achieve frequency and phase calibration through a loop, but due to the integral relationship between frequency and phase, the errors cannot be reduced to zero simultaneously. The loop must wait for a period of convergence until the frequency and phase errors are reduced to a small range before considering the loop locked, which significantly increases the loop locking time.

[0058] The fast locking scheme proposed in this embodiment consists of two stages: a frequency compensation stage and a phase compensation stage. In the frequency compensation stage, the system is reconfigured into an FLL (Flexible Linked Array) form, and the frequency of the VCO is detected by the FDC (Fault Discharge Center) and fed back to the charge pump for charging and discharging the capacitor. During this stage, the output current of the charge pump is set to maximum to complete frequency compensation as quickly as possible. When the VCO frequency matches the target frequency, the FDC transmits feedback information to the locking detection module, reporting that frequency compensation is complete. The locking detection module then adjusts the system to phase compensation mode. The system is reconfigured from an FLL to a PLL (Plug-in Loop) to operate on the phase. The PFD (Power Detector) performs phase detection on the reference frequency and the divided frequency, and the phase difference is output as a pulse voltage signal. The system inputs the pulse voltage signal and the VCO output frequency (after simple frequency division) to the PDC for phase difference detection. The digital phase difference signal output by the PDC is calculated and converted into the transient division ratio of the frequency divider. This transient division ratio modulates the transient period of the divided clock. The difference between the transient period and the normal period is the compensated phase difference. This scheme achieves phase error compensation within one cycle. The frequency compensation result remains unchanged within one cycle. Therefore, the loop is now in a state where both frequency error and phase error are 0, i.e., locked. At this point, the PDC outputs a feedback signal to the locking algorithm module to report that frequency compensation is complete. The system will then enter the normal locking state of loop control. Thus, the loop has achieved rapid locking.

[0059] This embodiment employs a divide-and-conquer approach, using a novel locking method to first calibrate the frequency and then perform a one-step phase calibration to achieve the fastest locking speed. This embodiment proposes an innovative reconfigurable system structure that achieves frequency and phase compensation with a non-intrusive design, enabling fast locking, low noise, and high precision.

[0060] Example 2:

[0061] Those skilled in the art can understand this embodiment as a more specific description of Embodiment 1.

[0062] This embodiment provides a fast frequency locking synthesizer based on frequency phase compensation. The overall structure of the frequency synthesizer is as follows: Figure 1 As shown, it includes a frequency and phase detector (PFD), a charge pump (CP), a loop filter (LPF), a voltage-controlled oscillator (VCO), a frequency divider (DIV), a frequency-to-digital converter (FDC), a phase-to-digital converter (PDC), and a locking algorithm module.

[0063] The PFD (Power Filter) discriminates the phase difference between the divided clock and the reference clock, converting the phase difference signal into a pulse voltage signal to control the subsequent CP (Concurrent Filter) circuit. The CP converts the phase difference pulse voltage signal into a pulse current signal. The PFD and CP achieve zero-order hold sampling of the phase difference signal. The LPF (Low Power Filter) uses a third-order resistor-capacitor (RC) network to extract the DC signal and pass it to the subsequent VCO (Voltage Control Unit) to lock the output frequency. It also filters out high-frequency noise, effectively improving the noise performance of the output clock. The filter has a switch that can short-circuit the resistor for use in frequency compensation mode. The VCO generates a voltage-controlled high-frequency clock, which is output through a buffer and distributed to the DIV (Divider Filter) for frequency division. The DIV divides the high-frequency clock from the VCO into a low-frequency signal, allowing the loop to operate at low frequencies, reducing circuit power consumption and design complexity. The division ratio is also flexibly controllable, making it easier to configure the circuit's operating state.

[0064] The PDC detects the phase difference between the divided clock and the reference clock, converts it into a digital signal, and outputs it to the DIV. The DIV then changes the division ratio to achieve phase compensation. Simultaneously, the PDC sends a feedback signal to the locking algorithm module. The FDC detects the difference between the frequency synthesizer output frequency and the target frequency, converts it into a digital signal, and outputs it to the CP, enabling the filter to charge and discharge rapidly to achieve the frequency compensation target. It also sends a feedback signal to the locking algorithm module. The locking algorithm infers the current operating state of the loop and provides corresponding signals to control the LPF, PDC, and FDC to set different system operating modes.

[0065] like Figure 2The diagram shows the system structure in frequency compensation mode. The condition for phase-locked loop (PLL) locking is that the phase of the divided clock frequency is the same as the reference clock. This structure's fast locking scheme uses external control to directly compensate the oscillator for both frequency and phase. Frequency compensation is achieved through a frequency-locked loop (FLL), including FDC, CP, LPF, and VCO. First, the resistors in the loop filter are short-circuited, turning the loop filter into a three-capacitor parallel configuration. This type of loop filter is a first-order structure, where charging and discharging charges accumulate on the capacitors. In normal operation, when a third-order structure is used, the addition of resistors does not affect the charge on the capacitors, thus ensuring that the frequency compensation results are not compromised. Next, the FDC measures the VCO output frequency, and the measurement result is fed back to the charge pump to charge or discharge the capacitors. The charge pump uses maximum current mode at this time to accelerate the frequency compensation. Under the action of the FLL, the VCO output frequency will approach the target frequency. After reaching the target frequency, the FDC relinquishes control of the CP and provides a feedback signal to the locking algorithm module to inform it that the frequency compensation phase has ended.

[0066] like Figure 3 The diagram shows the system structure in phase compensation mode. After the frequency compensation phase, the locking module control system enters the phase compensation phase. The system changes from an FLL to a PLL, and after phase compensation, it transitions to a normal PLL locked state. Since the VCO phase is random, the current VCO clock phase after DIV division is not aligned with the reference clock. Without phase compensation, the loop will accumulate phase changes by varying the output frequency to achieve phase alignment. This process is very wasteful of locking time. Phase compensation achieves a zeroing process by changing the division ratio. After compensation, the PDC relinquishes control of the division ratio, and the system operates with a fixed division ratio. Simultaneously, the PDC generates a feedback signal to inform the locking algorithm module that the phase compensation phase has ended.

[0067] like Figure 4 As shown, this embodiment uses a variable division ratio of the frequency divider to achieve a one-time zeroing of the phase error. The DIV (Digital Inverter) performs frequency division by counting. If the normal division ratio is N and the current phase error is Φ, then during the phase compensation period, the division ratio of the DIV needs to be changed to N(1-Φ / 2π). By reducing the number of counts, the instantaneous period of the divided clock is shortened, thereby achieving phase compensation. After the phase compensation period, the phase of the divided clock is aligned with the reference clock.

[0068] At this point, the system's frequency and phase are aligned, the loop interference is released, and the system will automatically enter a locked state. Subsequent frequency dividers will still use the original division ratio to ensure normal loop operation.

[0069] like Figure 5The diagram illustrates the rapid locking process of this embodiment, with the dashed line representing the traditional locking method for comparison. As can be seen, the traditional locking method uses a loop to feed back and calibrate phase information. However, frequency and phase are integral relationships, and a loop cannot simultaneously correct both errors to zero, significantly extending the loop's locking time. This embodiment employs a divide-and-conquer approach, calibrating frequency and phase separately to achieve the fastest convergence speed. Before time 1, the system is adjusted to an FLL structure for frequency compensation. At time 1, when frequency compensation is achieved at its fastest speed, the system's phase error reaches its maximum. Subsequently, the system performs a phase compensation step, filling the phase difference between the reference frequency and the divided frequency within one cycle. At this point, the system frequency is the target frequency, and the phase difference is 0, indicating entry into the locked state. As the diagram illustrates, compared to the traditional method of addressing both frequency and phase issues simultaneously, using a divide-and-conquer approach to perform frequency and phase compensation in stages significantly accelerates the convergence speed.

[0070] Unlike traditional schemes that use phase-locked loops to achieve frequency and phase alignment, this scheme employs direct frequency and phase control, offering the following advantages: First, it boasts faster initial convergence speed. The FLL structure is simple, and a charge pump continuously charges the loop filter until the frequencies are the same, making it the fastest way to charge all capacitors to the target control voltage. Second, it eliminates the phase-locking process after frequency alignment. During the initial frequency alignment in the PLL locking process, the phases are not aligned, requiring the PLL loop to continuously change the frequency to accumulate phase changes and achieve phase-frequency alignment—a very slow process. Based on these two reasons, the fast locking scheme proposed in this embodiment saves significantly more locking time compared to traditional schemes.

[0071] like Figure 6 As shown, the circuit of an important sub-module in this embodiment is as follows: The loop filter uses a third-order RC network. During normal operation, it filters the results of the PDF and CP zero-order hold sampling, and the result is passed to the VCO to realize the feedback of phase difference on the output clock frequency. During the frequency compensation stage, the resistors need to be shorted by a switch. If the switch is not used, the voltage between the capacitors will be different due to the current limiting of the resistors. In particular, C1 has the largest capacitance value. When the frequency compensation mode changes to the phase compensation mode, C1 will transfer charge to other capacitors, thereby changing the control voltage of the VCO. This will cause the frequency compensation to fail, and the output frequency will deviate from the target frequency again, which will eventually still need to be corrected by the loop. If the switch is used to short-circuit, the charge pump will charge all capacitors synchronously. When the frequency compensation mode changes to the phase compensation mode, the switch is opened, and there will be no charge transfer between the capacitors. This ensures that the result of frequency compensation is not destroyed.

[0072] like Figure 7As shown, the FDC (Frequency Control Unit) is the module for detecting the VCO output frequency. The FDC uses two counters to count the reference clock and the VCO output clock respectively, obtaining the number of rising edges of the VCO output clock within a certain reference clock cycle. The digital module can calculate the difference between the current frequency and the target frequency based on the number of rising edges, thus realizing the conversion of the frequency difference to digital values. Once the frequency difference narrows to within a certain threshold, it means that frequency compensation is complete. The digital unit then transmits a control signal to the charge pump to stop charging and discharging, and the system immediately enters phase compensation mode.

[0073] The FDC operates cyclically during counting. If the threshold is not reached after one frequency extraction, it needs to immediately enter the next stage of rising edge counting. If the VCO's output frequency is too high and the FDC cannot handle it, the VCO can be pre-divided before being fed into the FDC. This can be achieved by simply changing the threshold parameter in the subsequent digital module.

[0074] like Figure 8 As shown, the PDC is a module that detects the phase difference between the divided clock and the reference clock. The PDC generates a pulse signal with a pulse width equal to the phase difference between the divided clock and the reference clock. If this pulse signal is used as an enable to count the output of the VCO, this value can represent the phase difference, thus realizing the conversion of the phase difference to a digital signal. The structure of the PDC, as shown in the figure, is a counter with an enable signal that can count within the pulse signal. After obtaining the count value, the digital module converts it into the division ratio of the frequency divider. During the period compensation phase, the division ratio is changed to compensate for the phase difference. After the period compensation phase ends, the frequency divider returns to the normal division ratio, the PDC stops working, and the system enters a normal operating locked state.

[0075] Unlike FDC, PDC only operates once or a few times during the periodic compensation phase and is not in a periodic operation state. PDC can count within a single pulse or by averaging counts over multiple pulses. Averaging can improve the accuracy of phase error conversion, but it also increases the lock-in time. If the VCO frequency is too high, the VCO frequency can be pre-divided before being fed into the PDC; this can be achieved by simply changing the calculated value in the digital module.

[0076] like Figure 9The diagram illustrates the locking algorithm. The digital circuit starts in its initial state and returns to this state whenever a reset signal is encountered during operation. With the fast locking mode enabled, the algorithm begins operation, entering the frequency compensation module. During frequency compensation, feedback 1 is disabled, and the circuit remains in frequency compensation mode. When feedback 1 is enabled, the circuit enters the phase compensation phase. As long as phase compensation is not complete (i.e., feedback 2 is disabled), the circuit continues in phase compensation mode. When phase compensation is complete, feedback 2 is enabled, and the circuit enters the locked state. Unless externally commanded to adjust, the circuit remains in the normally operating locked state. When the higher-level system needs to change the frequency, the flag signal is enabled, and the circuit re-enters the frequency compensation state for a new round of fast locking. If a comparison of traditional locking and fast locking performance is needed during testing, the enable signal can be disabled, and the system will not enter the fast locking state; instead, loop convergence will be used for locking.

[0077] This invention overcomes the shortcomings of traditional loop correction methods that cannot return phase and frequency errors to zero by employing a novel locking method. Specifically, it uses a divide-and-conquer approach, first calibrating the frequency and then performing a one-step phase calibration to achieve the fastest locking speed. This invention proposes an innovative reconfigurable system structure that achieves frequency and phase compensation with a non-intrusive design, enabling fast locking, low noise, and high precision.

[0078] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A fast frequency-locking synthesizer based on frequency phase compensation, characterized in that, include: Frequency and phase detectors, charge pumps, lockout algorithm modules, loop filters, voltage-controlled oscillators, frequency dividers, frequency-to-digital converters, and phase-to-digital converters; The input terminal of the frequency and phase detector is connected to the output terminal of the frequency divider, and the output terminal of the frequency and phase detector is connected to the input terminal of the charge pump. The output terminal of the charge pump is connected to the input terminal of the loop filter, and the output terminal of the loop filter is connected to the input terminal of the voltage-controlled oscillator. The output terminal of the voltage-controlled oscillator is connected to the input terminal of the frequency-to-digital converter, the input terminal of the frequency divider, and the input terminal of the phase-to-digital converter, respectively. The output of the phase-to-digital converter is connected to the input of the frequency divider; The input terminal of the locking algorithm module is connected to the feedback signal terminal of the frequency-to-digital converter and the phase-to-digital converter; the output terminal of the locking algorithm module is connected to the control terminal of the loop filter resistor, the enable terminal of the frequency-to-digital converter, and the enable terminal of the phase-to-digital converter.

2. The fast frequency locking synthesizer based on frequency phase compensation according to claim 1, characterized in that, The loop filter includes resistor R1, resistor R2, capacitor C0, capacitor C1, and capacitor C2; One end of capacitor C0 is connected to one end of resistor R1 and one end of resistor R2, respectively, and serves as the input terminal of the loop filter; the other end of capacitor C0 is connected to one end of capacitor C1 and one end of capacitor C2, respectively, and is grounded. The other end of resistor R1 is connected to the other end of capacitor C1; the other end of resistor R2 is connected to the other end of capacitor C2, and serves as the output terminal of the loop filter.

3. The fast frequency locking synthesizer based on frequency phase compensation according to claim 2, characterized in that, The loop filter also includes a switch K1, which is connected in parallel to the resistor R1.

4. The fast frequency locking synthesizer based on frequency phase compensation according to claim 3, characterized in that, The loop filter also includes a switch K2, which is connected in parallel to the resistor R2.

5. The fast frequency locking synthesizer based on frequency phase compensation according to claim 1, characterized in that, The frequency-to-digital converter includes a first AND gate, a NOT gate, a first counter, and a D flip-flop; The first AND gate is connected to the first counter, the first counter is connected to the D flip-flop, and the D flip-flop is connected to the NOT gate; The first AND gate is connected to the strobe clock signal output to the first counter. After the first counter is full, it outputs a signal to the D flip-flop. After a delay, the D flip-flop transmits the signal to the NOT gate. The NOT gate outputs a signal to the first AND gate.

6. The fast frequency locking synthesizer based on frequency phase compensation according to claim 1, characterized in that, The phase-to-digital converter includes a second AND gate, a second counter, and a digital module; The second AND gate is connected to the second counter, and the second counter is connected to the digital module; The second AND gate selects the clock signal to the second counter, which is connected to the digital module for signal processing. The digital module outputs phase information.

7. The fast frequency locking synthesizer based on frequency phase compensation according to claim 1, characterized in that, The locking algorithm module infers the current locking state based on frequency and phase information and provides corresponding control signals.

8. The fast frequency locking synthesizer based on frequency phase compensation according to claim 1, characterized in that, The locking process includes a frequency compensation stage and a phase compensation stage; During the frequency compensation phase, the system is reconfigured into an FLL form, and the frequency of the VCO is detected by the FDC and fed back to the charge pump to charge and discharge the capacitor. During the phase compensation stage, the system is reconstructed from FLL to PLL, the phase is manipulated, the PFD performs phase detection on the reference frequency and the divided frequency, and the phase difference is output as a pulse voltage signal.

9. The fast frequency locking synthesizer based on frequency phase compensation according to claim 8, characterized in that, During the frequency compensation phase, the output current of the charge pump is set to the maximum mode to complete the frequency compensation. When the VCO frequency is the same as the target frequency, the FDC transmits feedback information to the lock detection module, reporting that frequency compensation is complete. The lock detection module then adjusts the system to phase compensation mode.

10. The fast frequency locking synthesizer based on frequency phase compensation according to claim 9, characterized in that, During the phase compensation stage, the system inputs the pulse voltage signal and the frequency of the VCO output after frequency division to the PDC for phase difference detection. The phase difference signal output by the PDC in digital form is calculated and converted into the transient division ratio of the frequency divider. The transient division ratio modulates the transient period of the divided clock, and the difference between the transient period and the normal period is the compensated phase difference; the phase error compensation is completed within one period. If the frequency compensation result remains unchanged within one cycle, the loop is in a locked state with both frequency and phase errors at 0. The PDC outputs a feedback signal to the locking algorithm module to report that the frequency compensation is complete, and the system will enter the normal locking state of loop control.

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