A chip scanning test circuit and a chip

Abstract

The present invention discloses a chip scanning test circuit and a chip. A chip scanning test circuit includes: at least one high-frequency logic module and at least one low-frequency logic module; at least one clock controller; a first clock input terminal for receiving an external test clock signal; a selection module, a first input terminal of the selection module is connected to the clock controller, a second input terminal of the selection module is connected to the first clock input terminal, and output terminals of the selection module are respectively connected to the high-frequency logic module and the low-frequency logic module; a mode control terminal is connected to a controlled terminal of the selection module. Thus, by controlling the output clock signal through the selection module, the low-frequency logic module can obtain the test clock signal without being connected after the clock controller, which is beneficial to improving the test coverage rate. At the same time, there is no need to insert a corresponding clock controller in front of the low-frequency logic module, which is beneficial to reducing the number of on-chip clock controllers, saving chip area, and reducing costs.

Description

Technical Field

[0001] The present invention relates to the field of chip scan testing, and particularly to a chip scan test circuit and a chip. Background Art

[0002] In order to detect whether a chip, i.e., an integrated circuit, has defects, the chip will be subjected to a scan (SCAN) test. Based on the structure connecting the timing unit and the fault logic model, the test process can be roughly divided into a shift input stage and a capture output stage. In the shift input stage, different test vectors are input to the timing unit, and in the capture output stage, the result vector output by the timing unit is obtained. According to the test vector and the result vector, it can be known whether the chip has defects.

[0003] The clock signals used in the shift input stage and the capture output stage may be different. According to the magnitude of the clock frequency used in the capture output stage, it can be divided into a slow (normal scan) test and a same-speed (at speed scan) test. The slow test usually uses the external input clock signal of an automatic test equipment (ATE), and the same-speed test generally uses the on-chip clock signal inside the chip. The same-speed test can simulate the actual working clock frequency and can more accurately reflect whether the chip has defects.

[0004] Reference Figure 3 In the prior art, all the test clocks in the chip are controlled by a clock controller 900 (OCCController). All the logic modules 910 to be tested in the chip are connected after the clock controller 900. Otherwise, the test clock cannot be obtained, which makes it difficult to process many small logic modules in the chip and reduces the test coverage. In addition, whether it is a high-frequency logic module or a low-frequency logic module in the logic module 900 to be tested, it needs to correspond to a clock controller 900, resulting in a large number of clock controllers 900, wasting chip area and increasing costs. Summary of the Invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art. For this purpose, the present invention provides a chip scan test circuit and a chip, which can improve the test coverage, save chip area and reduce costs.

[0006] A chip scan test circuit according to an embodiment of the first aspect of the present invention includes: at least one high-frequency logic module and at least one low-frequency logic module; at least one clock controller; a first clock input terminal for receiving an external test clock signal; a selection module, a first input terminal of the selection module is connected to the clock controller, a second input terminal of the selection module is connected to the first clock input terminal, and output terminals of the selection module are respectively connected to the high-frequency logic module and the low-frequency logic module; a mode control terminal is connected to a controlled terminal of the selection module.

[0007] A chip scan test circuit according to an embodiment of the present invention has at least the following beneficial effects: The first clock input terminal can obtain an external test clock signal. When slow testing is required, by controlling the level of the mode control terminal, the selection module is made to select the external slow test clock signal input from the second input terminal and output it to the high-frequency logic module and the low-frequency logic module, so as to perform slow testing on the high-frequency logic module and the low-frequency logic module. When same-speed testing is required, the level of the mode control terminal changes, causing the selection module to select the clock signal input from the first input terminal, that is, the same-speed test clock signal generated by the clock controller, and output it to the high-frequency logic module to achieve same-speed testing of the high-frequency logic module. The same-speed test clock signal does not need to be output to the low-frequency logic module. By changing the level of the mode control terminal, the slow test mode or the same-speed test mode can be selected. Thus, by controlling the clock signal output to the high-frequency logic module and the low-frequency logic module through the selection module, the low-frequency logic module can obtain the test clock signal without being connected after the clock controller, which is beneficial to improving the test coverage rate. At the same time, there is no need to insert a corresponding clock controller in front of the low-frequency logic module, which is beneficial to reducing the number of on-chip clock controllers, saving chip area, and reducing costs.

[0008] According to some embodiments of the present invention, it further includes a crystal oscillator clock input terminal and a second clock input terminal. A first input terminal of the clock controller is connected to the crystal oscillator clock input terminal, and a second input terminal of the clock controller is connected to the second clock input terminal.

[0009] According to some embodiments of the present invention, it further includes a crystal oscillator clock input terminal. A first input terminal of the clock controller is connected to the crystal oscillator clock input terminal, and a second input terminal of the clock controller is connected to the first clock input terminal.

[0010] According to some embodiments of the present invention, the selection module includes a first data selector corresponding to the clock controller one by one. The first input end of the first data selector is connected to the corresponding clock controller, the second input end of the first data selector is connected to the first clock input end, the output end of the first data selector is connected to the high-frequency logic module, and the controlled end of the first data selector is connected to the mode control end.

[0011] According to some embodiments of the present invention, the selection module further includes at least one second data selector. The input end of the second data selector is connected to the first clock input end, the output end of the second data selector is connected to the low-frequency logic module, and the controlled end of the second data selector is connected to the mode control end.

[0012] According to some embodiments of the present invention, an inverter is further included. The mode control end is respectively connected to the controlled end of the clock controller and the input end of the inverter, and the output end of the inverter is connected to the controlled end of the selection module.

[0013] According to some embodiments of the present invention, a first conduction control unit and a second conduction control unit are further included. The first clock input end is respectively connected to the input end of the first conduction control unit and the input end of the second conduction control unit. The output end of the first conduction control unit is connected to the clock controller, the output end of the second conduction control unit is connected to the second input end of the selection module, the controlled end of the first conduction control unit is connected to the mode control end, and the controlled end of the second conduction control unit is connected to the output end of the inverter.

[0014] According to some embodiments of the present invention, the high-frequency logic module includes a first timing unit, a high-frequency logic unit, a first scan input end, a first scan enable end, and a first capture output end. The input end of the first timing unit is connected to the first scan input end, the enable end of the first timing unit is connected to the first scan enable end, the clock end of the first timing unit is connected to the output end of the selection module, the high-frequency logic unit is connected to the first timing unit, and the output end of the first timing unit is connected to the first capture output end.

[0015] According to some embodiments of the present invention, the low-frequency logic module includes a second timing unit, a low-frequency logic unit, a second scan input terminal, a second scan enable terminal, and a second capture output terminal. The input terminal of the second timing unit is connected to the second scan input terminal, the enable terminal of the second timing unit is connected to the second scan enable terminal, the clock terminal of the second timing unit is connected to the output terminal of the selection module, the low-frequency logic unit is connected to the second timing unit, and the output terminal of the second timing unit is connected to the second capture output terminal.

[0016] A chip according to an embodiment of the second aspect of the present invention includes an integrated circuit, and the integrated circuit includes the above-mentioned chip scan test circuit.

[0017] The chip according to the embodiment of the present invention has at least the following beneficial effects: When inputting appropriate electrical frequencies or signals to each port of the integrated circuit for chip scan testing, specifically: input a test clock signal to the first clock input terminal. When slow testing is required, by controlling the level of the mode control terminal, the selection module is made to select the slow test clock signal input from the second input terminal and output it to the high-frequency logic module and the low-frequency logic module for slow testing of the high-frequency logic module and the low-frequency logic module. When same-speed testing is required, change the level of the mode control terminal so that the selection module selects the clock signal input from the first input terminal, that is, the same-speed test clock signal generated by the clock controller, and outputs it to the high-frequency logic module to achieve same-speed testing of the high-frequency logic module. The same-speed test clock signal does not need to be output to the low-frequency logic module. By changing the level of the mode control terminal, the slow test mode or the same-speed test mode can be selected. In this way, by controlling the clock signal output to the high-frequency logic module and the low-frequency logic module through the selection module, the low-frequency logic module can obtain the test clock signal without being connected after the clock controller, which is beneficial to improving the test coverage rate. At the same time, there is no need to insert a corresponding clock controller in front of the low-frequency logic module, which is beneficial to reducing the number of on-chip clock controllers, saving chip area, and reducing costs.

[0018] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present invention will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings, where:

[0020] Figure 1 is a circuit schematic diagram of one embodiment of the present invention;

[0021] Figure 2 is a circuit schematic diagram of another embodiment of the present invention;

[0022] Figure 3 It is a circuit schematic diagram in the prior art. Specific embodiments

[0023] The embodiments of the present invention will be described in detail below. The examples of the embodiments are shown in the drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present invention and should not be construed as a limitation to the present invention.

[0024] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by terms such as up, down, front, back, left, right, etc. is based on the orientation or positional relationship shown in the drawings. This is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0025] In the description of the present invention, if the first and second are described only for the purpose of distinguishing technical features, they should not be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0026] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installation, connection, etc. should be understood in a broad sense. Those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific content of the technical solution.

[0027] As Figure 1 and Figure 2 shown, a chip scanning test circuit according to an embodiment of the present invention includes: at least one high-frequency logic module 100 and at least one low-frequency logic module 200; at least one clock controller 300; a first clock input terminal 400 for receiving an external test clock signal; a selection module 500, a first input terminal of the selection module 500 is connected to the clock controller 300, a second input terminal of the selection module 500 is connected to the first clock input terminal 400, and an output terminal of the selection module 500 is respectively connected to the high-frequency logic module 100 and the low-frequency logic module 200; a mode control terminal 600 is connected to a controlled terminal of the selection module 500.

[0028] The first clock input terminal 400 can obtain an external test clock signal. When a slow test is required, by controlling the level of the mode control terminal 600, the selection module 500 is made to select the external slow test clock signal input from the second input terminal and output it to the high-frequency logic module 100 and the low-frequency logic module 200, so as to perform a slow test on the high-frequency logic module 100 and the low-frequency logic module 200. When a same-speed test is required, the level of the mode control terminal 600 changes, causing the selection module 500 to select the clock signal input from the first input terminal, that is, the same-speed test clock signal generated by the clock controller 300, and output it to the high-frequency logic module 100, achieving a same-speed test on the high-frequency logic module 100. The same-speed test clock signal does not need to be output to the low-frequency logic module 200. By changing the level of the mode control terminal 600, a slow test mode or a same-speed test mode can be selected. Thus, by controlling the clock signal output to the high-frequency logic module 100 and the low-frequency logic module 200 through the selection module 500, the low-frequency logic module 200 can obtain a test clock signal without being connected after the clock controller 300, which is beneficial to improving the test coverage. At the same time, there is no need to insert a corresponding clock controller 300 in front of the low-frequency logic module 200, which is beneficial to reducing the number of on-chip clock controllers 300, saving chip area, and reducing costs.

[0029] Referring to Figure 1 , in some embodiments of the present invention, it further includes a crystal oscillator clock input terminal 310 and a second clock input terminal 320. The first input terminal of the clock controller 300 is connected to the crystal oscillator clock input terminal 310, and the second input terminal of the clock controller 300 is connected to the second clock input terminal 320.

[0030] As one embodiment of the present invention, the clock controller 300 obtains a crystal oscillator clock signal from a crystal oscillator circuit inside the chip through the crystal oscillator clock input terminal 310, and obtains an externally input test clock signal through the second clock input terminal 320, so as to integrate the crystal oscillator clock signal and the externally input test clock signal, and then generate a corresponding start clock in the shift input stage and a capture clock in the capture output stage, achieving the purpose of same-speed testing.

[0031] Referring to Figure 2 , in some embodiments of the present invention, it further includes a crystal oscillator clock input terminal 310. The first input terminal of the clock controller 300 is connected to the crystal oscillator clock input terminal 310, and the second input terminal of the clock controller 300 is connected to the first clock input terminal 400.

[0032] As another embodiment of the present invention, the clock controller 300 obtains the crystal oscillator clock signal from the crystal oscillator circuit inside the chip through the crystal oscillator clock input terminal 310 of the crystal oscillator, and obtains the externally input test clock signal through the first clock input terminal 400, so as to integrate the crystal oscillator clock signal and the externally input test clock signal, and then generate the corresponding start clock in the shift input stage and generate the capture clock in the capture output stage, achieving the purpose of synchronous speed testing. With this structure, the first clock input terminal 400 serves as the external clock signal source for both the selection module 500 and the clock controller 300 at the same time, eliminating the need to set the second clock input terminal 320, reducing the number of ports, and facilitating the simplification of the circuit structure.

[0033] In a chip, ports (IO ports, pins) are very precious and limited resources. Therefore, by using the first clock terminal 400 as the external clock signal source for both the selection module 500 and the clock controller 300 at the same time, the port occupancy is reduced, achieving the effect of saving ports, which is beneficial to saving the chip area cost, or using the saved ports for other function implementations, which is beneficial to enhancing the chip function and improving the competitiveness of the chip function.

[0034] Refer to Figure 1 and Figure 2 In some embodiments of the present invention, the selection module 500 includes a first data selector 510 corresponding one-to-one to the clock controller 300. The first input terminal of the first data selector 510 is connected to the corresponding clock controller 300, the second input terminal of the first data selector 510 is connected to the first clock input terminal 400, the output terminal of the first data selector 510 is connected to the high-frequency logic module 100, and the controlled terminal of the first data selector 510 is connected to the mode control terminal 600.

[0035] The first data selector 510 selects the conducting channel according to the level of the controlled terminal, that is, the level of the mode control terminal 600. During low-speed testing, the first data selector 510 selects the externally input test clock obtained from the first input terminal and transmits it to the high-frequency logic module 100; during synchronous speed testing, the first data selector 510 selects the synchronous speed test clock signal obtained from the clock controller 300 at the second input and transmits it to the high-frequency logic module 100. The first data selector 510 can prevent the clock selector from having an impact during low-speed testing, improve the reliability of the testing, and has simple control, which is beneficial to facilitating the test design.

[0036] Refer to Figure 1 and Figure 2, in some embodiments of the present invention, the selection module 500 further includes at least one second data selector 520. The input end of the second data selector 520 is connected to the first clock input end 400, the output end of the second data selector 520 is connected to the low-frequency logic module 200, and the controlled end of the second data selector 520 is connected to the mode control end 600.

[0037] The second data selector 520 selects the conducting channel according to the level of the controlled end, that is, the level of the mode control end 600. During low-speed testing, the second data selector 520 selects the external test clock obtained from the first input end and transmits it to the low-frequency logic module 200. During same-speed testing, the low-frequency logic module 200 does not need to participate in the same-speed testing, and the second data selector 520 does not need to transmit the same-speed test clock signal to the low-frequency logic module 200. Adopting the second data selector structure is beneficial to improving the reliability of testing, and the control is simple, which is convenient for test design.

[0038] Reference Figure 1 , in some embodiments of the present invention, the first input end of the second data selector 520 is connected to the crystal oscillator clock input end 310, and the second input end of the second data selector 520 is connected to the first clock input end 400.

[0039] With this structure, during same-speed testing, the second data selector 520 transmits the crystal oscillator clock signal to the low-frequency logic module 200, enabling the low-frequency logic module 200 to simulate the actual working state, which helps to make the same-speed testing of the high-frequency logic module 100 more stable.

[0040] Refer to Figure 2 , in some embodiments of the present invention, an inverter 700 is further included. The mode control end 600 is respectively connected to the controlled end of the clock controller 300 and the input end of the inverter 700, and the output end of the inverter 700 is connected to the controlled end of the selection module 500.

[0041] For convenient testing, the clock controller 300 generally has a controlled terminal. The mode control terminal 600 is connected to the clock controller 300 and can control the operation of the clock controller 300. Moreover, the mode control terminal 600 is connected to the controlled terminal of the selection module 500 through an inverter. During low-speed testing, the clock controller 300 stops working, and the selection module 500 makes the external test clock signal at the first clock input terminal 400 be transmitted to the high-frequency logic module 100 and the low-frequency logic module 200. During same-speed testing, the clock controller 300 starts to work, and the selection module 500 makes the same-speed test clock signal generated by the clock controller 300 be transmitted to the high-frequency logic module 100. With this structure, the mode control terminal 600 can control both the clock controller 300 and the selection module 500 simultaneously, without the need to separately set a port for controlling the clock controller 300, which is beneficial to simplifying the circuit structure and making the control more convenient.

[0042] Since the ports in the chip are precious and limited resources, therefore, by controlling the operation of the clock controller 300 and the selection module 500 simultaneously through the mode control terminal 600, there is no need to set two corresponding control terminals, reducing port occupancy, achieving the effect of saving ports, being beneficial to saving the chip area cost, or using the saved ports for other function implementations, being beneficial to the design and implementation of other functions of the chip, and improving the utilization efficiency of the ports.

[0043] Refer to Figure 2 , in some embodiments of the present invention, it further includes a first conduction control unit 311 and a second conduction control unit 312. The first clock input terminal 400 is respectively connected to the input terminal of the first conduction control unit 311 and the input terminal of the second conduction control unit 312. The output terminal of the first conduction control unit 311 is connected to the clock controller 300. The output terminal of the second conduction control unit 312 is connected to the second input terminal of the selection module 500. The controlled terminal of the first conduction control unit 311 is connected to the mode control terminal 600. The controlled terminal of the second conduction control unit 312 is connected to the output terminal of the inverter 700.

[0044] During low-speed testing, the mode control terminal 600 turns off the first conduction control unit 311 and turns on the second conduction control unit 312, enabling the external test clock signal at the first clock input terminal 400 to be transmitted to the selection module 500 through the second conduction control unit 312, and the selection module 500 transmits the external test clock signal to the high-frequency logic module 100 and the low-frequency logic module 200; during same-speed testing, the mode control terminal 600 turns on the first conduction control unit 311 and turns off the second conduction control unit 312, allowing the external test clock signal at the first clock input terminal 400 to be transmitted to the clock controller 300 through the first conduction control unit 311. Subsequently, the clock controller 300 can generate a same-speed test clock signal and transmit it to the selection module 500, and the selection module 500 transmits the same-speed test clock signal to the high-frequency logic module 100. With this structure, the mode control terminal 600 can control the input signal at the first clock input terminal 400 to be transmitted to the selection module 500 or the clock controller 300 by controlling the first conduction control unit 311 and the second conduction control unit 312, that is, the selection module 500 and the clock controller 300 share the same port to obtain the external test clock signal, which is conducive to reducing the number of test ports, simplifying test control, and facilitating test design.

[0045] By adopting the first conduction control unit 311 and the second conduction control unit 312, the external test clock signals of the clock controller 300 and the selection module 500 are sourced from the same port, namely the first clock input terminal 400, which can reduce the port resources occupied by the chip, achieve the effect of saving ports, is conducive to saving the chip area cost, and makes test control more convenient; or the saved ports can be used for other function implementations, which is conducive to the function expansion of the chip.

[0046] The first conduction control unit 311 and the second conduction control unit 312 can be implemented as AND gate circuits.

[0047] Refer to Figure 1 In some embodiments of the present invention, the high-frequency logic module 100 includes a first timing unit 110, a high-frequency logic unit 120, a first scan input terminal 130, a first scan enable terminal 140, and a first capture output terminal 150. The input terminal of the first timing unit 110 is connected to the first scan input terminal 130, the enable terminal of the first timing unit 110 is connected to the first scan enable terminal 140, the clock terminal of the first timing unit 110 is connected to the output terminal of the selection module 500, the high-frequency logic unit 120 is connected to the first timing unit 110, and the output terminal of the first timing unit 110 is connected to the first capture output terminal 150.

[0048] In the displacement input stage, control the first scan enable terminal 140 so that the first timing unit 110 is in the input state, and input the test vector into the first timing unit 110 through the first scan input terminal 130; in the capture output stage, change the level of the first scan enable terminal 140 so that the first timing unit 110 is in the normal working state, and the first timing unit 110 is connected to the high-frequency logic unit 120 to work, and then the result vector can be obtained at the first capture output terminal 150. According to whether the test vector corresponds to the result vector, it can be known whether there is a defect in the high-frequency logic unit 120, and the effect of detecting whether there is a defect in the chip is achieved.

[0049] Referring to Figure 2 , in some embodiments of the present invention, the low-frequency logic module 200 includes a second timing unit 210, a low-frequency logic unit 220, a second scan input terminal 230, a second scan enable terminal 240, and a second capture output terminal 250. The input terminal of the second timing unit 210 is connected to the second scan input terminal 230, the enable terminal of the second timing unit 210 is connected to the second scan enable terminal 240, the clock terminal of the second timing unit 210 is connected to the output terminal of the selection module 500, the low-frequency logic unit 220 is connected to the second timing unit 210, and the output terminal of the second timing unit 210 is connected to the second capture output terminal 250.

[0050] In the displacement input stage, control the second scan enable terminal 240 so that the second timing unit 210 is in the input state, and input the test vector into the second timing unit 210 through the second scan input terminal 230; in the capture output stage, change the level of the second scan enable terminal 240 so that the second timing unit 210 is in the normal working state, and the second timing unit 210 is connected to the low-frequency logic unit 220 to work, and then the result vector can be obtained at the first capture output terminal 150. According to whether the test vector corresponds to the result vector, it can be known whether there is a defect in the low-frequency logic unit 220, and the effect of detecting whether there is a defect in the chip is achieved.

[0051] The first timing unit 110 and the second timing unit 120 can be implemented in a manner including a plurality of cascaded scan flip-flops. The high-frequency logic unit 120 and the low-frequency logic unit 220 can be implemented in a manner including logic circuits such as AND gates, OR gates, exclusive-NOR gates, and exclusive-OR gates.

[0052] Referring to Figure 1 and Figure 2 , the chip according to the second aspect embodiment of the present invention includes an integrated circuit, and the integrated circuit includes the above-mentioned chip scan test circuit.

[0053] When appropriate electrical frequencies or signals are input to each port of the integrated circuit for chip scan testing, specifically: a test clock signal is input to the first clock input terminal 400. When slow testing is required, by controlling the level of the mode control terminal 600, the selection module 500 is made to select the slow test clock signal input from the second input terminal and output it to the high-frequency logic module 100 and the low-frequency logic module 200, so as to perform slow testing on the high-frequency logic module 100 and the low-frequency logic module 200. When same-speed testing is required, the level of the mode control terminal 600 is changed, so that the selection module 500 selects the clock signal input from the first input terminal, that is, the same-speed test clock signal generated by the clock controller 300, and outputs it to the high-frequency logic module 100, to achieve same-speed testing of the high-frequency logic module 100. The same-speed test clock signal does not need to be output to the low-frequency logic module 200. By changing the level of the mode control terminal 600, the slow test mode or the same-speed test mode can be selected. In this way, by controlling the clock signal output to the high-frequency logic module 100 and the low-frequency logic module 200 through the selection module 500, the low-frequency logic module 200 can obtain the test clock signal without being connected after the clock controller 300, which is beneficial to improving the test coverage rate. At the same time, there is no need to insert the corresponding clock controller 300 in front of the low-frequency logic module 200, which is beneficial to reducing the number of on-chip clock controllers 300, saving chip area and reducing costs.

[0054] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0055] Of course, the present invention is not limited to the above-described embodiments. Those skilled in the art can also make equivalent deformations or substitutions without departing from the spirit of the present invention, and these equivalent deformations or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A chip scanning test circuit, characterized in that Comprising: At least one high-frequency logic module (100) and at least one low-frequency logic module (200); At least one clock controller (300); A first clock input terminal (400) for receiving an external test clock signal; A selection module (500); A mode control terminal (600) connected to the controlled terminal of the selection module (500); A crystal oscillator clock input terminal (310); The selection module (500) includes a first data selector (510) corresponding one-to-one to the clock controller (300). The first input terminal of the first data selector (510) is connected to the corresponding clock controller (300), the second input terminal of the first data selector (510) is connected to the first clock input terminal (400), the output terminal of the first data selector (510) is connected to the high-frequency logic module (100), and the controlled terminal of the first data selector (510) is connected to the mode control terminal (600); The selection module (500) further includes at least one second data selector (520). The first input terminal of the second data selector (520) is connected to the crystal oscillator clock input terminal (310), the second input terminal of the second data selector (520) is connected to the first clock input terminal (400), the output terminal of the second data selector (520) is connected to the low-frequency logic module (200), and the controlled terminal of the second data selector (520) is connected to the mode control terminal (600).

2. The chip scanning and testing circuit according to claim 1, wherein: It further includes a second clock input terminal (320). The first input terminal of the clock controller (300) is connected to the crystal oscillator clock input terminal (310), and the second input terminal of the clock controller (300) is connected to the second clock input terminal (320).

3. A chip scanning test circuit according to claim 1, characterized in that: The first input terminal of the clock controller (300) is connected to the crystal oscillator clock input terminal (310), and the second input terminal of the clock controller (300) is connected to the first clock input terminal (400).

4. A chip scanning test circuit according to claim 1, wherein: The high-frequency logic module (100) includes a first timing unit (110), a high-frequency logic unit (120), a first scan input terminal (130), a first scan enable terminal (140), and a first capture output terminal (150). The input terminal of the first timing unit (110) is connected to the first scan input terminal (130), the enable terminal of the first timing unit (110) is connected to the first scan enable terminal (140), the clock terminal of the first timing unit (110) is connected to the output terminal of the first data selector (510), the high-frequency logic unit (120) is connected to the first timing unit (110), and the output terminal of the first timing unit (110) is connected to the first capture output terminal (150).

5. The chip scanning and testing circuit according to claim 1, characterized in that: The low-frequency logic module (200) includes a second timing unit (210), a low-frequency logic unit (220), a second scan input terminal (230), a second scan enable terminal (240), and a second capture output terminal (250). The input terminal of the second timing unit (210) is connected to the second scan input terminal (230), the enable terminal of the second timing unit (210) is connected to the second scan enable terminal (240), the clock terminal of the second timing unit (210) is connected to the output terminal of the second data selector (520), the low-frequency logic unit (220) is connected to the second timing unit (210), and the output terminal of the second timing unit (210) is connected to the second capture output terminal (250).

6. Chip, characterized in that: An integrated circuit is included, and the integrated circuit includes a chip scan test circuit as described in any one of claims 1 to 5.

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