Parity check circuit testing method based on bubbling method
Through the parity check circuit testing method based on the bubble method, the test code is written using the bubble sorting principle, which solves the problem of limited selection of test codes in the existing technology, and achieves efficient and comprehensive testing.
Patent Information
- Application Number
- CN202211291222.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-10-21
- Publication Date
- 2025-03-14
- Estimated Expiration
- 2042-10-21
AI Technical Summary
When testing parity check circuits, the selection of test codes is limited, resulting in unguaranteed test quality, easy to miss tests or too low test efficiency, and existing testing equipment is difficult to compete with.
A parity check circuit testing method based on the bubble method is adopted. By obtaining the input pin parameters of the circuit to be tested, the test code is written in combination with the bubble sorting principle, and it is imported into the vector RAM of the ATE tester for testing.
This method can comprehensively test the quality of XOR gates at all levels, ensure the quality of the test and avoid missed tests. At the same time, due to the small number of test codes and the testing efficiency is greatly improved, the existing ATE test machines can also effectively support it.
Smart Images
Figure CN115469213B_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of large-scale integrated circuit production testing, in particular to a parity check circuit testing method based on a bubbling method. Background Art
[0002] In large-scale integrated circuits, in order to improve the accuracy of received and sent codes and eliminate interference, a check function is often added, among which parity check circuit is also a relatively commonly used one.
[0003] The parity check circuit is mainly composed of multiple levels of XOR gates. When there are an even number of 1s in all inputs, the output is low, and when there are an odd number of 1s in all inputs, the output is high.
[0004] The parity check circuit is tested to determine the quality of each level of XOR gates in the circuit. The steps usually include: writing test code according to the circuit logic function; inputting the test code into the parity check circuit and observing its circuit output; when the output voltage fully meets the logic function, the circuit is qualified; when the output voltage does not fully meet the logic function, the circuit is unqualified.
[0005] Currently, there are two methods for selecting test codes:
[0006] One is to select typical codes as test codes, such as all 1, all 0, 1010..., 0101..., etc., as the input of the parity check circuit test. However, this method will result in the inability to fully test the functions of multi-level logic gates, resulting in the leakage of the circuit.
[0007] The other method is to use the full code as the test code, that is, according to the number of pins of the circuit, all possible combination codes are used as test codes as the input of the parity check circuit test. This method can be implemented when the number of parity check bits is small. As the number of bits increases, the number of test codes also increases rapidly. For example, for a set of 24-bit parity check circuits, all test codes have reached 2 24 =16777216 combinations. For ATE testers, the vector depth of the test code can no longer meet the requirements.
[0008] In summary, the problems existing in the prior art are: when testing the parity check circuit, the test quality is not guaranteed due to the limitation of the test code selection, which may lead to missed circuits or too low test efficiency, and the existing test equipment is not competent. Summary of the invention
[0009] The object of the present invention is to provide a parity check circuit testing method based on a bubbling method, which has guaranteed test quality and high test efficiency.
[0010] The technical solution to achieve the purpose of the present invention is:
[0011] A parity check circuit testing method based on a bubbling method comprises the following steps:
[0012] (10) Test code writing: Write the test code based on the input pin parameters of the parity check circuit to be tested and in combination with the bubble sort principle;
[0013] (20) Test code import: import the test code into the vector RAM of the ATE test machine;
[0014] (30) Circuit test: Test the parity check circuit to be tested based on the imported test code.
[0015] Preferably, the (10) test code writing step includes:
[0016] (11) Input pin parameter acquisition: obtain the number and sequence of input pins of the parity check circuit to be tested;
[0017] (12) Single test code determination: set one input pin high and the other input pins low to obtain a test code;
[0018] (13) Determine all test codes: Replace the input pins that are set high one by one, and set the remaining input pins low to obtain all test codes.
[0019] As another preferred embodiment, the (10) test code writing step includes:
[0020] (101) Input pin parameter acquisition: obtain the number and sequence of input pins of the parity check circuit to be tested;
[0021] (102) Single test code determination: set one input pin low and the other input pins high to obtain a test code;
[0022] (103) All test codes are determined: the input pins that are set low are replaced one by one, and the remaining input pins are set high to obtain all test codes.
[0023] Compared with the prior art, the present invention has the following significant advantages:
[0024] 1. Test quality is guaranteed: Based on the bubble sorting principle, the present invention changes the state of logic gates at all levels in turn by changing the pin state, and can comprehensively test the quality of XOR gates at all levels, so the test quality is guaranteed. It can effectively avoid the leakage of the missed circuit.
[0025] 2. High test efficiency: The present invention only requires a test code with the same number of check bits, the test development is simple, the number of test codes is small, the test time is greatly shortened, and the test efficiency is improved.
[0026] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 It is the main flow chart of the parity check circuit testing method based on the bubbling method of the present invention.
[0028] Figure 2 yes Figure 1 Flowchart of the test code writing steps.
[0029] Figure 3 It is a working principle diagram of the parity check circuit testing method based on the bubbling method of the present invention. DETAILED DESCRIPTION
[0030] like Figure 1 As shown, the parity check circuit testing method based on the bubbling method of the present invention comprises the following steps:
[0031] (10) Test code writing: Write the test code based on the input pin parameters of the parity check circuit to be tested and in combination with the bubble sort principle.
[0032] like Figure 2 As shown, the (10) test code writing step includes:
[0033] (11) Input pin parameter acquisition: obtain the number and sequence of input pins of the parity check circuit to be tested;
[0034] (12) Single test code determination: set one input pin high and the other input pins low to obtain a test code;
[0035] (13) Determine all test codes: Replace the input pins that are set high one by one, and set the remaining input pins low to obtain all test codes.
[0036] In this way, the number of all test codes is equal to the number of input pins of the parity check circuit to be tested, and the vector depth of the test code makes the existing ATE test machine sufficient.
[0037] For example, if the input pin of an 8-bit parity check circuit is configured, all the test codes are as follows:
[0038] (10 00 00 00), (01 00 00 00), (00 10 00 00), (00 01 00 00),
[0039] (00 00 10 00), (00 00 01 00), (00 00 00 10), (00 00 00 01).
[0040] That is, for an n-bit parity check circuit, only n combinations are needed to fully check all logic gates and ports of the XOR gate array. There will be no missed tests, and the test code number will not exceed the capacity of the ATE tester, and the test efficiency is high.
[0041] (20) Test code import: Import the test code into the vector RAM of the ATE test machine.
[0042] (30) Circuit test: Test the parity check circuit to be tested based on the imported test code.
[0043] The above-mentioned (20) test code introduction and (30) circuit test are the same as the prior art and are not the focus of the present invention, and will not be described in detail here.
[0044] Figure 3 It is a working principle diagram of the parity check circuit testing method based on the bubbling method of the present invention.
[0045] like Figure 3 As shown, the number of test codes written according to the number and sequence of input pins of the parity check circuit to be tested and combined with the bubble sort principle is equal to the number of input pins. The difference is that in each test code, only one input pin is set high, and the other input pins are set low.
[0046] Use the existing test program to test the parity check circuit of each test code in turn, such as Figure 3 As shown in the figure, only when A1 is high and the rest are low, the channels and each level of logic gates related to A1 will flip, so that it can be verified whether the logic gates at each level are working properly. By changing the state of each pin in turn in this way, each channel, each logic gate, and each line will eventually switch between different states. In this way, the integrity of the entire circuit function can be tested. If the flip logic is incorrect, it will be directly judged as Fail.
[0047] As another preferred solution, the test code writing step (10) may also be performed according to the following process:
[0048] (101) Input pin parameter acquisition: obtain the number and sequence of input pins of the parity check circuit to be tested;
[0049] (102) Single test code determination: set one input pin low and the other input pins high to obtain a test code;
[0050] (103) All test codes are determined: the input pins that are set low are replaced one by one, and the remaining input pins are set high to obtain all test codes.
[0051] Likewise, the number of all test codes is equal to the number of input pins of the parity check circuit to be tested, and the vector depth of the test code makes the existing ATE test machine sufficient for the task.
[0052] The difference between this preferred solution and the previous solution is that the high and low states of all pins are reversed, that is: one input pin is set low and the other input pins are set high to obtain a test code; the low input pins are replaced one by one and the other input pins are set high to obtain all test codes.
[0053] For example, when the number of input pins of the parity check circuit to be tested is 8, all the test codes are as follows:
[0054] (01 11 11 11), (10 11 11 11), (11 01 11 11), (11 10 11 11),
[0055] (11 11 01 11), (11 11 10 11), (11 11 11 01), (11 11 11 10).
[0056] In addition to the advantages of guaranteed test quality and high test efficiency, this preferred solution also has a better effect in that only one pin is in a low state at a time and the other pins are in a high state, which plays a certain screening role for circuits with leakage pins.
Claims
1. A parity check circuit testing method based on a bubbling method, comprising the following steps: (10) Test code writing: Write the test code based on the input pin parameters of the parity check circuit to be tested and in combination with the bubble sort principle; (20) Test code import: import the test code into the vector RAM of the ATE test machine; (30) Circuit test: Test the parity check circuit to be tested according to the imported test code; It is characterized in that The (10) test code writing step includes: (11) Input pin parameter acquisition: obtain the number and sequence of input pins of the parity check circuit to be tested; (12) Single test code determination: set one input pin high and the other input pins low to obtain a test code; (13) Determine all test codes: Replace the input pins that are set high one by one, and set the remaining input pins low to obtain all test codes.
2. The parity check circuit testing method according to claim 1, characterized in that: When the number of input pins of the parity check circuit to be tested is 8, all the test codes are as follows: （10 00 00 00），（01 00 00 00），（00 10 00 00），（00 01 00 00）， （00 00 10 00），（00 00 01 00），（00 00 00 10），（00 00 00 01）。 3. A parity check circuit testing method based on a bubbling method, comprising the following steps: (10) Test code writing: Write the test code based on the input pin parameters of the parity check circuit to be tested and in combination with the bubble sort principle; (20) Test code import: import the test code into the vector RAM of the ATE test machine; (30) Circuit test: Test the parity check circuit to be tested according to the imported test code; It is characterized in that The (10) test code writing step includes: (101) Input pin parameter acquisition: obtain the number and sequence of input pins of the parity check circuit to be tested; (102) Single test code determination: set one input pin low and the other input pins high to obtain a test code; (103) All test codes are determined: the input pins that are set low are replaced one by one, and the remaining input pins are set high to obtain all test codes.
4. The parity check circuit testing method according to claim 3, characterized in that: When the number of input pins of the parity check circuit to be tested is 8, all the test codes are as follows: （01 11 11 11），（10 11 11 11），（11 01 11 11），（11 10 11 11）， （11 11 01 11），（11 11 10 11），（11 11 11 01），（11 11 11 10）。