A pW-level CMOS voltage reference source with optimized linear sensitivity

Abstract

The present invention discloses a pW-level CMOS voltage reference source with optimized linear sensitivity, which specifically includes a startup circuit module and a core reference source circuit module. The startup circuit module is used to enable the reference source to get rid of the degeneracy point and enter the normal working state during startup. The core reference source circuit module includes an active load for generating the reference voltage V<subgt;ref< / subgt>. Compared with the traditional voltage reference source technology, this method does not use triodes and resistors, has a simple structure, and occupies a small chip area. A method for optimizing linear sensitivity is proposed, which reversely utilizes the DIBL effect of transistors to greatly reduce the linear sensitivity of the reference voltage and obtain a self-biased ultra-low power consumption circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of voltage reference sources, and more specifically, to a pW-level CMOS voltage reference source with optimized linear sensitivity. Background Art

[0002] In recent years, as one of the basic building blocks of integrated circuits in many energy-constrained microsystems, voltage reference sources need to consume nano-watt or pico-watt power. The bandgap reference is the most commonly used voltage reference structure. However, the use of bipolar junction transistors limits the reduction of power supply voltage and power consumption. In addition, large resistors are usually required in this structure, which wastes chip area and increases costs. In contrast, CMOS voltage reference sources are very suitable for ultra-low voltage and ultra-low power consumption applications and have become a research hotspot in academia and industry at home and abroad. The power supply voltages provided in micro-systems such as energy harvesters usually have a wide range and high noise, which will have a certain impact on the output of the voltage reference source. Therefore, it is necessary to study an ultra-low power CMOS voltage reference source with excellent linear sensitivity.

[0003] In the prior art, in order to reduce the power supply dependence, some solutions use operational amplifiers for voltage clamping. However, this will increase the number of transistors, make the circuit structure more complex, and sacrifice chip area at the same time. In addition, in some other solutions, cascode current mirrors are also used to shield the influence of power supply fluctuations on the output reference, which sacrifices the margin of the operating voltage and also increases power consumption.

[0004] A method for optimizing linear sensitivity is disclosed in the prior art. This method uses the way of increasing the bias current in the circuit to reduce the influence of current disturbance on the reference voltage. This solution directly sacrifices the bias current as the price, which not only leads to an increase in the overall power consumption, but also makes the improvement of linear sensitivity very limited.

[0005] Therefore, in combination with the above requirements and the defects of sacrificing bias current, complex circuit structure and increased power consumption in the prior art, the present application proposes a pW-level CMOS voltage reference source with optimized linear sensitivity. Summary of the Invention

[0006] The present invention provides a pW-level CMOS voltage reference source with optimized linear sensitivity, which has a simple structure, occupies a small chip area, can reversely utilize the DIBL effect of transistors, and greatly reduces the linear sensitivity of the reference voltage.

[0007] The primary object of the present invention is to solve the above technical problems, and the technical solution of the present invention is as follows:

[0008] The present invention provides a pW-level CMOS voltage reference source with optimized linear sensitivity, including a startup circuit module and a core reference source circuit module. The startup circuit module is used to enable the reference source to get rid of the degeneracy point and enter the normal working state during startup. The core reference source circuit module includes an active load for generating a reference voltage V ref .

[0009] Furthermore, the core reference source circuit module includes: a first low-threshold PMOS transistor M1, a second low-threshold PMOS transistor M2, a first low-threshold NMOS transistor M3, a first high-threshold NMOS transistor M4, a second low-threshold NMOS transistor M5, a third low-threshold NMOS transistor M6, a fourth low-threshold NMOS transistor M7, and a third low-threshold PMOS transistor M8.

[0010] Furthermore, the startup circuit module includes a fifth low-threshold NMOS transistor M9, a fourth low-threshold PMOS transistor M10, a fifth low-threshold PMOS transistor M11, a sixth low-threshold PMOS transistor M12, a seventh low-threshold PMOS transistor M13, and a fifth low-threshold NMOS transistor M14. The first high-threshold NMOS transistor M4 and the second low-threshold NMOS transistor M5 form an active load.

[0011] Among them, the power supply voltage VDD is respectively input to the source electrodes of the first low-threshold PMOS transistor M1, the second low-threshold PMOS transistor M2, the third low-threshold PMOS transistor M8, and the seventh low-threshold PMOS transistor M13.

[0012] Furthermore, the gate of the first low-threshold PMOS transistor M1 is respectively connected to the gates of the second low-threshold PMOS transistor M2 and the third low-threshold PMOS transistor M8 through the drain of the fifth low-threshold NMOS transistor M14. The drain of the first low-threshold PMOS transistor M1 is respectively connected to the drain and gate of the first low-threshold NMOS transistor M3, the gate of the first high-threshold NMOS transistor M4, and the gate of the second low-threshold NMOS transistor M5. The source electrode of the first high-threshold NMOS transistor M4 is grounded. The source electrode of the first low-threshold NMOS transistor M3 and the drain of the first high-threshold NMOS transistor M4 are connected to the reference voltage terminal for generating the reference voltage V ref .

[0013] Furthermore, the drain of the second low-threshold PMOS transistor M2 is respectively connected to the drain of the fifth low-threshold NMOS transistor M14 and the drain of the second low-threshold NMOS transistor M5. The source electrode of the second low-threshold NMOS transistor M5 is connected to the drain of the third low-threshold NMOS transistor M6, and the gate of the third low-threshold NMOS transistor M6 is connected to the reference voltage terminal.

[0014] Further, the drain of the third low-threshold PMOS transistor M8 is connected to the source of the third low-threshold NMOS transistor M6, the gate and drain of the fourth low-threshold NMOS transistor M7 respectively, wherein the source of the fourth low-threshold NMOS transistor M7 is grounded, and the third low-threshold PMOS transistor M8 and the fourth low-threshold NMOS transistor M7 are used to optimize the linear sensitivity.

[0015] Further, the gate and drain of the seventh low-threshold PMOS transistor M13 are both connected to the source of the sixth low-threshold PMOS transistor M12, the gate and drain of the sixth low-threshold PMOS transistor M12 are both connected to the source of the fifth low-threshold PMOS transistor M11, and the gate and drain of the fifth low-threshold PMOS transistor M11 are both connected to the source of the fourth low-threshold PMOS transistor M10.

[0016] Further, the reference voltage terminal is connected to the gate of the fourth low-threshold PMOS transistor M10 and the gate of the fifth low-threshold NMOS transistor M9 respectively. The drain of the fourth low-threshold PMOS transistor M10 and the drain of the fifth low-threshold NMOS transistor M9 are both connected to the gate of the fifth low-threshold NMOS transistor M14. The fourth low-threshold PMOS transistor M10 and the fifth low-threshold NMOS transistor M9 are used to output a relatively high voltage to the fifth low-threshold NMOS transistor M14 to turn it on; wherein the source of the fifth low-threshold NMOS transistor M14 is grounded, and the source of the fifth low-threshold NMOS transistor M9 is grounded.

[0017] Further, the first high-threshold NMOS transistor M4 is a high-threshold 5V transistor, and all the remaining MOS transistors are low-threshold 1.8V transistors, and all the transistors operate in the subthreshold region.

[0018] Further, the second low-threshold NMOS transistor M5 and the third low-threshold NMOS transistor M6 are current source transistors, and the gate voltages of the second low-threshold NMOS transistor M5 and the third low-threshold NMOS transistor M6 are directly provided by the active load first high-threshold NMOS transistor M4 and the second low-threshold NMOS transistor M5 without an additional biasing structure.

[0019] Wherein, the first low-threshold PMOS transistor M1 and the second low-threshold PMOS transistor M2 form a current mirror. The second low-threshold PMOS transistor M2 copies the bias current generated by the current source transistors second low-threshold NMOS transistor M5 and third low-threshold NMOS transistor M6 to the first low-threshold PMOS transistor M1, and the first low-threshold PMOS transistor M1 injects the current into the active load first high-threshold NMOS transistor M4 and the second low-threshold NMOS transistor M5.

[0020] Further, when all the transistors of the core reference source circuit module are in the subthreshold region operating state, the mathematical expression form of the subthreshold current is:

[0021]

[0022] Among them, i = 1, 2, 3,... represents the number of MOS transistors, μ is the mobility, C ox is the gate oxide capacitance, m is the subthreshold slope, is the thermal voltage, is the width-to-length ratio of each transistor.

[0023] Furthermore, the reference voltage V ref is the difference between the gate-source voltage V GS3 of the first low-threshold NMOS transistor M3 and the gate-source voltage V GS4 of the first high-threshold NMOS transistor M4, and its mathematical expression is:

[0024]

[0025] Among them, ideally, the reference voltage should not change with the variation of the power supply voltage VDD. Since the gate-source voltage V GS3 of the first low-threshold NMOS transistor M3 has V T , so it has a positive temperature coefficient. The gate-source voltage V GS4 of the first high-threshold NMOS transistor M4 has a threshold voltage difference V TH4 -V TH3 , so it has a negative temperature coefficient; by changing the width-to-length ratio K3 of the first low-threshold NMOS transistor M3 and the width-to-length ratio K4 of the first high-threshold NMOS transistor M4, the positive temperature coefficient can be changed, and then a reference voltage V ref independent of temperature can be obtained by superimposing with the negative temperature coefficient.

[0026] Furthermore, the process of the startup circuit module enabling the circuit to power on quickly and work normally is as follows: The power supply voltage VDD gradually increases, and the reference voltage V ref is input to the gates of the fourth low-threshold PMOS transistor M10 and the fifth low-threshold NMOS transistor M9 with a lower initial value. Among them, the fourth low-threshold PMOS transistor M10 and the fifth low-threshold NMOS transistor M9 act as an inverter to output a higher voltage to the gate of the fifth low-threshold NMOS transistor M14, making it conduct. The drain of the fifth low-threshold NMOS transistor M14 is connected to point A, and point A is respectively connected to the gates of the first low-threshold PMOS transistor M1, the gate and drain of the second low-threshold PMOS transistor M2, the drain of the second low-threshold NMOS transistor M5, and the gate of the third low-threshold PMOS transistor M8, making the second low-threshold PMOS transistor M2 conduct; as the power supply voltage VDD gradually increases, the reference voltage V refWhen it is lifted to the normal output value, the fourth-lowest threshold PMOS transistor M10 and the fifth-lowest threshold NMOS transistor M9 turn off the fifth-lowest threshold NMOS transistor M14, causing the startup circuit module to stop working and completing the startup step.

[0027] Further, the output of the reference voltage V ref is related to the current flowing through the first-lowest threshold NMOS transistor M3 and the first-high threshold NMOS transistor M4. When the current flowing through the first-lowest threshold NMOS transistor M3 and the first-high threshold NMOS transistor M4 fluctuates with the fluctuation of the power supply voltage VDD, V ref will also fluctuate. The reference voltage V ref obtained according to the difference between the subthreshold slope m3 of the first-lowest threshold NMOS transistor M3 and the subthreshold slope m4 of the first-high threshold NMOS transistor M4 is:

[0028]

[0029]

[0030] wherein, I load is the current flowing through the first-lowest threshold NMOS transistor M3 and the first-high threshold NMOS transistor M4. By stacking the second-lowest threshold NMOS transistor M5 on the third-lowest threshold NMOS transistor M6, the disturbance of the power supply voltage VDD on the drain-source voltage V DS6 of the third-lowest threshold NMOS transistor M6 can be reduced, thereby obtaining a relatively stable bias current I BIAS .

[0031] Further, the relatively stable bias current I BIAS after being copied to the first-lowest threshold PMOS transistor M1 becomes I load which will fluctuate due to the DIBL effect of the first-lowest threshold PMOS transistor M1. By using the method of the fourth-lowest threshold NMOS transistor M7 and the third-lowest threshold PMOS transistor M8 to reverse the DIBL effect, the DIBL effect of the first-lowest threshold PMOS transistor M1 can be effectively weakened, thereby weakening the change of I load and achieving the purpose of optimizing the linear sensitivity.

[0032] Further, the process of optimizing the linear sensitivity is specifically as follows: when the power supply voltage VDD changes by Δvdd, the current fluctuation ΔI1 caused by the change of the drain-source voltage V GS1 of the first-lowest threshold PMOS transistor M1 is in the same direction as the change of Δvdd, while the gate-source voltage V DS1The current fluctuation ΔI2 caused by the change is opposite to the change direction of Δvdd. Through the fourth low-threshold NMOS transistor M7 and the third low-threshold PMOS transistor M8, the gate-source voltage V of the first low-threshold PMOS transistor M1 can be made GS1 vary in the reverse direction with the power supply voltage VDD, so that after the superposition of ΔI1 and ΔI2, the change of I load is weakened, achieving the purpose of optimizing the sensitivity.

[0033] Furthermore, the functions of the fourth low-threshold NMOS transistor M7 and the third low-threshold PMOS transistor M8 are specifically as follows: the gate and drain of the fourth low-threshold NMOS transistor M7 are short-circuited to form a diode connection type, which is used to convert current into voltage. When the power supply voltage VDD increases, the current flowing through the third low-threshold PMOS transistor M8 increases sharply, causing the gate-source voltage V of the four low-threshold NMOS transistor M7 GS7 to rise rapidly. When the rising speed of V GS7 is greater than the rising speed of the reference voltage V ref , the drain-source voltage V of the third low-threshold NMOS transistor M6 DS6 will keep decreasing, resulting in the gate-source voltage V of the second low-threshold PMOS transistor M2 GS2 , that is, the gate-source voltage V of the first low-threshold PMOS transistor M1 GS1 to decrease as the power supply voltage VDD increases. Through the compensation effect, the change of I load caused by the fluctuation with the power supply voltage VDD is weakened.

[0034] Compared with the prior art, the beneficial effects of the technical solution of the present invention are:

[0035] The present invention provides a pW-level CMOS voltage reference source with optimized linear sensitivity, which is constructed by all MOS transistors, has a simple circuit structure, occupies a small chip area, and has a low cost; only by means of two MOS transistors, the DIBL effect of the transistor is utilized in reverse to achieve optimized linear sensitivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic circuit diagram of a pW-level CMOS voltage reference source with optimized linear sensitivity according to the present invention.

[0037] Figure 2 is a schematic diagram of optimizing the linear sensitivity according to the present invention.

[0038] Figure 3 is a curve of V GS1 and V DS1 of the first low-threshold PMOS transistor M1 of the present invention varying with VDD.

[0039] Figure 4 is the current I before and after using the third low-threshold PMOS transistor M8 according to the present invention.load Curve varying with VDD

[0040] Figure 5 is the reference voltage V of the present invention ref Curve varying with power supply voltage VDD

[0041] Figure 6 is the curve of the power consumption of the reference source varying with temperature within the range of 0 °C to 100 °C of the present invention Detailed implementation manners

[0042] In order to more clearly understand the above objects, features and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners. It should be noted that, without conflict, the embodiments of the present application and the features in the embodiments can be combined with each other

[0043] Many specific details are set forth in the following description in order to fully understand the present invention. However, the present invention can also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited by the specific embodiments disclosed below

[0044] Embodiment 1

[0045] As Figure 1 shown, the present invention provides a pW-level CMOS voltage reference source with optimized linear sensitivity, including a startup circuit module and a core reference source circuit module. The startup circuit module is used to make the reference source get rid of the degeneracy point and enter the normal working state during startup. The core reference source circuit module includes an active load for generating the reference voltage V ref

[0046] Further, the core reference source circuit module includes: a first low-threshold PMOS transistor M1, a second low-threshold PMOS transistor M2, a first low-threshold NMOS transistor M3, a first high-threshold NMOS transistor M4, a second low-threshold NMOS transistor M5, a third low-threshold NMOS transistor M6, a fourth low-threshold NMOS transistor M7, and a third low-threshold PMOS transistor M8

[0047] Further, the startup circuit module includes a fifth low-threshold NMOS transistor M9, a fourth low-threshold PMOS transistor M10, a fifth low-threshold PMOS transistor M11, a sixth low-threshold PMOS transistor M12, a seventh low-threshold PMOS transistor M13, and a fifth low-threshold NMOS transistor M14; wherein the first high-threshold NMOS transistor M4 and the second low-threshold NMOS transistor M5 form an active load

[0048] ​Among them, the power supply voltage VDD is respectively input to the source of the first low-threshold PMOS transistor M1, the source of the second low-threshold PMOS transistor M2, the source of the third low-threshold PMOS transistor M8, and the source of the seventh low-threshold PMOS transistor M13.

[0049] Further, the gate of the first low-threshold PMOS transistor M1 is respectively connected to the gates of the second low-threshold PMOS transistor M2 and the third low-threshold PMOS transistor M8 through the drain of the fifth low-threshold NMOS transistor M14. The drain of the first low-threshold PMOS transistor M1 is respectively connected to the drain and gate of the first low-threshold NMOS transistor M3, the gate of the first high-threshold NMOS transistor M4, and the gate of the second low-threshold NMOS transistor M5. The source of the first high-threshold NMOS transistor M4 is grounded. Among them, the source of the first low-threshold NMOS transistor M3 and the drain of the first high-threshold NMOS transistor M4 are connected to the reference voltage terminal for generating the reference voltage V ref .

[0050] Further, the drain of the second low-threshold PMOS transistor M2 is respectively connected to the drain of the fifth low-threshold NMOS transistor M14 and the drain of the second low-threshold NMOS transistor M5. The source of the second low-threshold NMOS transistor M5 is connected to the drain of the third low-threshold NMOS transistor M6, and the gate of the third low-threshold NMOS transistor M6 is connected to the reference voltage terminal.

[0051] Further, the drain of the third low-threshold PMOS transistor M8 is respectively connected to the source of the third low-threshold NMOS transistor M6, the gate and drain of the fourth low-threshold NMOS transistor M7. The source of the fourth low-threshold NMOS transistor M7 is grounded. The third low-threshold PMOS transistor M8 and the fourth low-threshold NMOS transistor M7 are used to optimize the linear sensitivity.

[0052] Further, the gate and drain of the seventh low-threshold PMOS transistor M13 are both connected to the source of the sixth low-threshold PMOS transistor M12. The gate and drain of the sixth low-threshold PMOS transistor M12 are both connected to the source of the fifth low-threshold PMOS transistor M11. The gate and drain of the fifth low-threshold PMOS transistor M11 are both connected to the source of the fourth low-threshold PMOS transistor M10.

[0053] Further, the reference voltage terminal is respectively connected to the gate of the fourth low-threshold PMOS transistor M10 and the gate of the fifth low-threshold NMOS transistor M9. The drain of the fourth low-threshold PMOS transistor M10 and the drain of the fifth low-threshold NMOS transistor M9 are both connected to the gate of the fifth low-threshold NMOS transistor M14. The fourth low-threshold PMOS transistor M10 and the fifth low-threshold NMOS transistor M9 are used to output a relatively high voltage to the fifth low-threshold NMOS transistor M14 to turn it on. Among them, the source of the fifth low-threshold NMOS transistor M14 is grounded, and the source of the fifth low-threshold NMOS transistor M9 is grounded.

[0054] Further, the first high-threshold NMOS transistor M4 is a 5V transistor with a high threshold, and all the other MOS transistors are 1.8V transistors with a low threshold. All the transistors operate in the subthreshold region.

[0055] In a specific embodiment, the present invention can operate under the conditions of a power supply voltage of 0.65V to 1.8V and a temperature range of 0°C to 100°C, and the output voltage is about 350mV.

[0056] Further, the second low-threshold NMOS transistor M5 and the third low-threshold NMOS transistor M6 are current source transistors. The gate voltages of the second low-threshold NMOS transistor M5 and the third low-threshold NMOS transistor M6 are directly provided by the active load first high-threshold NMOS transistor M4 and the second low-threshold NMOS transistor M5, without an additional biasing structure.

[0057] Among them, the first low-threshold PMOS transistor M1 and the second low-threshold PMOS transistor M2 form a current mirror. The second low-threshold PMOS transistor M2 copies the bias current generated by the current source transistors, the second low-threshold NMOS transistor M5 and the third low-threshold NMOS transistor M6, to the first low-threshold PMOS transistor M1, and the first low-threshold PMOS transistor M1 injects the current into the active load first high-threshold NMOS transistor M4 and the second low-threshold NMOS transistor M5.

[0058] Further, when all the transistors of the core reference source circuit module are in the subthreshold region operating state, the mathematical expression form of the subthreshold current is:

[0059]

[0060] Among them, i = 1, 2, 3,... represents the number of the MOS transistors, μ is the mobility, C ox is the gate oxide capacitance, m is the subthreshold slope, is the thermal voltage, is the aspect ratio of each transistor.

[0061] Further, the reference voltage V ref is the difference between the gate-source voltage V GS3 of the first low-threshold NMOS transistor M3 and the gate-source voltage V GS4 of the first high-threshold NMOS transistor M4, and its mathematical expression form is:

[0062]

[0063] Among them, ideally, the reference voltage should not change with the variation of the power supply voltage VDD. Since the gate-source voltage V GS3 of the first low-threshold NMOS transistor M3 has VT , thus having a positive temperature coefficient, the gate-source voltage V of the first high-threshold NMOS transistor M4 GS4 having a threshold voltage difference V TH4 -V TH3 , thus having a negative temperature coefficient; by changing the aspect ratio K3 of the first low-threshold NMOS transistor M3 and the aspect ratio K4 of the first high-threshold NMOS transistor M4, the positive temperature coefficient can be changed, and then by superimposing with the negative temperature coefficient, a reference voltage V independent of temperature is obtained ref .

[0064] Furthermore, the process of the startup circuit module enabling the circuit to power on quickly and work properly is as follows: the power supply voltage VDD gradually increases, and the reference voltage V ref is input to the gates of the fourth low-threshold PMOS transistor M10 and the fifth low-threshold NMOS transistor M9 with a lower initial value. The fourth low-threshold PMOS transistor M10 and the fifth low-threshold NMOS transistor M9 act as an inverter to output a higher voltage to the gate of the fifth low-threshold NMOS transistor M14, making it conduct. The drain of the fifth low-threshold NMOS transistor M14 is connected to point A, and point A is respectively connected to the gates of the first low-threshold PMOS transistor M1, the gates and drains of the second low-threshold PMOS transistor M2, the drain of the second low-threshold NMOS transistor M5, and the gate of the third low-threshold PMOS transistor M8, making the second low-threshold PMOS transistor M2 conduct; as the power supply voltage VDD gradually increases, the reference voltage V ref is lifted to the normal output value, and the fourth low-threshold PMOS transistor M10 and the fifth low-threshold NMOS transistor M9 turn off the fifth low-threshold NMOS transistor M14, stopping the operation of the startup circuit module and completing the startup step.

[0065] Furthermore, the output of the reference voltage V ref is related to the current flowing through the first low-threshold NMOS transistor M3 and the first high-threshold NMOS transistor M4. When the current flowing through the first low-threshold NMOS transistor M3 and the first high-threshold NMOS transistor M4 fluctuates with the fluctuation of the power supply voltage VDD, V ref will also fluctuate. The reference voltage V ref obtained according to the difference between the subthreshold slope m3 of the first low-threshold NMOS transistor M3 and the subthreshold slope m4 of the first high-threshold NMOS transistor M4 is:

[0066]

[0067]

[0068] where, where I loadis the current flowing through the first low-threshold NMOS transistor M3 and the first high-threshold NMOS transistor M4. By stacking the second low-threshold NMOS transistor M5 on the third low-threshold NMOS transistor M6, the disturbance caused by the power supply voltage VDD to the drain-source voltage V of the third low-threshold NMOS transistor M6 can be reduced, so as to obtain a relatively stable bias current I DS6 . BIAS

[0069] Furthermore, the relatively stable bias current I BIAS will fluctuate due to the DIBL effect of the first low-threshold PMOS transistor M1 after being copied to the first low-threshold PMOS transistor M1. By using the method of the fourth low-threshold NMOS transistor M7 and the third low-threshold PMOS transistor M8 to reverse the DIBL effect, the DIBL effect of the first low-threshold PMOS transistor M1 can be effectively weakened, thereby weakening the change of I load and achieving the purpose of optimizing the linear sensitivity. load

[0070] Furthermore, the process of optimizing the linear sensitivity is specifically as follows: when the power supply voltage VDD changes by Δvdd, the current fluctuation ΔI1 caused by the change of the drain-source voltage V of the first low-threshold PMOS transistor M1 is in the same direction as the change of Δvdd, while the current fluctuation ΔI2 caused by the change of the gate-source voltage V of the first low-threshold PMOS transistor M1 is in the opposite direction to the change of Δvdd. Through the fourth low-threshold NMOS transistor M7 and the third low-threshold PMOS transistor M8, the gate-source voltage V of the first low-threshold PMOS transistor M1 can be made to change in the opposite direction to the power supply voltage VDD, so that after ΔI1 and ΔI2 are superimposed, the change of I DS1 is weakened, achieving the purpose of optimizing the sensitivity. GS1 GS1 load

[0071] Furthermore, the functions of the fourth low-threshold NMOS transistor M7 and the third low-threshold PMOS transistor M8 are specifically as follows: the gate and drain of the fourth low-threshold NMOS transistor M7 are short-circuited to form a diode connection type, which is used to convert current into voltage. When the power supply voltage VDD rises, the current flowing through the third low-threshold PMOS transistor M8 increases sharply, causing the gate-source voltage V of the four low-threshold NMOS transistor M7 to rise rapidly. When the rising speed of V GS7 is greater than the rising speed of the reference voltage V GS7 , the drain-source voltage V of the third low-threshold NMOS transistor M6 will keep decreasing, resulting in the gate-source voltage V of the second low-threshold PMOS transistor M2 ref , that is, the gate-source voltage V of the first low-threshold PMOS transistor M1 DS6 GS2 GS1 ​​​​​​​Decreases as the power supply voltage VDD increases, and the change caused by the power supply voltage VDD fluctuation is weakened through compensation. load The change caused by the fluctuation of the power supply voltage VDD.

[0072] Embodiment 2

[0073] Based on the above Embodiment 1, combined with Figure 2 , the principle of optimizing the linear sensitivity is elaborated in detail in this embodiment.

[0074] In a specific embodiment, as Figure 2 shown, the plus and minus signs in the figure represent the change direction of the variable, and R DS represents the equivalent impedance between the drain and source of the M1 transistor. ΔI1 represents the current fluctuation of the M1 transistor caused by the change of the gate-source voltage V GS1 , and ΔI2 represents the current fluctuation of the M1 transistor caused by the change of the drain-source voltage V DS1 . When the power supply voltage VDD changes by Δvdd, the change direction of ΔI2 is the same as that of Δvdd, while ΔI1 changes in the opposite direction compared with ΔI2. After the two are superimposed, ΔI load becomes smaller, and the current I load flowing through the M3 and M4 transistors is more stable.

[0075] To make ΔI1 change in the opposite direction compared with ΔI2, the V GS1 of M1 also needs to change in the opposite direction with VDD, which needs to be achieved by means of the transistors M7 and M8. The M8 transistor is a transistor with a short channel length, so its DIBL effect is very obvious. The gate and drain of the M7 transistor are short-circuited to form a diode connection type, which is used to convert current into voltage.

[0076] In a specific embodiment, when the power supply voltage VDD increases, the current of M8 increases sharply at this time, so that the gate-source voltage V GS7 of M7 rises rapidly. When its rising speed exceeds the reference voltage V ref , the drain-source voltage V DS6 of the current source transistor M6 will keep decreasing, so the current of the M6 transistor branch will also decrease and finally lead to the gate-source voltage V GS2 of the M2 transistor, that is, the gate-source voltage V GS1 of the M1 transistor will decrease as the power supply voltage VDD increases. The analysis method when VDD decreases is the same as above. This method reversely utilizes the DIBL effect of the M8 transistor to realize the reverse change of V GS1 with the power supply voltage VDD, compensates the current fluctuation caused by the change of V GS1 , and finally weakens the change of I load .

[0077] Embodiment 3

[0078] Based on the above-mentioned Embodiment 1 and Embodiment 2, combined with Figures 3 - 6 , in this embodiment, the changes of the currents and voltages of transistors M1 and M8 with the power supply voltage VDD during the process of optimizing the sensitivity are elaborated in detail.

[0079] In a specific embodiment, as Figure 3 and Figure 4 shown, after introducing transistor M8, the current I load is less sensitive to the power supply voltage VDD and has a smaller slope.

[0080] In a specific embodiment, as Figure 5 shown, the DIBL effect of transistor M8 is utilized in reverse, making the current I load of transistor M1 more stable, and the linear sensitivity of the reference is greatly reduced. It can be seen that the reference voltage V ref is almost not affected by the power supply voltage VDD. When VDD changes from 0.65V to 1.8V, the reference voltage only changes by 9.8μV, and the linear sensitivity is 0.002% / V.

[0081] In a specific embodiment, as Figure 6 shown, all transistors operate in the subthreshold region, the lowest operating voltage is 0.65V, and the power consumption at room temperature is only 530pW, realizing an ultra-low-power application.

[0082] The icons describing the structural position relationships in the drawings are only for illustrative purposes and should not be construed as limitations on this patent.

[0083] Obviously, the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not limitations on the implementation manners of the present invention. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. A pW-level CMOS voltage reference source with optimized linear sensitivity, characterized in that, It includes a startup circuit module and a core reference source circuit module. The startup circuit module is used to enable the reference source to get rid of the degeneracy point and enter the normal working state during startup. The core reference source circuit module includes an active load for generating a reference voltage V ref ; The core reference source circuit module includes: a first low-threshold PMOS transistor M1, a second low-threshold PMOS transistor M2, a first low-threshold NMOS transistor M3, a first high-threshold NMOS transistor M4, a second low-threshold NMOS transistor M5, a third low-threshold NMOS transistor M6, a fourth low-threshold NMOS transistor M7, and a third low-threshold PMOS transistor M8; The startup circuit module includes a fifth low-threshold NMOS transistor M9, a fourth low-threshold PMOS transistor M10, a fifth low-threshold PMOS transistor M11, a sixth low-threshold PMOS transistor M12, a seventh low-threshold PMOS transistor M13, and a fifth low-threshold NMOS transistor M14; wherein the first high-threshold NMOS transistor M4 and the second low-threshold NMOS transistor M5 form an active load; Among them, the power supply voltage VDD is respectively input to the source of the first low-threshold PMOS transistor M1, the source of the second low-threshold PMOS transistor M2, the source of the third low-threshold PMOS transistor M8, and the source of the seventh low-threshold PMOS transistor M13; The gate of the first low-threshold PMOS transistor M1 is respectively connected to the gates of the second low-threshold PMOS transistor M2 and the third low-threshold PMOS transistor M8 through the drain of the fifth low-threshold NMOS transistor M14. The drain of the first low-threshold PMOS transistor M1 is respectively connected to the drain and gate of the first low-threshold NMOS transistor M3, the gate of the first high-threshold NMOS transistor M4, and the gate of the second low-threshold NMOS transistor M5. The source of the first high-threshold NMOS transistor M4 is grounded; wherein the source of the first low-threshold NMOS transistor M3 and the drain of the first high-threshold NMOS transistor M4 are connected to the reference voltage terminal for generating the reference voltage V ref ; The drain of the second low-threshold PMOS transistor M2 is respectively connected to the drain of the fifth low-threshold NMOS transistor M14 and the drain of the second low-threshold NMOS transistor M5; the source of the second low-threshold NMOS transistor M5 is connected to the drain of the third low-threshold NMOS transistor M6, and the gate of the third low-threshold NMOS transistor M6 is connected to the reference voltage terminal; The drain of the third low-threshold PMOS transistor M8 is respectively connected to the source of the third low-threshold NMOS transistor M6, the gate and drain of the fourth low-threshold NMOS transistor M7, and the source of the fourth low-threshold NMOS transistor M7 is grounded. The third low-threshold PMOS transistor M8 and the fourth low-threshold NMOS transistor M7 are used to optimize the linear sensitivity; The gate and drain of the seventh low-threshold PMOS transistor M13 are both connected to the source of the sixth low-threshold PMOS transistor M12, the gate and drain of the sixth low-threshold PMOS transistor M12 are both connected to the source of the fifth low-threshold PMOS transistor M11, and the gate and drain of the fifth low-threshold PMOS transistor M11 are both connected to the source of the fourth low-threshold PMOS transistor M10; The reference voltage terminal is respectively connected to the gate of the fourth low-threshold PMOS transistor M10 and the gate of the fifth low-threshold NMOS transistor M9. The drain of the fourth low-threshold PMOS transistor M10 and the drain of the fifth low-threshold NMOS transistor M9 are both connected to the gate of the fifth low-threshold NMOS transistor M14. The fourth low-threshold PMOS transistor M10 and the fifth low-threshold NMOS transistor M9 are used to output a relatively high voltage to the fifth low-threshold NMOS transistor M14 to turn it on; wherein the source of the fifth low-threshold NMOS transistor M14 is grounded, and the source of the fifth low-threshold NMOS transistor M9 is grounded.

2. A pW-level CMOS voltage reference source with optimized linear sensitivity according to claim 1, characterized in that The first high-threshold NMOS transistor M4 is a high-threshold 5V transistor, and all the other MOS transistors are low-threshold 1.8V transistors. All the transistors operate in the subthreshold region.

3. A pW-level CMOS voltage reference source with optimized linear sensitivity according to claim 1, characterized in that, The second low-threshold NMOS transistor M5 and the third low-threshold NMOS transistor M6 are current source transistors, and the gate voltages of the second low-threshold NMOS transistor M5 and the third low-threshold NMOS transistor M6 are directly provided by the active load first high-threshold NMOS transistor M4 and the second low-threshold NMOS transistor M5 without an additional biasing structure; The first low-threshold PMOS transistor M1 and the second low-threshold PMOS transistor M2 form a current mirror. Among them, the second low-threshold PMOS transistor M2 copies the bias current generated by the current source transistors, the second low-threshold NMOS transistor M5 and the third low-threshold NMOS transistor M6, to the first low-threshold PMOS transistor M1, and the first low-threshold PMOS transistor M1 injects current into the active load first high-threshold NMOS transistor M4 and the second low-threshold NMOS transistor M5.

4. A pW-level CMOS voltage reference source with optimized linear sensitivity according to claim 3, characterized in that, When all the transistors of the core reference source circuit module are operating in the subthreshold region, the mathematical expression of the subthreshold current is: Among them, i = 1, 2, 3,... represents the number of MOS transistors, V GS represents the gate-source voltage of the transistor, V THi represents the threshold voltage of the i-th transistor, μ n is the mobility, C ox is the gate oxide capacitance, m i is the subthreshold slope of the i-th transistor, V T is the thermal voltage, is the width-to-length ratio of the i-th transistor.

5. A pW-level CMOS voltage reference source with optimized linear sensitivity according to claim 4, characterized in that The reference voltage V ref is the difference between the gate-source voltage V GS3 of the first low-threshold NMOS transistor M3 and the gate-source voltage V GS4 of the first high-threshold NMOS transistor M4, and its mathematical expression is: Among them, ideally, the reference voltage should not change with the variation of the power supply voltage VDD. Since the gate-source voltage V of the first low-threshold NMOS transistor M3 GS3 with V T , so it has a positive temperature coefficient. The gate-source voltage V of the first high-threshold NMOS transistor M4 GS4 has a threshold voltage difference V TH4 -V TH3 , so it has a negative temperature coefficient; m represents the subthreshold slope; by changing the aspect ratio K3 of the first low-threshold NMOS transistor M3 and the aspect ratio K4 of the first high-threshold NMOS transistor M4, the positive temperature coefficient can be changed, and then by superimposing with the negative temperature coefficient, a reference voltage V independent of temperature can be obtained ref .

6. A pW-level CMOS voltage reference source with optimized linear sensitivity according to claim 1, characterized in that, The process of the startup circuit module enabling the circuit to power up quickly and operate normally is specifically as follows: The power supply voltage VDD gradually increases, and the reference voltage V ref is input to the gates of the fourth low-threshold PMOS transistor M10 and the fifth low-threshold NMOS transistor M9 with a lower initial value. The fourth low-threshold PMOS transistor M10 and the fifth low-threshold NMOS transistor M9 act as an inverter to output a higher voltage to the gate of the fifth low-threshold NMOS transistor M14, causing it to conduct. The drain of the fifth low-threshold NMOS transistor M14 is connected to point A, and point A is respectively connected to the gates of the first low-threshold PMOS transistor M1, the second low-threshold PMOS transistor M2's gate and drain, the drain of the second low-threshold NMOS transistor M5, and the gate of the third low-threshold PMOS transistor M8, causing the second low-threshold PMOS transistor M2 to conduct. As the power supply voltage VDD gradually increases, the reference voltage V ref is lifted to the normal output value, and the fourth low-threshold PMOS transistor M10 and the fifth low-threshold NMOS transistor M9 turn off the fifth low-threshold NMOS transistor M14, causing the startup circuit module to stop working and completing the startup step.

7. A pW-level CMOS voltage reference source with optimized linear sensitivity according to claim 6, characterized in that Relatively stable bias current I BIAS The I obtained after being copied to the first low-threshold PMOS transistor M1 load will fluctuate due to the DIBL effect of the first low-threshold PMOS transistor M1. The method of using the fourth low-threshold NMOS transistor M7 and the third low-threshold PMOS transistor M8 to reverse the DIBL effect can effectively weaken the DIBL effect of the first low-threshold PMOS transistor M1, thereby weakening the change of I load and achieving the purpose of optimizing the linear sensitivity.

8. A pW-level CMOS voltage reference source with optimized linear sensitivity according to claim 7, characterized in that The specific process of optimizing the linear sensitivity is as follows: when the power supply voltage VDD changes by Δvdd, the drain-source voltage V of the first low-threshold PMOS transistor M1 GS1 The current fluctuation ΔI1 caused by the change is in the same direction as the change of Δvdd, while the gate-source voltage V of the first low-threshold PMOS transistor M1 DS1 The current fluctuation ΔI2 caused by the change is in the opposite direction to the change of Δvdd. Through the fourth low-threshold NMOS transistor M7 and the third low-threshold PMOS transistor M8, the gate-source voltage V of the first low-threshold PMOS transistor M1 GS1 Changes in the opposite direction to the power supply voltage VDD, so that after the superposition of ΔI1 and ΔI2, the change of I load is weakened, achieving the purpose of optimizing the sensitivity.

9. A pW-level CMOS voltage reference source with optimized linear sensitivity according to claim 8, characterized in that, The functions of the fourth low-threshold NMOS transistor M7 and the third low-threshold PMOS transistor M8 are as follows: The gate and drain of the fourth low-threshold NMOS transistor M7 are short-circuited to form a diode connection type, which is used to convert current into voltage. When the power supply voltage VDD increases, the current flowing through the third low-threshold PMOS transistor M8 increases sharply, causing the gate-source voltage V of the four low-threshold NMOS transistor M7 GS7 to rise rapidly. When the rising speed of V GS7 is greater than the rising speed of the reference voltage V ref , the drain-source voltage V of the third low-threshold NMOS transistor M6 DS6 will keep decreasing, resulting in the gate-source voltage V of the second low-threshold PMOS transistor M2 GS2 , that is, the gate-source voltage V of the first low-threshold PMOS transistor M1 GS1 decreases as the power supply voltage VDD increases. Through the compensation effect, the change caused by the fluctuation of I load with the power supply voltage VDD is weakened.

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