A voltage noise smoothing system for MCM-GPU

Abstract

A voltage noise smoothing system for MCM-GPUs includes two major parts: a detector and an actuator. The detector detects the SMs within all GPMs, but only determines whether a single GPM is about to experience a voltage drop. The actuator postpones execution of all SMs, which not only smooths the first GPM that experiences voltage noise, but also prevents voltage noise from occurring in other GPMs in the future. The detector of the present invention uses a communication channel within the SM, which has no additional overhead and a low performance burden. The technology fits the characteristics of the MCM architecture and uses GPM perception to smooth voltage noise based on the time differences between different GPMs. The detection window and range can detect most voltage noise, while reserving time for the execution window to execute, so that serious voltage noise will not occur during detection.

Description

Technical Field

[0001] The present invention belongs to the technical field of smoothing voltage noise, and in particular relates to a GPU voltage noise smoothing technology for an MCM architecture. Technical Background

[0002] The performance of graphics processing unit chips is positively correlated with the number of transistors, which is determined by the chip's area and process technology. However, due to recent limitations in optical performance and production yields, the number of transistors per chip has slowed significantly, leading to the gradual breakdown of Moore's Law. The growth rate of chip area and transistor count is steadily decreasing. However, in many fields such as high-performance computing, cloud computing, and deep learning, there remains a huge demand for higher chip performance. Therefore, MCM (Multi-Chip-in-One Package) technology has gradually become a new and effective way to significantly improve chip performance.

[0003] An MCM chip contains multiple GPMs (graphics processing modules), roughly the size of a conventional packaged chip. These chip modules are integrated into a single package, doubling the chip's overall performance. However, this also results in significantly increased power consumption and challenges to power supply stability.

[0004] Voltage noise occurs when the actual voltage of a chip is lower than the supply voltage during operation. Large voltage fluctuations can cause programs to crash and fail to run. Therefore, current processor PDN (power supply network) voltage designs include a significant protection band to mitigate the effects of voltage noise. However, the maximum voltage drop occurs only rarely during program execution, contributing significantly to energy consumption. Voltage noise is primarily caused by two factors. One is due to the parasitic resistance of the power supply network, which is dependent solely on hardware parameters and difficult to smooth out. The other is related to the rate of change of current during program execution. This can be achieved by optimizing program execution to stabilize the current and, in turn, the voltage.

[0005] When a processor experiences rapid current changes within a short period of time while running a program, the parasitic inductance of the power transmission system itself can cause voltage ripple in the chip's power supply lines. If this voltage rises or falls within a large range, it can cause program failures. This is known as the dI / dt (dI / dt) problem. The dI / dt voltage drop is determined by the slope of the current curve, or the rate of increase of the current. The voltage after the dI / dt drop can be calculated as:

[0006] V=Vdd–L×dI / dt (1)

[0007] Wherein, Vdd is the power supply voltage of the processor, L is the parasitic inductance of the power supply system, and dI / dt is the current change rate of the processor.

[0008] Because MCM-based GPUs are significantly larger than traditional GPUs, stable voltage supply poses a greater challenge. Therefore, it is essential to smooth voltage noise based on the characteristics of the MCM architecture. This not only ensures stable program execution but also reduces the voltage protection band to improve energy efficiency.

[0009] Currently, there is no research or technology to mitigate voltage noise in MCM-based GPUs. Research on voltage noise mitigation in single-GPU architectures, similar to this technology, also involves a detector and an executor. The detector detects the number of warps across all SMs. Voltage noise is detected when the number of warps increases in more than half of the SMs within the entire GPU. This works well in a single GPU. However, due to the large scale of the MCM architecture and the high latency between GPMs, this approach is less effective in MCM-based GPUs. Regarding the executor, the duration of voltage noise also varies due to differences in GPU size. Voltage noise in MCM-based GPUs persists for a longer period, making single-GPU technology unable to continuously smooth out a complete period of voltage noise. Summary of the Invention

[0010] In response to the above technical problems, the present invention aims to provide a GPU voltage noise smoothing system for an MCM architecture, which can effectively smooth the voltage noise occurring in the MCM-GPU.

[0011] To achieve the above-mentioned object, the present invention provides a voltage noise smoothing system for MCM-GPU, comprising two parts: a detector and an actuator, wherein the detector includes:

[0012] a first storage device for storing a WARP status flag of each SM within 50 cycles;

[0013] a second storage device for storing the number of SMs whose WARP status flags change in each GPM within 50 cycles;

[0014] The actuators include:

[0015] a third storage device for storing a flag bit of a signal for triggering a smoothing mechanism;

[0016] a fourth storage device for storing a start cycle of SM execution;

[0017] The detector is characterized in that it also includes:

[0018] a first comparator for comparing the WARP status flag of the previous cycle SM with the WARP status flag of the current cycle SM;

[0019] a WARP state flag changing device controlled by a first comparator;

[0020] An SM quantity changing device controlled by a WARP status flag changing device.

[0021] The actuator also includes:

[0022] a second comparator for comparing the number of SMs stored in the second storage device with half the number of SMs in the GPM;

[0023] a trigger smoothing mechanism signal flag bit conversion device controlled by a second comparator;

[0024] A means for controlling the SM execution start cycle change of the third storage means.

[0025] Furthermore, the WARP status flag changing device is a device that changes the WARP status flag stored in the first storage device from 0 to 1 and a device that does not change the WARP status flag.

[0026] Furthermore, the SM number changing means includes: means for adding 1 to the SM number stored in the second storage means and means for keeping the SM number unchanged.

[0027] Furthermore, the trigger smoothing mechanism signal flag bit conversion device includes: trigger smoothing mechanism signal flag bit 1 and trigger smoothing mechanism signal flag bit 0 stored in the third storage device.

[0028] Furthermore, the SM execution start period changing means includes: means for increasing the SM execution start period stored in the fourth storage means by 50 and means for not changing the SM execution start period.

[0029] The detector of the present invention runs during the GPU's scheduling phase, which assigns threads to each streaming multiprocessor (SM). During each program cycle, the detector records changes in the number of warps for each SM. If, within a detection window (50 cycles), it receives a flag change from 0 to 1 from more than half of the SMs within a GPM, the detector predicts a voltage drop and triggers the execution of the executor. The executor runs during the GPU's execution phase, which is the process by which the SM begins executing the threads assigned during the scheduling phase. Upon receiving the detector's prediction of an impending voltage drop, the executor begins staggered execution of all SMs, deferring each SM's execution by 50 cycles. Delaying SM execution prevents simultaneous rapid current fluctuations across the entire GPU, thereby stabilizing voltage and smoothing voltage noise. 50 cycles is sufficient to avoid the most severe voltage drops. Furthermore, the detector uses internal SM communication channels, eliminating overhead and minimizing performance burden. This technology aligns with the characteristics of the MCM architecture, leveraging GPM awareness to mitigate voltage noise based on the timing differences between different GPMs. The detection window and range can detect most voltage noise, while reserving time for the execution window, so that serious voltage noise will not occur during detection, which can effectively improve the detection accuracy of voltage noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a block diagram of the system composition of the present invention;

[0031] Figure 2 It is a flowchart of the system work flow of the present invention;

[0032] Figure 3 The following is a comparison of the voltage noise amplitude when running the relevant test program before and after using this technology. DETAILED DESCRIPTION

[0033] Reference Figure 1 The present invention is divided into two parts: a detector and an actuator. The detector includes:

[0034] a first storage device 3 for storing a WARP status flag of each SM within 50 cycles;

[0035] a second storage device 5 for storing the number of SMs whose WARP status flags change in each GPM within 50 cycles;

[0036] a first comparator 1 for comparing the WARP status flag of the previous cycle SM with the WARP status flag of the current cycle SM;

[0037] a WARP state flag changing device 2 controlled by a first comparator;

[0038] An SM quantity changing device 4 controlled by the WARP state flag changing device.

[0039] The first comparator 1 compares the WARP status flag of the previous cycle SM with the WARP status flag of the current cycle SM, and controls the WARP status flag conversion device 2. When the WARP number in the SM changes from 0 in a certain cycle to 1 in the next cycle or remains unchanged, the WARP status flag conversion device 2 changes the WARP status flag stored in the first storage device 3 from 0 to 1 or does not change it, and controls the SM number changing device 4 to add 1 to the SM number stored in the second storage device 5 or keep it unchanged.

[0040] The actuators include:

[0041] A third storage device 6 for storing a flag bit of a signal for triggering a smoothing mechanism;

[0042] a fourth storage device 10 for storing a start cycle of SM execution;

[0043] a second comparator 8 which compares the number of SMs stored in the second storage device 5 with half the number of SMs in the GPM;

[0044] A trigger smoothing mechanism signal flag conversion device 7 controlled by a second comparator 8;

[0045] An SM execution cycle changing device 9 for controlling the third storage device 6.

[0046] Second comparator 8 compares the number of SMs in second storage device 5 with half the number of SMs in the GPM, and controls trigger smoothing mechanism signal flag conversion device 7. When the number of SMs in first storage device 3 is greater than, equal to, or less than half the number of SMs in the GPM, trigger smoothing mechanism signal flag conversion device 7 sets the trigger smoothing mechanism signal flag stored in third storage device 6 to 1 or 0. Third storage device 6 is used to store the trigger smoothing mechanism signal flag, and controls SM execution period change device 9 to increase or decrease the start period of SM execution stored in fourth storage device 10 by 50.

[0047] Reference Figure 2 The detector runs during the GPU's scheduling phase, which assigns threads to each streaming multiprocessor (SM). During each program cycle, the detector records changes in the number of warps on each SM. If, within a 50-cycle detection window, the detector receives a flag change from 0 to 1 from more than half of the SMs within a given GPM, it predicts a voltage drop and triggers the execution of the actuator.

[0048] The executor runs in the execution phase of the GPU, which is the process in which the SM begins to execute the threads assigned in the scheduling phase. After receiving the signal from the detector predicting that a voltage drop will occur, the executor begins to interleave and limit the execution of all SMs, delaying the execution of each SM by 50 cycles. Delaying the execution of the SM will prevent the entire GPU from experiencing rapid current changes at the same time, thereby stabilizing the voltage and smoothing out the voltage noise, and 50 cycles are enough to avoid the most severe voltage drops. Therefore, this application narrows the detection range to the GPM level, and at the same time takes into account the existence of delays between GPMs, increases the detection time window, and can effectively improve the detection accuracy of voltage noise.

[0049] Working principle: The principle of the detector is to detect the number of WARPs in each cycle for each SM (streaming multiprocessor) in the MCM-GPU. Because when the number of WARPs in the SM increases from 0, the current will rise rapidly. Combined with the voltage noise, the rapid change of current will cause the appearance of voltage noise. When this change occurs simultaneously in most SMs of the entire processor, the entire processor will have large-scale voltage noise. In addition, due to the delay between different GPMs (GPU modules) in the MCM-GPU (for example, after one GPM starts to generate voltage noise, other GPMs will start to generate voltage noise after a period of time), this technology predicts the occurrence of large-scale voltage noise by detecting the change in the number of WARPs of each SM in the cycle (50). When more than half of the SMs in a GPM have a change in the number of WARPs from 0 to 1, it can be considered that large-scale voltage noise is about to occur.

[0050] The principle of the actuator is to postpone the execution of the SM (50 cycles) when it detects the possibility of large-scale voltage noise. By delaying the execution of the SM, the current rise rate caused by the increase in WARP is slowed down. By stabilizing the current change rate, the voltage noise amplitude can be reduced according to formula (1).

[0051] Reference Figure 3 ,Comparison of the voltage noise amplitude (i.e. the maximum voltage drop ratio during program operation) when running the relevant test program before and after using this technology:

[0052] The experiment uses Accel-sim (a GPU simulator) to simulate the operation of MCM-GPU with the following configuration:

[0053] GPMs数量 4 SM总数 96 DRAM数量 12 GPU频率 1905MHz 标称电源电压 1V Warp调度器 贪婪优先,然后是最旧的 GPM间带宽 1.5TB / s GPM间延迟 56ns 片外能量 0.54pJ / bit

[0054] According to the experimental results, the voltage noise during the running of all test programs was smoothed, with the highest reduction of 38% and an average of around 29%, proving that this technology can effectively smooth the voltage noise appearing in MCM-GPUs.

Claims

1. A voltage noise smoothing system for MCM-GPU, comprising a detector and an actuator, wherein: Detectors include: a first storage device for storing a WARP status flag of each SM within 50 cycles; a second storage device for storing the number of SMs whose WARP status flags change in each GPM within 50 cycles; The actuators include: a third storage device for storing a flag bit of a signal for triggering a smoothing mechanism; a fourth storage device for storing a start cycle of SM execution; The detector is characterized in that it also includes: a first comparator for comparing the WARP status flag of the previous cycle SM with the WARP status flag of the current cycle SM; a WARP state flag changing device controlled by a first comparator; an SM quantity changing device controlled by a WARP state flag changing device; The actuator also includes: a second comparator for comparing the number of SMs stored in the second storage device with half the number of SMs in the GPM; a trigger smoothing mechanism signal flag bit conversion device controlled by a second comparator; A means for controlling the SM execution start cycle change of the third storage means.

2. The voltage noise smoothing system for MCM-GPU according to claim 1, characterized in that: The WARP status flag changing means is a means for changing the WARP status flag stored in the first storage means from 0 to 1 and a means for not changing the WARP status flag.

3. The voltage noise smoothing system for MCM-GPU according to claim 1, characterized in that: The SM number changing device includes: a device for adding 1 to the SM number stored in the second storage device and a device for keeping the SM number unchanged.

4. The voltage noise smoothing system for MCM-GPU according to claim 1, characterized in that: The triggering smooth mechanism signal flag bit conversion device includes: triggering the smooth mechanism signal flag bit 1 and triggering the smooth mechanism signal flag bit 0 stored in the third storage device.

5. The voltage noise smoothing system for MCM-GPU according to claim 1, characterized in that: The SM execution cycle changing device includes: a device for increasing the SM execution start cycle stored in the fourth storage device by 50 and a device for not changing the SM execution start cycle.

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