Circuit modules with reliable tolerance settings

Abstract

A circuit module with reliable tolerance settings includes a main circuit, a first auxiliary circuit, and a second auxiliary circuit. When the first auxiliary circuit is turned on, the second auxiliary circuit is turned on or off based on a control signal at a first level or a second level. When both the first and second auxiliary circuits are turned on, the first and second auxiliary circuits jointly set an operating parameter of the main circuit to a first value. When the first auxiliary circuit is turned on and the second auxiliary circuit is turned off, the first auxiliary circuit sets the operating parameter to a second value. An operating tolerance of the main circuit covers a range between the first and second values.

Description

Technical Field

[0001] The present invention relates to a circuit module with a reliable margin configuration, and more particularly to a circuit module, such as a memory module, comprising a main circuit, a first auxiliary circuit, and a second auxiliary circuit. When the first auxiliary circuit is turned on, the second auxiliary circuit is turned on or off according to a control signal, so that an operating parameter of the main circuit is at a first value or a second value. Furthermore, an operating margin of the main circuit covers a range between the first value and the second value, allowing the main circuit to switch between different operating conditions without interrupting ongoing operation. Background Art

[0002] Various circuit modules, such as silicon intellectual property (SIP) and memory modules, are essential building blocks of integrated circuits. To balance power consumption and performance, modern circuit modules must be able to switch between different operating modes, such as a high-performance mode with a high clock and high voltage, and a low-power mode with a low clock and low voltage. In different modes, the various operating parameters of the circuit modules also have different values. For example, at different clock frequencies in different modes, the access timing parameters of the memory module are also different; at different supply voltages in different modes, the voltage parameters applied to the word lines and / or bit lines of the memory module are also different.

[0003] To support different modes, conventional circuit modules configure dedicated circuits for different modes, such as a first-mode-specific circuit for the first mode and a second-mode-specific circuit for the second mode. When the conventional circuit module operates in the first mode, the first-mode-specific circuit is turned on, while the second-mode-specific circuit is turned off. When operating in the second mode, the first-mode-specific circuit is turned off, and the second-mode-specific circuit is turned on instead. In the prior art, the first-mode-specific circuit sets an operating parameter to a first value, while the second-mode-specific circuit sets the operating parameter to a different second value. Thus, the operating parameter will be the first value in the first mode (because only the first-mode-specific circuit is turned on), and the second value in the second mode (because only the second-mode-specific circuit is turned on).

[0004] However, this prior art has many drawbacks. For example, a mode handover period is required to fully switch from the first mode to the second mode (or vice versa). During this mode handover period, whether the circuits dedicated to the first mode and the circuits dedicated to the second mode are turned on or off is unpredictable and has a random component. Ideally, one is turned on and the other is turned off, but there may be a period of time when both are turned on, both are turned off, or the one that should be turned on is not turned on and the one that should be turned off is not turned off, and so on. The uncertainty during the mode handover period makes it difficult to determine the operating parameters of the circuit module. For example, if the circuits dedicated to the first and second modes are both turned on, it is difficult to determine whether the operating parameter is the first value, the second value, or another value.

[0005] Furthermore, each mode-specific circuit requires a transient period to transition from on to fully off, or from off to fully on. During the mode transition period, even if the two mode-specific circuits correctly switch from on to off and back on, the transient period between the two mode-specific circuits can still have unpredictable effects on the overall operation of the circuit module. For example, when a conventional circuit module switches from a first mode to a second mode, the operating parameter ideally should be set to the second value. However, if the first mode-specific circuit is not fully off when the second mode-specific circuit is turned on, the operating parameter will deviate from the second value, but will not be the first value.

[0006] To avoid the uncertainties caused by mode handovers and transients, conventional technology interrupts normal circuit module operation during mode switching, resuming operation only after the mode switch is complete. For example, conventional memory modules perform a mode handover after an access (read or write) cycle has completed, and do not perform any access operations during the mode handover period. The next access cycle will only begin after the circuits specific to each mode have been correctly enabled and disabled. Because normal circuit module operation must be interrupted during mode switching, this conventional technology reduces the circuit module's operating performance. Summary of the Invention

[0007] One of the purposes of the present invention is to provide a circuit module (e.g., 100, 101) with a reliable margin setting so as to switch between different operating conditions without interrupting the ongoing operation. Figure 1 The circuit module may include a main circuit (eg 110, Figure 1 ), a first auxiliary circuit (eg Figure 3a 、 4a or 121, y1[p] or x1[k] in 5a) and a second auxiliary circuit (e.g. Figure 3a 、 4a or 122, y2[p] or x2[k] in 5a). The main circuit may include a first node (e.g. Figure 3a 、 4aor n1, al[p], or b1[k] in 5a). The first auxiliary circuit is coupled to the first node, and the second auxiliary circuit is coupled to the first node and a control signal (eg Figure 3a dvs_sa_relax in or Figure 4a 、 5a When the first auxiliary circuit is turned on, the second auxiliary circuit is at a first level or a second level (e.g., v0, v1, Figure 2 ) and turned on or off. When the first auxiliary circuit and the second auxiliary circuit are both turned on, the first auxiliary circuit and the second auxiliary circuit work together to make an operating parameter of the main circuit a first value (for example Figure 3b 、 4b When the first auxiliary circuit is turned on and the second auxiliary circuit is turned off, the first auxiliary circuit sets the operating parameter to a second value (e.g., Figure 3b 、 4b or T32, T41 or v51 in 5b), the second value is different from the first value. An operation tolerance of the main circuit covers the range between the first value and the second value, so that: even if the control signal is in an operation cycle of the main circuit (for example Figure 3b 、 4b or Tp1, Tp2 or Tp3 in 5b), the main circuit still continues the normal operation in the operation cycle and does not affect the operation correctness in the operation cycle.

[0008] In one embodiment (for example Figure 2 ), when the supply voltage of the main circuit (e.g., VDD) is a first supply value (e.g., vdd1) and the period of a clock (e.g., CK) running the main circuit is a first cycle value (e.g., T1), the control signal is at the first level (e.g., v0). When the supply voltage of the main circuit is a second supply value (e.g., vdd2) and the period of the clock running the main circuit is a second cycle value (e.g., T2), the control signal is at the second level (e.g., v1). The first supply value and the second supply value are different, and the first cycle value and the second cycle value are different.

[0009] In one embodiment (for example Figure 1 ), the main circuit may include at least one storage unit (e.g. Figure 1 c[p,q] in the , at least one tracking cell (e.g. Figure 1 Tc[p] in) and at least one sense amplifier (e.g. Figure 1. The memory cell is coupled to a word line (e.g., WL[p]) and a bit line (e.g., BL[q]). The tracking memory cell is coupled to a tracking word line (e.g., TWL) and a tracking bit line (e.g., TBL). The sense amplifier is coupled to the bit line.

[0010] In one embodiment of the present invention (e.g. Figure 1 、 3a 3b), the first node (eg n1, Figure 3a ) is coupled to the tracking bit line. Figure 3a ) may include a first transistor (e.g., M1) and a third transistor (e.g., M3). The first transistor includes a first controlled terminal (e.g., a gate terminal) and two first channel terminals (e.g., a drain terminal and a source terminal); the two first channel terminals are respectively coupled to the first node (e.g., n1) and a third node (e.g., n3). The third transistor includes a third controlled terminal and two third channel terminals; the two third channel terminals are respectively coupled to the third node and a fourth node (e.g., n4), and one of the first controlled terminal and the third controlled terminal is coupled to the following word line. The second auxiliary circuit (e.g., 122, Figure 3a ) may include a second transistor (e.g., M2), a fourth transistor (e.g., M4), and an inverter (e.g., 124). The second transistor includes a second controlled terminal and two second channel terminals; the two second channel terminals are coupled to the first node and a second node (e.g., n2), respectively. The fourth transistor includes a fourth controlled terminal and two fourth channel terminals; the two fourth channel terminals are coupled to the second node and the fourth node, respectively. One of the second controlled terminal and the fourth controlled terminal is coupled to the control signal (e.g., dvs_sa_relax) (via the inverter), and the other is coupled to the following word line. In one embodiment, the operating parameter may be: after the following word line is driven (e.g., t30, Figure 3b ) The time it takes for the voltage of the tracking bit line to change to a second voltage value (e.g., v32). In one embodiment, the operating parameter may be: the time it takes for the voltage of the tracking bit line to change from a first voltage value (e.g., v31, Figure 3b ) changes to a second voltage value (eg, v32). In one embodiment, the operating margin is a timing margin of the sense amplifier.

[0011] In one embodiment of the present invention (e.g. Figure 1 、 4a 4b), the first node (eg a1[p], Figure 4a ) is coupled to the word line (eg, WL[p], Figure 4a), the first auxiliary circuit (e.g., y1[p]) includes a first transistor (e.g., H1[p]) and a third transistor (e.g., H3[p]), and the second auxiliary circuit (e.g., y2[p]) includes a second transistor (e.g., H2[p]) and an inverter (e.g., INV[p]). The first transistor includes two first channel terminals, respectively coupled to the first node and a second node (e.g., a2[p]). The third transistor includes two third channel terminals, respectively coupled to the second node and a third node (e.g., a3[p]). The second transistor (e.g., H2[p]) includes a second controlled terminal and two second channel terminals; the second controlled terminal is coupled to the control signal (e.g., dvs_rawa_assert) via the inverter, and the two second channel terminals are respectively coupled to the first node and the second node. In one embodiment, the operating parameter may be: the voltage of the bit line is changed by a third voltage value (e.g., v41, Figure 4b ) changes to a fourth voltage value (e.g., v42). In one embodiment, the operating parameter may be: the time it takes for the voltage of the bit line to change to a fourth voltage value (e.g., v42) after the word line is driven (e.g., t40). In one embodiment, after the word line is driven, if the control signal is the first level (e.g., v0, Figure 2 ), the voltage of the word line is a fifth voltage value (eg, vw42, Figure 4b ); If the control signal is the second level (eg v1, Figure 2 ), the voltage of the word line is a sixth voltage value (eg, vw41, Figure 4b ), and the fifth voltage value is different from the sixth voltage value. In one embodiment, the operating margin is a timing margin of the sense amplifier.

[0012] In one embodiment of the present invention (e.g. Figure 1 、 5a 5b), the main circuit further includes a write circuit (eg WB[k], Figure 1 and 5a ), coupled to the bit line and a negative voltage bit line (eg, NBL[k], Figure 5a ); the first node (eg b1[k], Figure 5a ) is coupled to the negative voltage bit line. The first auxiliary circuit (eg x1[k], Figure 5a) includes a first logic gate (e.g., g1[k]) and a first capacitor (e.g., C1[k]). The first logic gate includes a first input terminal (e.g., i1[k]) and a first output terminal (e.g., o1[k]), and the first capacitor is coupled between the first output terminal and the first node. The second auxiliary circuit (e.g., x2[k]) includes a second logic gate (e.g., g2[k]) and a second capacitor (e.g., C2[k]). The second logic gate includes two second input terminals (e.g., i21[k] and i22[k]) and a second output terminal (e.g., o2[k]), and the two second input terminals are respectively coupled to the first input terminal and the control signal (e.g., dvs_rawa_assert). The second capacitor is coupled between the second output terminal and the first node. In one embodiment, the first logic gate is an inverter, and the second logic gate is an NAND gate. In one embodiment, the operating parameter may be: after the word line is driven (e.g., t50, Figure 5b ) The voltage limit of the negative voltage bit line. In one embodiment, the operating margin is the negative voltage tolerance of the bit line.

[0013] In one embodiment of the present invention, the circuit module not only includes the first auxiliary circuit (eg 121, Figure 3a ) and a second auxiliary circuit (eg, 122, coupled to the control signal (eg, dvs_sa_relax) Figure 3a ), further comprising a third auxiliary circuit and a fourth auxiliary circuit (eg Figure 4a y1[p] and y2[p] in , or Figure 5a The third auxiliary circuit is coupled to a fourth node (eg Figure 4a a1[p] or Figure 5a b1[k]), the fourth auxiliary circuit couples the fourth node to a second control signal (e.g., dvs_rawa_assert). When the third auxiliary circuit is turned on, the fourth auxiliary circuit is a third level or a fourth level (e.g., v0, v1, etc.) according to the second control signal. Figure 2 When the third auxiliary circuit and the fourth auxiliary circuit are both turned on, the third auxiliary circuit and the fourth auxiliary circuit work together to make a second operating parameter of the main circuit a third value (for example Figure 4b T42 or Figure 5b When the third auxiliary circuit is turned on and the fourth auxiliary circuit is turned off, the third auxiliary circuit sets the operating parameter to a fourth value (e.g. Figure 4b T41 or Figure 5b v51 in the figure), the fourth value is different from the third value. A second operating tolerance of the main circuit covers the range between the third value and the fourth value. Figure 2) and the second control signal (eg, dvs_rawa_assert, Figure 2 ) will not switch levels simultaneously. In one embodiment, when the control signal switches levels (e.g., t1-t2, Figure 2 ), the second control signal switches its level (e.g., t3-t4) after a first delay time (e.g., Dt1). When the second control signal switches its level again (e.g., t5-t6), the control signal switches its level again (e.g., t7-t8) after a second delay time (e.g., Dt2). BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to better understand the above and other aspects of the present invention, the following embodiments are specifically described in detail with reference to the accompanying drawings:

[0015] Figure 1 FIG. 1 illustrates a circuit module according to an embodiment of the present invention, which may include three auxiliary units.

[0016] Figure 2 It indicates Figure 1 Waveform timing example of related signals.

[0017] Figure 3a 、 Figure 4a and Figure 5a Respectively indicate Figure 1 In the auxiliary unit embodiment, each auxiliary unit may include two auxiliary circuits.

[0018] Figure 3b 、 Figure 4b and Figure 5b Respectively indicate Figure 3a 、 Figure 4a and Figure 5a Waveform timing example of related signals.

[0019] The description of the accompanying drawings is as follows:

[0020] 100: Circuit module

[0021] 110: Main circuit

[0022] 120, y[1], y[p], y[P], x[1], x[k], x[K]: auxiliary units

[0023] 130, 140: Peripheral circuits

[0024] 150: Control circuit

[0025] 121, 122, y1[p], y2[p], x1[k], x2[k]: Auxiliary circuit

[0026] sn1, WTG, dvs_sa_relax, dvs_rawa_assert, vn1, vg31, vg1[p], vg3[p]: signals

[0027] VDD: supply voltage

[0028] CK: Clock

[0029] WL[1], WL[p], WL[P]: word lines

[0030] BL[1], BLb[1], BL[q], BLb[q], BL[Q], BLb[Q]: bit lines

[0031] c[1,1], c[1,q], c[1,Q], c[p,1], c[p,q], c[p,Q], c[P,1], c[P,q], c[P,Q]: storage cells

[0032] TWL: Follow Character Line

[0033] TBL, TBLb: Follow Bit Line

[0034] Tc[1], Tc[p], Tc[P]: follow-up storage unit

[0035] SA[1], SA[k], SA[K]: sense amplifiers

[0036] WB[1], WB[k], WB[K]: write circuit

[0037] vdd1, vdd2: power supply value

[0038] v0, v1: Level

[0039] T: period

[0040] T1, T2: period value

[0041] t21-t26, t1-t8, t30-t32, t3_01, t3_10, t3a-t3d, t40-t42, t4_01, t4_10, t4a-t4b, t50-t52, t5_01, t5_10: time point

[0042] Dt1, Dt2: delay time

[0043] 124. INV[p]: Inverter

[0044] g1[k], g2[k]: logic gates

[0045] NBL[k]: Negative bit line

[0046] n1-n4, a1[p]-a3[p], b1[k]: nodes

[0047] i1[k], i21[k], i22[k]: input terminals

[0048] o1[k], o2[k]: output terminals

[0049] M1-M4, H1[p]-H3[p]: transistors

[0050] C1[k], C2[k]: capacitors

[0051] WD[p]: word line driver

[0052] vw31-vw32, v31-v32, vw40-vw42, v41-v42, v50-52, v5a-v5b: voltage value

[0053] Tp1-Tp3: Operation cycle

[0054] vTWL, vTBL_0, vTBL_1, vTBL_01, vTBL_01t, vTBL_10, vTBL_10t, vWL[p], vWL[p]_0, vWL[p]_1, vWL[p]_01, vW L[p]_10, vBL[q]_0, vBL[q]_1, vBL[q]_01, vBL[q]_10, vNBL[k]_0, vNBL[k]_1, vNBL[k]_01, vNBL[k]_10: Waveform

[0055] T31-T32, T3a-T3d, T41-T42, T4a-T4b: Time DETAILED DESCRIPTION

[0056] Figure 1 The circuit module 100 according to one embodiment of the present invention may include a main circuit 110. To implement the technology of the present invention, the circuit module 100 further includes an auxiliary unit 120, y[1] to y[P] and x[1] to x[K]. Figure 1As shown, in one embodiment of the present invention, the circuit module 100 may be a memory module, such as an embedded static random access memory module; the main circuit 110 may be a memory array, including P*Q memory cells c[1,1] to c[P,Q], P word lines WL[1] to WL[P], Q groups of bit lines such as BL[1] to BL[Q] and BLb[1] to BLb[Q], P tracking memory cells Tc[1] to Tc[P], a tracking word line TWL, a group of tracking bit lines such as TBL and TBLb, K write circuits WB[1] to WB[K], K sense amplifiers SA[1] to SA[K], two peripheral circuits 130 and 140, and a control circuit 150. The numbers P, Q, and K may be integers greater than or equal to 1. With the support of the auxiliary unit 120, y[1] to y[P], and x[1] to x[K], the control circuit 150 can control the operation of the main circuit 110. Due to the auxiliary unit 120, y[1] to y[P], and x[1] to x[K] of the present invention, the main circuit 110 can switch between different operating conditions (or different modes, such as different supply voltage values ​​and / or different clock frequencies) without interrupting the ongoing operation; even if the operating condition switch occurs during a certain operating cycle of the main circuit 110 (such as a read cycle or a write cycle), the main circuit 110 can still continue the normal operation (such as reading or writing) in the operating cycle without affecting the correctness of the operation in the operating cycle. The technology of the present invention will be further described in detail later.

[0057] In master circuit 110, each memory cell c[p,q] (for p=1 to P and q=1 to Q) can be a static random access memory cell, coupled to a corresponding word line WL[p] and one or more bit lines, such as BL[q] and BLb[q]. Each memory cell c[p,q] can store one bit of data. Each tracking memory cell Tc[p] is coupled to a tracking word line TWL and one or more tracking bit lines, such as TBL and TBLb. Each tracking memory cell Tc[p] has the same circuit structure as each memory cell c[p,q] to reflect the response of each memory cell c[p,q]. The peripheral circuit 130 is coupled to the word lines WL[1] to WL[P], and the peripheral circuit 140 is coupled to the bit lines BL[1] to BL[Q] and BLb[1] to BLb[Q], the sense amplifiers SA[1] to SA[K], and the write circuits WB[1] to WB[K]. The control circuit 150 can provide a signal sn1 to the sense amplifiers SA[1] to SA[K] and a signal WTG to the write circuits WB[1] to WB[K]. The main circuit 110 is powered by a supply voltage VDD; for example, each memory cell c[p,q] can draw power from the supply voltage VDD to latch bit data. The control circuit 150 can control the operating cycle of the main circuit 110 (such as an access cycle, including a read cycle and a write cycle) based on a clock CK.

[0058] like Figure 1 As shown, auxiliary cell 120 is coupled to a control signal dvs_sa_relax, a following word line TWL, a following bit line TBL, and control circuit 150. Each auxiliary cell y[p] is coupled to a corresponding word line WL[p] and a control signal dvs_rawa_assert. Each auxiliary cell x[k] is coupled to signal WTG, signal dvs_rawa_assert, and a corresponding write circuit WB[k].

[0059] When data in memory cell c[p,q] is to be read, peripheral circuit 130 can drive word line WL[p], and peripheral circuit 140 can connect bit lines BL[q] and BLb[q] to one of sense amplifiers SA[1] to SA[K], allowing sense amplifier SA[k] to read the data stored in memory cell c[p,q] under the timing control of signal sn1. Auxiliary unit 120 can provide a signal vn1 based on signal dvs_sa_relax, and the timing of signal sn1 is related to signal vn1 (discussed in detail later). When peripheral circuit 130 drives word line WL[p], auxiliary unit y[p] can adjust the driving voltage based on signal dvs_rawa_assert (discussed in detail later).

[0060] When data is to be written into memory cell c[p,q], peripheral circuit 130 may drive word line WL[p], and peripheral circuit 140 may connect bit lines BL[q] and BLb[q] to one WB[k] of write circuits WB[1] to WB[K], enabling write circuit WB[k] to write data into memory cell c[p,q] under the triggering of signal WTG. When signal WTG is triggered, the corresponding auxiliary unit x[k] may induce a negative voltage on bit lines BL[q] and BLb[q] via write circuit WB[k], and adjust the magnitude of the negative voltage according to signal dvs_rawa_assert (discussed in detail later) to assist write circuit WB[k] in writing data into memory cell c[p,q].

[0061] Figure 1 The signals dvs_sa_relax and dvs_rawa_assert in FIG1 are related to the operating conditions of the circuit module 100, including the supply voltage VDD and the clock CK. Figure 1 , Figure 2 The diagram shows the switching of the supply voltage VDD and the clock CK in the circuit module 100 and the timing of the signals dvs_sa_relax and dvs_rawa_assert. Figure 2As shown, between time points t20 and t21 , the supply voltage VDD may be at the supply value vdd1 , the period T of the clock CK may be at the period value T1 , and the signal levels of the signals dvs_sa_relax and dvs_rawa_assert may be at the level v0 .

[0062] Between times t21 and t22, the supply voltage VDD can be maintained at the supply value vdd1, while the period T can be switched to another period value T2. Period values ​​T1 and T2 can be different. For example, period value T1 can be smaller than period value T2. That is, the clock CK can be switched from its original higher frequency (1 / T1) to a lower frequency (1 / T2) after time t21. Furthermore, between times t21 and t22, the signal dvs_sa_relax can be switched from level v0 to another different level v1 between t1 and t2. After a delay time Dt1, the signal dvs_rawa_assert can be switched from level v0 to level v1 between t3 and t4.

[0063] Between time points t22 and t23, the period T of the clock CK can be maintained at period value T2, the signals dvs_sa_relax and dvs_rawa_assert can be maintained at level v1, and the value of the supply voltage VDD can be switched from the supply value vdd1 to another different supply value vdd2; for example, the supply value vdd2 can be lower than the supply value vdd1.

[0064] Between time points t23 and t24, the supply voltage VDD can be maintained at the supply value vdd2, the period T of the clock CK can be maintained at the period value T2, and the signals dvs_sa_relax and dvs_rawa_assert can be maintained at the level v1. Before time point t21, the circuit module 100 originally operated at the supply value vdd1 and the period value T1 (e.g., a high-performance mode). After the handover preparation between time points t21 and t23, the circuit module 100's operating conditions can be switched to the supply value vdd2 and the period value T2 (e.g., a low-power mode) after time point t23.

[0065] Between time points t24 and t25 , the period T of the clock CK may be maintained at the period value T2 , the signals dvs_sa_relax and dvs_rawa_assert may be maintained at the level v1 , and the supply voltage VDD may be switched from the supply value vdd2 back to vdd1 .

[0066] Between time t25 and t26, the supply voltage VDD can be maintained at the supply value vdd1, and the period T can be maintained at the period value T2. Furthermore, between time t25 and t26, the signal dvs_rawa_assert can be switched from level v1 to level v0 at time t5 to t6. After a delay time Dt2, the signal dvs_sa_relax can be switched from level v1 to level v0 at time t7 to t8.

[0067] After time t26, the supply voltage VDD can be maintained at the supply value vdd1, the signals dvs_sa_relax and dvs_rawa_assert can be maintained at the level v0, and the cycle T switches back to the cycle value T1. Between time t23 and t24, the operating conditions of the circuit module 100 were originally the supply value vdd2 and the cycle value T2; after the handover preparation between time t24 and t26, the operating conditions of the circuit module 100 can be switched back to the supply value vdd1 and the cycle value T1 after time t26. Figure 2 It can be seen that the level switching of the signals dvs_sa_relax and dvs_rawa_assert corresponds to the switching of the operating conditions of the circuit module 100 .

[0068] continue Figure 1 and Figure 2 , Figure 3a The auxiliary unit 120 according to one embodiment of the present invention is shown. Figure 3b The following is an example of the waveform sequence of the relevant signals when the auxiliary unit 120 is running. Figure 3a As shown, the auxiliary unit 120 may include two auxiliary circuits 121 and 122 coupled to the tracking bit line TBL at a node n1. The voltage of the tracking bit line TBL at node n1 is the signal vn1, which can be received by the control circuit 150. The auxiliary circuit 121 may include two transistors M1 and M3, and the auxiliary circuit 122 may include two transistors M2 and M4 and an inverter 124. For example, each of the transistors M1 to M4 may be an n-type metal oxide semiconductor transistor.

[0069] In the auxiliary circuit 121, transistor M1 may include a controlled terminal (e.g., a gate terminal) and two channel terminals (e.g., a drain terminal and a source terminal), respectively coupled to a signal vg31, node n1, and another node n3. Transistor M3 may include a controlled terminal and two channel terminals, respectively coupled to the tracking word line TWL, node n3, and another node n4 (which may be a ground node).

[0070] In the auxiliary circuit 122, transistor M2 may include a controlled terminal and two channel terminals, the two channel terminals being coupled to nodes n1 and n2, respectively. The controlled terminal is coupled to the signal dvs_sa_relax via an inverter 124. Transistor M4 may include a controlled terminal and two channel terminals, respectively coupled to the tracking word line TWL and nodes n2 and n4.

[0071] like Figure 3b As shown, in an operation cycle Tp1 of the main circuit 110 (for example, a reading cycle, the length of which may be one cycle T of the clock CK, Figure 2 ), the voltage of the tracking word line TWL can be driven from a voltage value vw31 to another voltage value vw32 at time point t30, as shown in the waveform vTWL; as the tracking word line TWL is driven, the voltage of the tracking bit line TBL (i.e., signal vn1) will start to change (e.g., decrease) from a voltage value v31. The time it takes for the voltage of the tracking bit line TBL to change from voltage value v31 to another different voltage value v32 can be regarded as an operating parameter of the main circuit 110, hereinafter referred to as the tracking word line discharge time. The length of the tracking word line discharge time is reflected by the control circuit 150 in the timing of the signal sn1, and is used to control the operating timing of the sense amplifiers SA[1] to SA[K] accordingly, for example, controlling when to enable the sense amplifiers SA[1] to SA[K].

[0072] Under different operating conditions, the numerical values ​​of the operating parameters of main circuit 110 may also vary. As previously described, conventional circuit modules configure different mode-specific circuits for different modes (different operating conditions). Ideally, when one of these mode-specific circuits is enabled, the others are disabled, and the value of the operating parameter is determined by the enabled mode-specific circuit. However, in practice, when switching modes, the enabling and disabling of different mode-specific circuits is unpredictable and random, and there may be transient states between enabling and disabling. Consequently, the magnitude of the change in the operating parameters between different modes is also unpredictable.

[0073] In contrast, in the present invention, the length of the tracking bit line discharge time (the time it takes for the tracking bit line TBL to change from the voltage value v31 to the voltage value v32) is related to the two auxiliary circuits 121 and 122 in the auxiliary unit 120. However, the turning on and off of the auxiliary circuits 121 and 122 are not mutually exclusive. When the auxiliary circuit 121 is turned on, the auxiliary circuit 122 can respond to the signal dvs_sa_relax ( Figure 1 and Figure 2 ) to turn on or off according to different levels (corresponding to different operating conditions / different modes). Thus, the magnitude of the change in the discharge time of the bit line is no longer unpredictable. The operation of the two auxiliary circuits 121 and 122 is further described below.

[0074] Before time t30 , since the tracking word line TWL is not driven, the transistors M3 and M4 are both off, the auxiliary circuits 121 and 122 are both off, and the voltage of the tracking bit line TBL is a voltage value v31 .

[0075] After time t30, as the tracking word line TWL is driven, transistors M3 and M4 are turned on, and the voltage of signal vg31 also turns on transistor M1. Since both transistors M1 and M3 are turned on, auxiliary circuit 121 is turned on and can provide a conductive path between nodes n1 and n4.

[0076] After time t30, when the auxiliary circuit 121 is turned on, if the signal dvs_sa_relax is at level v0, the transistor M2 is turned on. Since both transistors M2 and M4 are turned on, the auxiliary circuit 122 is turned on and provides an additional conductive path between nodes n1 and n4. Therefore, after time t30, the tracking bit line TBL coupled to the node n1 can be discharged through the parallel conductive path provided by the two auxiliary circuits 121 and 122, and changes to a voltage value v32 at time t31, as shown in FIG. Figure 3b Therefore, the discharge time of the following bit line is time T31 (from time point t30 to t31).

[0077] After time t30, when the auxiliary circuit 121 is turned on, if the signal dvs_sa_relax is at level v1, the transistor M2 is turned off, the auxiliary circuit 122 is turned off, and no additional conductive path is provided between the nodes n1 and n4. Therefore, after time t30, the tracking bit line TBL is discharged to the node n4 via the single conductive path provided by the auxiliary circuit 121, and drops to the voltage value v32 at time t32. Figure 3b As shown in the waveform vTBL_1 in FIG. Therefore, the discharge time of the following bit line is time T32 (from time point t30 to t32). Figure 3b As shown in , time T32 is longer than time T31.

[0078] After time t30, when the auxiliary circuit 121 is turned on, if the signal dvs_sa_relax changes from level v0 to level v1 at time t3_01 in the same operating cycle Tp1, the auxiliary circuit 122 will be turned on from time t30 to t3_01, and then turned off at time t3_01. Therefore, the tracking bit line TBL will first discharge at a faster rate between time t30 and t3_01 (because both auxiliary circuits 121 and 122 are turned on), and then discharge at a slower rate after time t3_01 (because the auxiliary circuit 122 is turned off), and then drop to a voltage value v32 at time t3b. Figure 3bTherefore, the discharge time of the following bit line is time T3b (from time point t30 to t3b).

[0079] After time t30, when the auxiliary circuit 121 is turned on and the signal dvs_sa_relax changes from level v0 to level v1 at time t3_01, the auxiliary circuit 122 may need a transient period to switch from on to off. Therefore, the tracking bit line TBL will discharge at a faster rate between time t30 and t3_01, and then discharge at a gradually decreasing rate after time t3_01, and finally drop to voltage v32 at time t3a. Figure 3b Therefore, the following bit line discharge time will be time T3a (from time point t30 to t3a).

[0080] After time t30, when the auxiliary circuit 121 is turned on, if the signal dvs_sa_relax changes from level v1 to level v0 at time t3_10 in the same operating cycle Tp1, the auxiliary circuit 122 will be turned off from time t30 to t3_10, and then turned on again at time t3_10. Therefore, the tracking bit line TBL will discharge at a slower rate between time t30 and t3_10, and then discharge at a faster rate after time t3_10, and finally drop to a voltage value v32 at time t3c. Figure 3b Therefore, the discharge time of the following bit line is time T3c (from time point t30 to t3c).

[0081] After time t30, when the auxiliary circuit 121 is turned on and the signal dvs_sa_relax changes from level v1 to level v0 at time t3_10, the auxiliary circuit 122 may need a transient period to switch from off to on. Therefore, the tracking bit line TBL will discharge at a slow rate between time t30 and t3_10, then discharge at an increasing rate after time t3_10, and finally drop to voltage v32 at time t3d. Figure 3b Therefore, the discharge time of the following bit line is time T3d (from time point t30 to t3d).

[0082] Depend on Figure 3bIt can be seen that within the same operating cycle Tp1, regardless of whether the signal dvs_sa_relax maintains level v0, maintains level v1, switches from level v0 to level v1, or switches from level v1 to v0 (i.e., whether the same operating condition / mode is maintained or a different operating condition / mode is switched within the same operating cycle Tp1), the auxiliary circuit 121 is always turned on (after the tracking word line TWL is driven), and the auxiliary circuit 122 is turned on or off in response to the signal dvs_sa_relax being at level v0 or v1. This ensures that the voltage change of the tracking bit line TBL is always within the range of the waveforms vTBL_0 and vTBL_1, and the discharge time of the tracking bit line is always between times T31 and T32. Therefore, when the operating condition / mode is switched, the present invention avoids the inability to reliably infer the magnitude of the operating parameter change due to the uncertainty and transient behavior of the switching of circuits specific to different modes, as in the prior art. In the present invention, as long as the operating tolerance of the master circuit 110 can cover the range of time T31 to T32 (for example, the read timing of the sense amplifiers SA[1] to SA[K] can tolerate the timing variation from time T31 to T32), regardless of whether the signal dvs_sa_relax switches within the same operating cycle Tp1 (whether the operating condition / mode switches within the same operating cycle Tp1), the master circuit 110 can still continue normal operation (such as data reading) within the operating cycle Tp1, and the operating correctness (such as the correctness of the read data) within the operating cycle Tp1 is not affected.

[0083] continue Figure 1 and Figure 2 , Figure 4a The diagram shows an auxiliary unit y[p] (one of the auxiliary units y[1] to y[P]) according to an embodiment of the present invention. Figure 4b The figure shows the waveform sequence of the relevant signals when the auxiliary unit y[p] is running. Figure 4a As shown, the auxiliary unit y[p] may include two auxiliary circuits y1[p] and y2[p], coupled to the corresponding word line WL[p] at a node a1[p]. The word line WL[p] is also coupled to a word line driver WD[p] (e.g., an inverter) in the peripheral circuit 130. The auxiliary circuit y1[p] may include two transistors H1[p] and H3[p], and the auxiliary circuit y2[p] may include a transistor H2[p] and an inverter INV[p]. For example, transistors H1[p] and H2[p] may be p-type metal oxide semiconductor transistors, and transistor H3[p] may be an n-type metal oxide semiconductor transistor.

[0084] In auxiliary circuit y1[p], transistor H1[p] may include a controlled terminal and two channel terminals, each coupled to a signal vg1[p], node a1[p], and another node a2[p]. In one embodiment, the voltage of signal vg1[p] turns on transistor H1[p]. Transistor H3[p] may include a controlled terminal and two channel terminals, each coupled to a signal vg3[p], node a2[p], and another node a3[p] (which may be a ground node).

[0085] In auxiliary circuit y2[p], transistor H2[p] includes a controlled terminal and two channel terminals. The two channel terminals are coupled to nodes a1[p] and a2[p], respectively. The controlled terminal is coupled to signal dvs_rawa_assert via inverter INV[p]. When signal dvs_rawa_assert is at level v0, transistor H2[p] is non-conductive, and auxiliary circuit y2[p] is disabled. When signal dvs_rawa_assert is at level v1, transistor H2[p] is conductive, and auxiliary circuit y2[p] is enabled.

[0086] like Figure 4b As shown, in an operation cycle Tp2 of the main circuit 110 (for example, a reading cycle, the length of which may be one cycle T of the clock CK, Figure 2 ), when the memory cell c[p,q] on word line WL[p] is to be read, word line WL[p] may be driven at time t40. Consequently, the voltage of bit line BL[q] or BLb[q] may also begin to change (e.g., decrease) from a voltage value v41. For ease of explanation, it is assumed that the voltage of bit line BL[q] changes. The time it takes for the voltage of bit line BL[q] to change from voltage value v41 to another voltage value v42 can be considered an operating parameter of main circuit 110 and is hereinafter referred to as the bit line discharge time.

[0087] When word line WL[p] is driven at time t40, if signal dvs_rawa_assert is at level v0, word line WL[p] is driven from voltage vw40 to voltage vw42, as shown in waveform vWL[p]_0. Correspondingly, the voltage of bit line BL[q] begins to change (e.g., decrease) from voltage v41 after time t40, and changes to voltage v42 at time t41, as shown in waveform vBL[q]_0. Therefore, the bit line discharge time is time T41 (from time t40 to t41).

[0088] When word line WL[p] is driven at time t40, if signal dvs_rawa_assert is at level v1, word line WL[p] is driven from voltage vw40 to voltage vw41, as shown in waveform vWL[p]_1. Correspondingly, the voltage of bit line BL[q] changes to voltage v42 at time t42, as shown in waveform vBL[q]_1. Therefore, the bit line discharge time is time T42 (from time t40 to t42).

[0089] Voltage values ​​vw41 and vw42 can be different so that the voltage of word line WL[p] can adapt to different operating conditions during read operation. For example, voltage value vw42 can be greater than voltage value vw41. When word line WL[p] is driven at time t40, regardless of whether signal dvs_rawa_assert is at level v0 or v1, signals vg1[p] and vg3[p] ( Figure 4a ) will turn on the transistors H1[p] and H3[p], thereby turning on the auxiliary circuit y1[p].

[0090] When the word line WL[p] is driven at time t40, if the signal dvs_rawa_assert is at level v0, transistor H2[p] is non-conductive, and the auxiliary circuit y2[p] is also turned off. The turned-on auxiliary circuit y1[p] causes the voltage of the word line WL[p] to be a higher voltage value vw42. Conversely, if the signal dvs_rawa_assert is at level v1, transistor H2[p] is turned on, and the auxiliary circuit y2[p] is also turned on. The auxiliary circuits y1[p] and y2[p] combine to cause the voltage of the word line WL[p] to be a lower voltage value vw41. When the word line WL[p] is driven to a higher voltage value vw42 (such as waveform vWL[p]_0), the voltage change speed (such as discharge speed) of the bit line BL[q] is faster (such as waveform vBL[q]_0); when the word line WL[p] is driven to a lower voltage value vw41 (such as waveform vWL[p]_1), the voltage change speed of the bit line BL[q] is slower (such as waveform vBL[q]_1).

[0091] In one embodiment, the voltage value vw42 may be slightly lower than the power supply value vdd1 ( Figure 2 ), so as to realize read assistant by using word line underdrive when the supply voltage VDD is the supply value vdd1. In one embodiment, the voltage value vw41 can be substantially equal to the supply value vdd2 ( Figure 2 ) to stop the read assist of the word line low drive when the supply voltage VDD is the supply value vdd2.

[0092] like Figure 4bAs shown, after word line WL[p] is driven at time t40, if signal dvs_rawa_assert switches from level v0 to level v1 at time t4_01, word line WL[p] is first driven to voltage vw42 between time t40 and t4_01 (auxiliary circuits y1[p] and y2[p] are turned on and off, respectively), and then driven to voltage vw41 at time t4_01 (auxiliary circuits y1[p] and y2[p] are both turned on), as shown in waveform vWL[p]_01. Correspondingly, after time t40, the voltage of bit line BL[q] changes at a faster rate between time t40 and t4_01, then changes at a slower rate after time t4_01, reaching voltage v42 at time t4a, as shown in waveform vBL[q]_01. Therefore, the bit line discharge time is time T4a (time point t40 to t4a).

[0093] After word line WL[p] is driven at time t40, if signal dvs_rawa_assert switches from level v1 to level v0 at time t4_10, word line WL[p] is first driven to voltage vw41 between time t40 and t4_10 (auxiliary circuits y1[p] and y2[p] are both turned on), and then driven to voltage vw42 after time t4_10 (auxiliary circuits y1[p] and y2[p] are turned on and off, respectively), as shown in waveform vWL[p]_10. Correspondingly, after time t40, the voltage of bit line BL[q] changes at a slower rate between time t40 and t4_10, then changes at a faster rate after time t4_10, reaching voltage v42 at time t4b, as shown in waveform vBL[q]_10. Therefore, the bit line discharge time is time T4b (time point t40 to t4b).

[0094] Depend on Figure 4b It can be seen that even if the signal dvs_rawa_assert switches its level (corresponding to the switching of operating conditions / modes) in the same operating cycle Tp2, the bit line discharge time (such as time T4a or T4b) will still fall between time T41 and T42. Figure 4bHowever, when the signal dvs_rawa_assert switches its level during the same operating cycle Tp2, causing the auxiliary circuit y2[p] to switch on and off, even if there is a transient state during the switching of the auxiliary circuit y2[p], the bit line discharge time will still fall between time T41 and T42. Therefore, in the present invention, as long as the operating tolerance of the main circuit 110 can cover the range of time T41 to T42 (for example, the read timing of the sense amplifiers SA[1] to SA[K] can tolerate the timing variation between time T41 and T42), regardless of whether the signal dvs_rawa_assert switches during the same operating cycle Tp2 (whether the operating condition / mode switches during the same operating cycle Tp2), the main circuit 110 can still continue normal operation (such as data reading) during the operating cycle Tp2 without affecting the operating correctness (such as the correctness of the read data) during the operating cycle Tp2.

[0095] continue Figure 1 and Figure 2 , Figure 5a The diagram shows an auxiliary unit x[k] (one of the auxiliary units x[1] to x[K]) according to an embodiment of the present invention. Figure 5b The following is a diagram showing the waveform sequence of the relevant signals when the auxiliary unit x[k] is running. Figure 5a As shown, the auxiliary unit x[k] may include two auxiliary circuits x1[k] and x2[k], coupled to a negative voltage bit line NBL[k] at a node b1[k]. Node b1[k] may be coupled to the write circuit WB[k] via the negative voltage bit line NBL[k]. The auxiliary circuit x1[k] may include a logic gate g1[k] and a capacitor C1[k]. The auxiliary circuit x2[k] may include a logic gate g2[k] and a capacitor C2[k]. The logic gate g1[k] may be an inverter having an input terminal i1[k] and an output terminal o1[k]. The capacitor C1[k] is coupled between the output terminal o1[k] and the node b1[k]. The logic gate g2[k] can be an NAND gate having two input terminals i21[k] and i22[k] and an output terminal o2[k]; the two input terminals i21[k] and i22[k] are coupled to the input terminal i1[k] and the signal dvs_rawa_assert respectively, and the capacitor C2[k] is coupled between the output terminal o2[k] and the node b1[k]. Figure 5a As shown, the signal WTG is coupled to the auxiliary circuits x1[k] and x2[k] via the input terminals i1[k] and i21[k] respectively, and the signal dvs_rawa_assert is coupled to the auxiliary circuit x2[k] via the input terminal i22[k].

[0096] like Figure 5b As shown, in an operation cycle Tp3 of the main circuit 110 (for example, a write cycle, the length of which may be one cycle T of the clock CK, Figure 2 ), when data is to be written into the memory cell c[p,q] on the word line WL[p], the peripheral circuit 140 conducts the corresponding bit lines BL[q] and BLb[q] to the write circuit WB[k], and the word line WL[p] is driven from a voltage value vw51 to another voltage value vw52 at time t50, as shown in the waveform vWL[p]; the signal WTG( Figure 5a ) triggers the write circuit WB[k] to write data. Consequently, the voltage of the negative voltage bit line NBL[k] changes (e.g., decreases) from a voltage value v50 (e.g., a ground voltage) to a voltage extreme, and then reverses (e.g., increases) back to voltage v50, presenting a pulse waveform. The voltage extreme of the negative voltage bit line NBL[k] can be considered an operating parameter of the main circuit 110, hereinafter referred to as the bit line negative voltage value. The voltage waveform of the negative voltage bit line NBL[k] is applied to the bit lines BL[q] and BLb[q] via the write circuit WB[k] and the peripheral circuit 140 to implement write assistance.

[0097] like Figure 5b As shown, after time t50, if the signal dvs_rawa_assert is at level v1, the auxiliary circuits x1[k] and x2[k] are both turned on. When the signal WTG is triggered, the two circuits jointly cause the voltage of the negative voltage bit line NBL[k] to change to waveform vNBL[k]_1, reaching an extreme value (voltage value v52) at time t52, resulting in a negative voltage value of the bit line v52.

[0098] After time t50, if signal dvs_rawa_assert is at level v0, auxiliary circuit x2[k] is disabled, leaving only auxiliary circuit x1[k] enabled. Therefore, when signal WTG is triggered, auxiliary circuit x1[k] alone causes the voltage of negative voltage bit line NBL[k] to change to waveform vNBL[k]_0, reaching its extreme value (voltage v51) at time t51. Consequently, the negative voltage of the bit line is voltage v51.

[0099] After time t50, if the signal dvs_rawa_assert switches from level v0 to level v1 at time t5_01 in the same operating cycle Tp3, the auxiliary circuit x2[k] switches from off to on while the auxiliary circuit x1[k] is on. The voltage change of the negative voltage bit line NBL[k] will take the waveform vNBL[k]_01, resulting in a negative voltage value of the bit line v5a.

[0100] After time t50, if the signal dvs_rawa_assert switches from level v1 to level v0 at time t5_10 in the same operating cycle Tp3, the auxiliary circuit x2[k] switches from on to off while the auxiliary circuit x1[k] is on. The voltage of the negative voltage bit line NBL[k] changes as waveform vNBL[k]_10, resulting in a negative voltage value of the bit line v5b.

[0101] Depend on Figure 5b It can be seen that even if the signal dvs_rawa_assert switches its level (corresponding to the switching of operating conditions / modes) in the same operating cycle Tp3, the negative voltage value of the bit line (such as voltage value v5a or v5b) will still fall between voltage values ​​v51 and v52. Figure 5b However, when the signal dvs_rawa_assert switches levels during the same operating cycle Tp3, causing the auxiliary circuit x2[p] to switch on and off, even if there is a transient state during the switching of the auxiliary circuit x2[p], the negative voltage on the bit line will still fall between voltages v51 and v52. Therefore, in the present invention, as long as the operating tolerance of the main circuit 110 covers the range of voltages v51 to v52 (for example, the bit lines BL[q] and BLb[q] can tolerate negative voltage variations between voltages v51 and v52), the main circuit 110 can continue normal operation (e.g., data writing) during the operating cycle Tp3 regardless of whether the signal dvs_rawa_assert switches during the same operating cycle Tp3 (whether the operating conditions / modes switch during the same operating cycle Tp3), and the operational correctness (e.g., the correctness of the written data) during the operating cycle Tp3 will not be affected.

[0102] In summary, the prior art sets different mode-specific circuits for different modes; when switching modes, one mode-specific circuit must be switched from off to on, and the other mode-specific circuit must be switched from on to off. Due to the uncertainty and transient nature of the on and off of different mode-specific circuits, the prior art has difficulty in reliably determining the range of relevant operating parameters and tolerances, and consequently, cannot continue normal operation when the mode is switched. In contrast, the auxiliary unit in the present invention may include two auxiliary circuits; when the relevant control signal switches levels (corresponding to the switching of operating conditions / modes), only one of the two auxiliary circuits will switch on and off accordingly, and the other auxiliary circuit will be on regardless of the control signal. Therefore, the present invention can clearly and reliably know the change amplitude and corresponding tolerance of the relevant operating parameters, thereby allowing the circuit module of the present invention to continue normal operation when the operating conditions / modes are switched. Even if the switching of operating conditions / modes occurs during an operating cycle, the circuit module of the present invention can still continue normal operation in that operating cycle.

[0103] In summary, although the present invention has been disclosed above with reference to the embodiments, these are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A circuit module with reliable tolerance setting, comprising: A main circuit comprising a first node; a first auxiliary circuit coupled to the first node; and a second auxiliary circuit coupled to the first node and a control signal; wherein: When the first auxiliary circuit is turned on, the second auxiliary circuit is turned on or off according to whether the control signal is at a first level or a second level; When the first auxiliary circuit and the second auxiliary circuit are both turned on, the first auxiliary circuit and the second auxiliary circuit work together to make an operating parameter of the main circuit a first value; When the first auxiliary circuit is turned on and the second auxiliary circuit is turned off, the first auxiliary circuit causes the operating parameter to be a second value, the second value being different from the first value; and An operating tolerance of the main circuit covers a range between the first value and the second value.

2. The circuit module according to claim 1, wherein: When the supply voltage of the main circuit is a first supply value and the period of a clock running the main circuit is a first period value, the control signal is the first level; When the supply voltage of the main circuit is a second supply value and the period of the clock is a second period value, the control signal is at the second level; as well as The first power supply value is different from the second power supply value, and the first cycle value is different from the second cycle value.

3. The circuit module according to claim 1, wherein: The main circuit includes: At least one memory cell coupled to a word line and a bit line; At least one following memory cell is coupled to a following word line and a following bit line, and the first node is coupled to the following bit line; as well as A sense amplifier is coupled to the bit line.

4. The circuit module according to claim 3, wherein: The first auxiliary circuit comprises: a first transistor comprising a first controlled terminal and two first channel terminals; the two first channel terminals are respectively coupled to the first node and a third node; and a third transistor comprising a third controlled terminal and two third channel terminals; the two third channel terminals are respectively coupled to the third node and a fourth node, and one of the first controlled terminal and the third controlled terminal is coupled to the tracking word line; and The second auxiliary circuit comprises: a second transistor comprising a second controlled terminal and two second channel terminals; the two second channel terminals are coupled to the first node and a second node respectively; and A fourth transistor includes a fourth controlled terminal and two fourth channel terminals; the two fourth channel terminals are coupled to the second node and the fourth node respectively; one of the second controlled terminal and the fourth controlled terminal is coupled to the control signal, and the other of the second controlled terminal and the fourth controlled terminal is coupled to the tracking word line.

5. The circuit module according to claim 3, wherein: The operating parameter is the time it takes for the voltage of the following bit line to change to a second voltage value after the following word line is driven.

6. The circuit module according to claim 3, wherein: The operating parameter is the time it takes for the voltage of the tracking bit line to change from a first voltage value to a second voltage value.

7. The circuit module according to claim 3, wherein: The operating margin is the timing margin of the sense amplifier.

8. The circuit module according to claim 1, wherein: The main circuit includes: At least one memory cell is coupled to a word line and a bit line, and the first node is coupled to the word line; and A sense amplifier is coupled to the bit line.

9. The circuit module according to claim 8, wherein: The first auxiliary circuit comprises: a first transistor comprising two first channel terminals respectively coupled to the first node and a second node; and a third transistor comprising two third channel terminals respectively coupled to the second node and a third node; and The second auxiliary circuit comprises: A second transistor includes a second controlled end and two second channel ends; the second controlled end is coupled to the control signal, and the two second channel ends are coupled to the first node and the second node respectively.

10. The circuit module according to claim 8, wherein: The operating parameter is the time it takes for the voltage of the bit line to change from a third voltage value to a fourth voltage value.

11. The circuit module according to claim 8, wherein: The operating parameter is the time it takes for the voltage of the bit line to change to a fourth voltage value after the word line is driven.

12. The circuit module according to claim 8, wherein: When the word line is driven, if the control signal is at the first level, the voltage of the word line is a fifth voltage value; if the control signal is at the second level, the voltage of the word line is a sixth voltage value, and the fifth voltage value is different from the sixth voltage value.

13. The circuit module according to claim 8, wherein: The operating margin is the timing margin of the sense amplifier.

14. The circuit module according to claim 1, wherein: The main circuit includes: At least one memory cell coupled to a word line and a bit line; A write circuit is coupled to the bit line and a negative voltage bit line, and the first node is coupled to the negative voltage bit line.

15. The circuit module according to claim 14, wherein: The first auxiliary circuit comprises: a first logic gate comprising a first input terminal and a first output terminal; and a first capacitor coupled between the first output terminal and the first node; and The second auxiliary circuit comprises: a second logic gate comprising two second input terminals and a second output terminal, wherein the two second input terminals are respectively coupled to the first input terminal and the control signal; and A second capacitor is coupled between the second output terminal and the first node.

16. The circuit module according to claim 15, wherein: The first logic gate is an inverter, and the second logic gate is a NAND gate.

17. The circuit module according to claim 14, wherein: The operating parameter is: the voltage extreme value of the negative voltage bit line after the word line is driven.

18. The circuit module according to claim 14, wherein: The operating margin is the negative voltage tolerance of the bit line.

19. The circuit module according to claim 1, further comprising: a third auxiliary circuit coupled to a fourth node; a fourth auxiliary circuit coupled to the fourth node and a second control signal; wherein: When the third auxiliary circuit is turned on, the fourth auxiliary circuit is turned on or off according to whether the second control signal is at a third level or a fourth level; When the third auxiliary circuit and the fourth auxiliary circuit are both turned on, the third auxiliary circuit and the fourth auxiliary circuit work together to make a second operating parameter of the main circuit a third value; When the third auxiliary circuit is turned on and the fourth auxiliary circuit is turned off, the third auxiliary circuit causes the second operating parameter to be a fourth value, which is different from the third value; A second operating tolerance of the main circuit covers a range between the third value and the fourth value; as well as The control signal and the second control signal will not switch levels at the same time.

20. The circuit module according to claim 19, wherein: When the control signal switches level, the second control signal switches level after a first delay time; and When the second control signal switches level again, the control signal switches level again after a second delay time.

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