Isolated switching converter and controller and control method thereof

Abstract

The application discloses an isolated switching converter, a controller and a control method thereof. The switching converter comprises a transformer, a primary switch tube and an isolation circuit. The control method comprises: generating a first compensation signal based on the difference between an output feedback signal representing an output signal of the switching converter and a reference voltage; generating a first and a second control signal based on the first compensation signal; sending the first control signal to a first channel of the isolation circuit to generate a first synchronization signal electrically isolated from the first control signal; sending the second control signal to a second channel of the isolation circuit to generate a second synchronization signal electrically isolated from the second control signal; generating a first threshold voltage for controlling the peak value of the current flowing through the primary switch tube based on the first synchronization signal; and generating a turn-on control signal of the primary switch tube based on the second synchronization signal to control the working frequency of the primary switch tube.

Description

Technical Field

[0001] This invention relates to electronic circuits, and more particularly to a quasi-resonant controlled isolated switching converter, its controller, and control method. Background Technology

[0002] Isolated switching power supplies are widely used in various offline power supply systems. Isolated switching converters typically include a transformer with primary and secondary windings to provide isolation. A primary switch is coupled to the primary winding, controlling the transfer of energy stored in the primary winding to the secondary winding. A secondary switch is coupled to the secondary winding, providing a stable output voltage to the load coupled to the secondary side. In peak current controlled isolated switching power supplies, the primary switch is turned off when the current flowing through it reaches a turn-off threshold, thereby controlling the energy transferred to the load. Since a constant peak current leads to inefficiency under light load conditions, the peak current signal often needs to vary with the load. However, in isolated switching power supplies without optocouplers, how to achieve isolated communication between the primary and secondary sides and transmit load change information from the secondary side to the primary side is the problem this invention aims to solve. Summary of the Invention

[0003] In view of one or more problems existing in the prior art, the purpose of the present invention is to provide an isolated switching converter and its controller and control method that can effectively realize communication isolation between the primary side and the secondary side.

[0004] According to an embodiment of the present invention, a controller for an isolated switching converter includes a transformer having a primary winding and a secondary winding, a primary switching transistor coupled to the primary winding, and a secondary switching transistor coupled to the secondary winding. The controller includes: an error amplifier circuit that receives an output feedback signal related to the output signal of the switching converter and generates a first compensation signal at its output terminal based on the difference between the output feedback signal and a reference voltage; a control signal generation circuit that generates a first control signal and a second control signal at its output terminal based on the first compensation signal; and an isolation circuit having a first channel for transmitting the first control signal and a second channel for transmitting the second control signal. A dual-channel circuit provides a first synchronization signal electrically isolated from a first control signal at a first output terminal and a second synchronization signal electrically isolated from a second control signal at a second output terminal; a threshold generation circuit is coupled to the first output terminal of the isolation circuit to receive the first synchronization signal and provides a first threshold voltage at the output terminal based on the first synchronization signal; a peak comparison circuit compares a current detection signal representing the current flowing through the primary switch with the first threshold voltage and generates a turn-off control signal at the output terminal; and a primary logic circuit generates a primary control signal at the output terminal based on the second synchronization signal and the turn-off control signal to control the on and off of the primary switch.

[0005] An isolated switching converter according to an embodiment of the present invention includes the controller as described above.

[0006] According to an embodiment of the present invention, a control method for an isolated switching converter includes a transformer having a primary winding and a secondary winding, a primary switching transistor coupled to the primary winding, a secondary switching transistor coupled to the secondary winding, and an isolation circuit. The control method includes: generating an output feedback signal based on an output signal of the switching converter; generating a first compensation signal based on the difference between the output feedback signal and a reference voltage; generating a first control signal and a second control signal based on the first compensation signal; sending the first control signal into a first channel of the isolation circuit to generate a first synchronization signal electrically isolated from the first control signal; sending the second control signal into a second channel of the isolation circuit to generate a second synchronization signal electrically isolated from the second control signal; generating a first threshold voltage based on the first synchronization signal to control the peak value of the current flowing through the primary switching transistor; and generating a turn-on control signal for the primary switching transistor based on the second synchronization signal to control the operating frequency of the primary switching transistor.

[0007] In an embodiment of the present invention, a dual-channel isolation circuit is used to receive a first synchronization signal that controls the peak current of the primary switch and a second synchronization signal that controls the frequency of the primary switch, respectively. This ensures that the primary switch is accurately turned on at the valley bottom while adjusting the threshold voltage of the current according to the load change, thereby controlling the energy supplied to the load and improving the efficiency of the switching converter. Attached Figure Description

[0008] Figure 1 This is a block diagram of an isolated switching converter 100 according to an embodiment of the present invention;

[0009] Figure 2 This is a block diagram of an isolated switching converter 100A according to an embodiment of the present invention;

[0010] Figure 3 This is a circuit schematic diagram of a control signal generation circuit 102 according to an embodiment of the present invention;

[0011] Figure 4 This is a circuit diagram of an error amplifier circuit 101 and a control signal generation circuit 102A according to an embodiment of the present invention.

[0012] Figure 5 This is a flowchart of a method for determining a target trough value according to an embodiment of the present invention;

[0013] Figure 6 This is a circuit diagram of a primary-side control circuit according to an embodiment of the present invention;

[0014] Figure 7 This is a waveform diagram of an isolated switching converter according to an embodiment of the present invention.

[0015] Figure 8 This is a waveform diagram of an isolated switching converter according to another embodiment of the present invention;

[0016] Figure 9 This is a flowchart of a control method 700 for a quasi-resonant controlled isolated switching converter according to an embodiment of the present invention. Detailed Implementation

[0017] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0018] Throughout this specification, references to “an embodiment,” “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “in an embodiment,” “in an embodiment,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It should be understood that when an element is referred to as “connected to” or “coupled” to another element, it can be a direct connection or coupling to the other element or there may be intermediate elements. Conversely, when an element is referred to as “directly connected to” or “directly coupled to” another element, there are no intermediate elements. The same reference numerals indicate the same elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0019] This invention can be applied to any isolated converter. In the following detailed description, for the sake of brevity, only a flyback converter will be used as an example to explain the specific working principle of this invention.

[0020] Figure 1 This is a block diagram of an isolated switching converter 100 according to an embodiment of the present invention. Figure 1As shown, the isolated switching converter 100 includes a transformer T, a primary switch 10, a secondary switch 20, and a controller 30. The transformer T has a primary winding and a secondary winding, both having a first terminal and a second terminal. The first terminal of the primary winding receives an input voltage Vin, and the first terminal of the secondary winding provides a DC output voltage Vo. The second terminal is coupled to a secondary reference ground. The primary switch 10 is coupled between the second terminal of the primary winding and the primary reference ground. The secondary switch 20 is coupled between the second terminal of the secondary winding and the load. However, those skilled in the art will understand that the secondary switch 20 can also be coupled between the first terminal of the secondary winding and the load.

[0021] exist Figure 1 In the illustrated embodiment, the controller 30 of the isolated switching converter 100 incorporates quasi-resonant control. In quasi-resonant control, the switching converter operates in a non-current continuous mode. When the current flowing through the energy storage element (transformer T) drops to zero, the parasitic capacitance of the energy storage element and the primary switching transistor 10 begins to resonate, generating a resonant voltage waveform. When the resonant voltage across the primary switching transistor 10 reaches its minimum value, the primary switching transistor 10 is turned on (commonly referred to as valley conduction), thereby reducing the switching losses and electromagnetic interference of the switching converter 100.

[0022] The controller 30 includes an error amplifier circuit 101, a control signal generation circuit 102, an isolation circuit 103, a threshold generation circuit 104, a peak comparison circuit 105, and a primary logic circuit 106. In some embodiments, the controller 30 is integrated with the secondary switch 20 on the same chip, and a drive circuit is provided for the secondary switch 20.

[0023] exist Figure 1 In the disconnect switch converter 100 shown, the controller 30 has multiple pins, including the output feedback pin FB, the compensation pin COMP, the secondary reference ground pin SGND, the primary current detection pin CS, the primary control pin PDrv, and the primary reference ground pin PGND.

[0024] Error amplifier circuit 101 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the output feedback pin FB to receive an output feedback signal VFB related to the output signal of the switching converter 100 (e.g., output voltage Vo). The second input terminal receives a reference voltage VREF. The output terminal is coupled to the compensation pin COMP. Error amplifier circuit 101 generates a first compensation signal Vcomp at the output terminal based on the difference between the output feedback signal VFB and the reference voltage VREF.

[0025] The control signal generation circuit 102 is coupled to the compensation pin COMP to receive the first compensation signal Vcomp. Based on the first compensation signal Vcomp, the control signal generation circuit 102 generates a first control signal PL1 and a second control signal PL2 at its output terminal to control the first threshold voltage VTH and the switching frequency of the primary switching transistor 10, respectively. The isolation circuit 103 has a first channel for transmitting the first control signal PL1 and a second channel for transmitting the second control signal PL2. It provides a first synchronization signal SYNC1, which is electrically isolated from the first control signal PL1, at its first output terminal and a second synchronization signal SYNC2, which is electrically isolated from the second control signal PL2, at its second output terminal.

[0026] like Figure 1 As shown, the threshold generation circuit 104 is coupled to the first output of the isolation circuit 103 to receive the first synchronization signal SYNC1, and provides a first threshold voltage VTH at the output based on the first synchronization signal SYNC1. The peak comparator circuit 105 has a first input, a second input, and an output, wherein the first input is coupled to the primary current detection pin CS to receive the current detection signal VCS representing the current flowing through the primary switch, and the second input is coupled to the output of the threshold generation circuit 104 to receive the first threshold voltage VTH. The peak comparator circuit 105 compares the current detection signal VCS with the first threshold voltage VTH and provides a turn-off control signal RST at the output. The primary logic circuit 106 generates a primary control signal CTRLP at the output based on the second synchronization signal SYNC2 and the turn-off control signal RST, which is coupled to the control terminal of the primary switch 10 via the primary control pin PDrv to control the turn-on and turn-off of the primary switch 10.

[0027] exist Figure 1 In the illustrated embodiment, the isolation circuit 103 provides dual-channel communication isolation, transmitting a first synchronization signal SYNC1, electrically isolated from the first control signal PL1, and a second synchronization signal SYNC2, electrically isolated from the second control signal PL2, to the primary side. The first synchronization signal SYNC1 is configured to control the first threshold voltage VTH of the primary switch 10 to control the energy supplied to the load, and the second synchronization signal SYNC2 is configured to control the switching frequency of the primary switch 10.

[0028] Figure 2 This is a block diagram of an isolated switching converter 100A according to an embodiment of the present invention. Figure 1 Compared to the switching converter 100, Figure 2 The switching converter 100A shown further includes a zero-crossing detection circuit 107 and a conduction control circuit 108.

[0029] The zero-crossing detection circuit 107 is used to detect whether the resonant voltage across the primary switch 10 has reached its minimum value, i.e., the trough. Figure 2 In the illustrated embodiment, the isolated switching converter 100A further includes an auxiliary winding located on the primary side, which is coupled to the zero-crossing detection pin ZCD of the controller 30 via a resistor divider circuit. A zero-crossing detection circuit 107 is coupled to the zero-crossing detection pin ZCD to receive the zero-crossing detection signal VZCD. The zero-crossing detection circuit 107 compares the zero-crossing detection signal VZCD with the zero-crossing threshold voltage VZCD_TH and outputs a zero-crossing signal SET0 at its output terminal.

[0030] The turn-on control circuit 108 generates a turn-on control signal SET at its output terminal, based on the second synchronization signal SYNC2 and the zero-crossing signal SET0, to control the operating frequency of the primary switching transistor 10. Figure 2 In the illustrated embodiment, the turn-on control circuit 108 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the second output terminal of the isolation circuit 103 to receive the second synchronization signal SYNC2, and the second input terminal is coupled to the zero-crossing detection circuit 107 to receive the zero-crossing signal SET0. Based on the zero-crossing signal SET0 and the second synchronization signal SYNC2, the turn-on control circuit 108 provides a turn-on control signal SET at its output terminal to control the turn-on of the primary switch 10. In one embodiment, when the second synchronization signal SYNC2 arrives and the resonant voltage across the primary switch 10 reaches its minimum value, the primary switch 10 is turned on.

[0031] Figure 3 This is a circuit schematic diagram of a control signal generation circuit 102 according to an embodiment of the present invention. Figure 3 In the illustrated embodiment, the control signal generation circuit 102 includes a first control signal generation circuit 120 and a second control signal generation circuit 121.

[0032] like Figure 3 As shown, the first control signal generation circuit 120 includes a hysteresis compensation circuit 1201, a first comparison circuit 1202, and a first pulse circuit 1203. The hysteresis compensation circuit 1201 is coupled to the output of the error amplifier circuit 101 to receive a first compensation signal Vcomp, and provides a second compensation signal Vcomp1 at the output based on the first compensation signal Vcomp. In one embodiment, the hysteresis compensation circuit 1201 superimposes a hysteresis signal onto the first compensation signal Vcomp. In another embodiment, the second compensation signal Vcomp1 is proportional to the first compensation signal Vcomp, and its proportionality coefficient is K1.

[0033] The first comparator circuit 1202 is coupled to the output of the hysteresis compensation circuit 1201 to receive the second compensation signal Vcomp1, and coupled to the output of the modulation signal generation circuit 1210 to receive the modulation signal VCT. The first comparator circuit 1202 compares the second compensation signal Vcomp1 with the modulation signal VCT and generates a first comparison signal CMP1 at its output. The first pulse circuit 1203 receives the first comparison signal CMP1 and provides a pulse-form first control signal PL1 at its output, which is transmitted to the primary side through the first channel of the isolation circuit 103.

[0034] exist Figure 3 In the illustrated embodiment, the second control signal generation circuit 121 includes a second comparison circuit 1211, a valley detection circuit 1212, a valley locking circuit 1213, and a second pulse circuit 1214. The second comparison circuit 1211 is coupled to the output of the error amplifier circuit 101 to receive a first compensation signal Vcomp, and coupled to the modulation signal generation circuit 1210 to receive a modulation signal VCT. It compares the modulation signal VCT with the first compensation signal Vcomp and generates a second comparison signal CMP2 at its output. The valley detection circuit 1212 is used to detect the waveform of the resonant voltage. In one embodiment, the valley detection circuit 1212 is coupled to the secondary switch 20 to detect the waveform of the resonant voltage and outputs a valley pulse signal VP representing one or more valleys of the resonant voltage. The valley locking circuit 1213 receives the first comparison signal CMP1 and the second comparison signal CMP2 to receive the valley pulse signal VP, provides a target valley value for the primary switch to turn on at its output, and generates a frequency control signal FS corresponding to the target valley value. In one embodiment, the valley locking circuit 1213 compares the valley value when the modulation signal VCT reaches the second compensation signal Vcomp1 with the current locked valley value, and decides whether to increase the target valley value based on the comparison result. It also compares the valley value when the modulation signal VCT reaches the first compensation signal Vcomp with the current locked valley value, and decides whether to decrease the target valley value based on the comparison result.

[0035] The second pulse circuit 1214 provides a pulse-shaped second control signal PL2 at its output terminal based on the frequency control signal FS, which is transmitted to the primary side through the second channel of the isolation circuit 103.

[0036] Figure 4 This is a circuit diagram of an error amplifier circuit 101 and a control signal generation circuit 102A according to an embodiment of the present invention. Figure 4 In the illustrated embodiment, the error amplifier circuit 101 includes an error amplifier EA. The error amplifier EA has a non-inverting input, an inverting input, and an output, wherein the non-inverting input receives an output feedback signal VFB, the inverting input receives a reference voltage VREF, and the output provides a first compensation signal Vcomp.

[0037] like Figure 4 As shown, the control signal generation circuit 102A includes a first control signal generation circuit 120A and a second control signal generation circuit 121A. The first control signal generation circuit 121A includes a hysteresis compensation circuit 1201A, a first comparison circuit 1202A, and a first pulse circuit 1203. The hysteresis compensation circuit 1201A includes a proportional circuit. The proportional circuit receives a first compensation signal Vcomp and provides a second compensation signal Vcomp1 at its output. In one embodiment, the second compensation signal Vcomp1 = K1 * Vcomp, where K1 is a proportionality coefficient greater than 1.

[0038] like Figure 4 As shown, the modulation signal generation circuit 1210A includes a voltage source VPK, a switching transistor ST, a capacitor CT, and a resistor RT. Figure 4 As shown, the voltage source VPK has a positive terminal and a negative terminal, with the negative terminal coupled to the secondary reference ground. The switching transistor ST has a first terminal, a second terminal, and a control terminal; the first terminal is coupled to the positive terminal of the voltage source VPK, and the control terminal is connected to the second control signal PL2. The capacitor CT has a first terminal and a second terminal, with the first terminal coupled to the second terminal of the switching transistor ST, and the second terminal connected to the secondary reference ground. The resistor RT has a first terminal and a second terminal, with the first terminal coupled to the first terminal of the capacitor CT, and the second terminal connected to the secondary reference ground. The modulation signal VCT is generated at the first terminal of the capacitor CT. When the second control signal PL2 is active, the modulation signal VCT is pulled high to its peak voltage, and then begins to decrease until the second control signal PL2 becomes active again.

[0039] The first comparator circuit 1202A includes a comparator COM1. The non-inverting input of comparator COM1 receives a second compensation signal Vcomp1, and its inverting input is coupled to the first terminal of capacitor CT to receive a modulation signal VCT. The output provides a first comparison signal CMP1. The second comparator circuit 1211A includes a comparator COM2. The non-inverting input of comparator COM2 receives the first compensation signal Vcomp, and its inverting input is coupled to the first terminal of capacitor CT to receive the modulation signal VCT. The output provides a second comparison signal CMP2.

[0040] Figure 5 This is a flowchart of a method for determining a target trough value according to an embodiment of the present invention. Figure 5 As shown, the method 130 for generating the target valley value includes steps 131 to 137.

[0041] In step 131, the valley count value when the first comparison signal is valid is recorded as the first specified valley value.

[0042] In step 132, the valley count value when the second comparison signal is valid is recorded as the second specified valley value.

[0043] In step 133, it is determined whether the first specified valley value is less than the currently locked valley value. If it is less, proceed to step 135. Otherwise, proceed to step 134, where the target valley value is increased.

[0044] In step 135, it is determined whether the difference between the second specified valley value and the currently locked valley value is greater than a preset value. If it is greater, proceed to step 137, where the target valley value is reduced. Otherwise, proceed to step 136, where the target valley value is equal to the currently locked valley value.

[0045] Figure 6 This is a circuit diagram of a primary-side control circuit according to an embodiment of the present invention. Figure 6 As shown, the primary side control circuit includes a threshold generation circuit 104A, a peak comparison circuit 105A, a conduction control circuit 108A, and a primary logic circuit 106A.

[0046] exist Figure 6 In the illustrated embodiment, the threshold generation circuit 104A includes a first capacitor C1. When the rising edge of the second synchronization signal SYNC2 arrives, the voltage across the first capacitor C1 is set high to the upper threshold voltage Vs2. After that, the voltage across the first capacitor C1 begins to decrease, and when the first synchronization signal SYNC1 arrives, the voltage across the first capacitor C1 is sampled and held to provide the first threshold voltage VTH.

[0047] like Figure 6As shown, the threshold generation circuit 104A further includes a timing circuit 1041, a trigger FF1, voltage sources V1 and V2, switching transistors S1 and S2, a resistor R2, and a sample-and-hold circuit 1042. The timing circuit 1041 has an input terminal and an output terminal, wherein the input terminal is coupled to the second output terminal of the isolation circuit 103 to receive the second synchronization signal SYNC2. The timing circuit 1041 performs timing based on the second synchronization signal SYNC2 and generates a timing signal DLY at its output terminal. The trigger FF1 has a set terminal, a reset terminal, and an output terminal, wherein the set terminal receives the second synchronization signal SYNC2, and the reset terminal is coupled to the output terminal of the timing circuit 1041 to receive the timing signal DLY. The voltage source V1 provides a lower threshold voltage Vs1 and has a positive terminal and a negative terminal, wherein the negative terminal is coupled to the primary reference ground. The voltage source V2 provides an upper threshold voltage Vs2 and has a positive terminal and a negative terminal, wherein the negative terminal is coupled to the primary reference ground. Switch S1 has a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the first terminal of the first capacitor C1, the second terminal is coupled to the positive terminal of the voltage source V2, and the control terminal is coupled to the output terminal of the flip-flop FF1. Switch S2 has a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the first terminal of the first capacitor C1, the second terminal is coupled to the positive terminal of the voltage source V1 via resistor R2, and the control terminal is coupled to the inverting output terminal of the flip-flop FF1. Sample-and-hold circuit 1042 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the first output terminal of isolation circuit 103 to receive the first synchronization signal SYNC1, and the second input terminal is coupled to the first terminal of the first capacitor C1 to receive the voltage across the first capacitor C1. Sample-and-hold circuit 1042 samples and holds the voltage across the first capacitor C1 based on the first synchronization signal SYNC1, and generates a first threshold voltage VTH at the output terminal.

[0048] The peak comparator circuit 105A includes a comparator COM3. The non-inverting input of the comparator COM3 receives the current detection signal VCS, the inverting input receives the first threshold voltage VTH, and the output provides a turn-off control signal RST.

[0049] The turn-on control circuit 108A includes a flip-flop FF2, an AND gate circuit 1081, and a single-trigger circuit 1082. Flip-flop FF2 has a set terminal, a reset terminal, and an output terminal. The set terminal receives the second synchronization signal SYNC2, and the reset terminal is coupled to the output terminal of the primary logic circuit 106A via the single-trigger circuit 1082 to receive the primary control signal CTRP. The AND gate circuit 1081 has a first input terminal and a second input terminal connected to an output terminal. The first input terminal is coupled to the output terminal of flip-flop FF2, and the second input terminal is coupled to the output terminal of the zero-crossing detection circuit 107 to receive the zero-crossing signal SET0, providing the turn-on control signal SET at the output terminal. The primary logic circuit 106A includes a flip-flop FF3. Flip-flop FF3 has a set terminal, a reset terminal, and an output terminal. The set terminal is coupled to the output terminal of the turn-on control circuit 108A to receive the turn-on control signal SET, and the reset terminal is coupled to the output terminal of the peak comparator circuit 105A to receive the turn-off control signal RST, providing the primary control signal CTRLP at the output terminal.

[0050] Figure 7 This is a waveform diagram of an isolated switching converter according to an embodiment of the present invention. Figure 7 As shown, at time t0, the second synchronization signal SYNC2 arrives, and the voltage VC1 across the first capacitor C1 is raised to the upper threshold voltage Vs2, after which the voltage VC1 begins to decrease. At the same time, the second synchronization signal SYNC2 arrives and the resonant voltage of the primary switch 10 reaches its minimum value, and the primary switch 10 is turned on.

[0051] The current flowing through the primary switch 10 gradually increases. When the current detection signal VCS reaches the first threshold voltage VTH, for example at time t1, the primary switch 10 is turned off.

[0052] At time t2, the first synchronization signal SYNC1 arrives, sampling and holding the voltage VC1 across the first capacitor C1 to provide the first threshold voltage VTH. Afterwards, voltage VC1 is pulled down to the lower threshold voltage Vs1. At time t4, the second synchronization signal SYNC2 arrives and the resonant voltage of the primary switch 10 reaches its minimum value, turning the primary switch 10 back on. This process repeats continuously, as follows... Figure 7 As shown, as the load increases, the frequency of the first synchronization signal SYNC1 increases, and the first threshold voltage VTH also increases accordingly.

[0053] Figure 8 This is a waveform diagram of an isolated switching converter according to another embodiment of the present invention. Figure 8 In the illustrated embodiment, at time t0, the second synchronization signal SYNC2 arrives, and the voltage VC1 is pulled high until the upper threshold voltage Vs2. After that, the voltage VC1 begins to decrease.

[0054] At time t1, the second synchronization signal SYNC2 arrives and the resonant voltage of the primary switch reaches its minimum value, and the primary switch 10 is turned on.

[0055] At time t2, the current detection signal VCS reaches the first threshold voltage VTH, and the primary switch 10 is turned off.

[0056] At time t3, the first synchronization signal SYNC1 arrives, sampling and holding the voltage VC1 to provide the first threshold voltage VTH. This process repeats continuously. Figure 8 As shown, as the load decreases, the first threshold voltage VTH also decreases.

[0057] Figure 9 This is a flowchart of a control method 700 for a quasi-resonant controlled isolated switching converter according to an embodiment of the present invention. The switching converter includes a transformer having a primary winding and a secondary winding, a primary switch coupled to the primary winding, a secondary switch coupled to the secondary winding, and an isolation circuit. The control method includes steps 701 to 707.

[0058] In step 701, the output signal of the sampling switch converter is sampled to provide an output feedback signal.

[0059] In step 702, a first compensation signal is generated based on the difference between the output feedback signal and the reference voltage.

[0060] In step 703, a first control signal and a second control signal are generated based on the first compensation signal. In one embodiment, the method for generating the first control signal includes: generating a second compensation signal based on the first compensation signal; comparing the second compensation signal with a modulation signal to provide a first comparison signal; and providing the first control signal based on the first comparison signal. In a further embodiment, the method for generating the second control signal includes: comparing the first compensation signal with the modulation signal to generate a second comparison signal; and generating a target valley value for primary switch conduction based on the first comparison signal, the second comparison signal, and a valley pulse signal characterizing the valley of the voltage across the secondary switch, and providing a second control signal corresponding to the target valley value.

[0061] In step 704, the first control signal is sent to the first channel of the isolation circuit to generate a first synchronization signal that is electrically isolated from the first control signal. In step 705, the second control signal is sent to the second channel of the isolation circuit to generate a second synchronization signal that is electrically isolated from the second control signal.

[0062] In step 706, a first threshold voltage is generated based on the first synchronization signal to control the peak current flowing through the primary switch. In one embodiment, when the rising edge of the second synchronization signal arrives, the voltage across the first capacitor is set high to the upper threshold voltage. Afterward, the voltage across the first capacitor begins to decrease, and the voltage across the first capacitor is sampled and held when the first synchronization signal arrives to provide the first threshold voltage.

[0063] In step 707, based on the second synchronization signal, a turn-on control signal for the primary switch is generated to control the operating frequency of the primary switch. In one embodiment, step 707 further includes: when the second synchronization signal arrives and the resonant voltage across the primary switch reaches its minimum value, controlling the primary switch to turn on.

[0064] In the specification, terms such as "first" and "second" may be used merely to distinguish one entity or action from another, and do not necessarily imply any relationship or order between these entities or actions. Numerical orders such as "first," "second," and "third" refer only to different individuals among a plurality and do not imply any order or sequence, unless specifically defined in the language of the claims. The order of the text in any claim does not imply that the processing steps must be performed in a provisional or logical order according to such order, unless specifically specified in the language of the claims. Without departing from the scope of the invention, these processing steps may be interchanged in any order, provided that such interchange does not contradict the language of the claims and does not result in logical absurdity.

[0065] The above description and embodiments are merely exemplary and are not intended to limit the scope of the invention. Variations and modifications to the disclosed embodiments are possible, and other feasible alternative embodiments and equivalent variations of elements in the embodiments can be understood by those skilled in the art. Other variations and modifications to the embodiments disclosed in this invention do not depart from the spirit and scope of protection of this invention.

Claims

1. A controller for an isolated switching converter, the isolated switching converter including a transformer having a primary winding and a secondary winding, a primary switch coupled to the primary winding, and a secondary switch coupled to the secondary winding, the controller comprising: The error amplifier circuit receives the output feedback signal related to the output signal of the isolated switching converter, and generates a first compensation signal at the output terminal based on the difference between the output feedback signal and the reference voltage. The hysteresis compensation circuit generates a second compensation signal based on the first compensation signal; The first comparison circuit compares the second compensation signal with the same modulation signal and generates a first comparison signal at the output terminal. The first pulse circuit provides a first control signal based on the first comparison signal; The second comparison circuit compares the first compensation signal with the modulation signal to generate a second comparison signal; The valley locking circuit generates a target valley value for the primary switch to turn on at the output terminal based on a first comparison signal, a second comparison signal, and a valley pulse signal that characterizes the valley of the voltage across the secondary switch, and generates a frequency control signal corresponding to the target valley value. The second pulse circuit provides a second control signal based on the frequency control signal; An isolation circuit has a first channel for transmitting a first control signal and a second channel for transmitting a second control signal, provides a first synchronization signal electrically isolated from the first control signal at a first output terminal, and provides a second synchronization signal electrically isolated from the second control signal at a second output terminal; A threshold generation circuit is coupled to the first output terminal of an isolation circuit to receive a first synchronization signal, and provides a first threshold voltage at the output terminal based on the first synchronization signal; The peak comparator circuit compares the current detection signal, which represents the current flowing through the primary switch, with the first threshold voltage and generates a turn-off control signal at the output. as well as The primary logic circuit, based on the second synchronization signal and the turn-off control signal, generates a primary control signal at the output terminal to control the turn-on and turn-off of the primary switching transistor.

2. The controller of claim 1, wherein the modulation signal is pulled up to a peak voltage when the second control signal is active, and then begins to decrease until the second control signal becomes active again.

3. The controller as claimed in claim 1, wherein: The valley locking circuit compares the valley value when the modulation signal reaches the second compensation signal with the current locked valley value, and decides whether to increase the target valley value based on the comparison result. It also compares the valley value when the modulation signal reaches the first compensation signal with the current locked valley value, and decides whether to decrease the target valley value based on the comparison result.

4. The controller of claim 1, wherein the threshold generation circuit includes a first capacitor, wherein when the rising edge of the second synchronization signal arrives, the voltage across the first capacitor is set high to an upper threshold voltage, then the voltage across the first capacitor begins to decrease, and the voltage across the first capacitor is sampled and held when the first synchronization signal arrives to provide a first threshold voltage.

5. The controller of claim 4, wherein the threshold generation circuit comprises: The timing circuit has an input terminal and an output terminal, wherein the input terminal is coupled to the second output terminal of the isolation circuit to receive a second synchronization signal, the timing circuit performs timing based on the second synchronization signal, and generates a timing signal at the output terminal; The first flip-flop has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives a second synchronization signal, and the second input terminal is coupled to the output terminal of the timing circuit to receive a timing signal; The first capacitor has a first terminal and a second terminal, wherein the second terminal is coupled to a primary reference ground; A first voltage source has a positive terminal and a negative terminal, wherein the negative terminal is coupled to the primary reference ground; The second voltage source has a positive terminal and a negative terminal, wherein the negative terminal is coupled to the primary reference ground; The first switching transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the first terminal of the first capacitor, the second terminal is coupled to the positive terminal of the first voltage source, and the control terminal is coupled to the output terminal of the first flip-flop. The second switching transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the first terminal of the first capacitor, the second terminal is coupled to the positive terminal of the second voltage source via a first resistor, and the control terminal is coupled to the inverted output terminal of the first flip-flop. as well as The sample-and-hold circuit has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the first output terminal of the isolation circuit to receive a first synchronization signal, and the second input terminal is coupled to the first terminal of the first capacitor to receive the voltage across the first capacitor. The sample-and-hold circuit samples and holds the voltage across the first capacitor based on the first synchronization signal and generates a first threshold voltage at the output terminal.

6. The controller as described in claim 1, wherein the primary logic circuit controls the primary switch to turn on when the second synchronization signal arrives and the resonant voltage across the primary switch reaches its minimum value.

7. An isolated switching converter, comprising: A transformer has a primary winding and a secondary winding; The primary switching transistor is coupled to the primary winding. The secondary switch is coupled to the secondary winding; as well as The controller as described in any one of claims 1 to 6.

8. A control method for an isolated switching converter, the isolated switching converter comprising a transformer having a primary winding and a secondary winding, a primary switching transistor coupled to the primary winding, a secondary switching transistor coupled to the secondary winding, and an isolation circuit, the control method comprising: An output feedback signal is generated based on the output signal of the isolated switching converter. A first compensation signal is generated based on the difference between the output feedback signal and the reference voltage; Based on the first compensation signal, a second compensation signal is generated; The second compensation signal is compared with a modulation signal to provide a first comparison signal; Based on the first comparison signal, a first control signal is provided; The first compensation signal is compared with the modulation signal to generate a second comparison signal; Based on the first comparison signal, the second comparison signal, and the valley pulse signal characterizing the valley of the voltage across the secondary switch, a target valley value for the primary switch to turn on is generated, and a second control signal corresponding to the target valley value is provided. The first control signal is sent into the first channel of the isolation circuit to generate a first synchronization signal that is electrically isolated from the first control signal. The second control signal is sent into the second channel of the isolation circuit to generate a second synchronization signal that is electrically isolated from the second control signal. Based on the first synchronization signal, a first threshold voltage is generated to control the peak value of the current flowing through the primary switch. as well as Based on the second synchronization signal, a turn-on control signal for the primary switch is generated to control the operating frequency of the primary switch.

9. The control method of claim 8, wherein the method of providing the first threshold voltage comprises: When the rising edge of the second synchronization signal arrives, the voltage across the first capacitor is set high to the upper limit threshold voltage. Then the voltage across the first capacitor began to drop; as well as When the first synchronization signal arrives, the voltage across the first capacitor is sampled and held to provide a first threshold voltage.

10. The control method as described in claim 8, further comprising: When the second synchronization signal arrives and the resonant voltage across the primary switch reaches its minimum value, the primary switch is controlled to turn on.

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