Control circuit of isolated power supply and isolated power supply
By independently controlling the off time of the secondary synchronous rectifier tube and optimizing the opening time of the primary main switch tube with the feedback control loop, the problem of common communication between the main switch tube and the synchronous rectifier tube in the isolated power supply is solved, and efficient and reliable power control is achieved.
Patent Information
- Application Number
- CN202110656105.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-06-11
- Publication Date
- 2025-08-19
- Estimated Expiration
- 2041-06-11
AI Technical Summary
In isolated power supplies, feedback adjustment accuracy loss and performance degradation caused by common problems between the main switch tube and the synchronous rectifier tube, and existing control solutions are difficult to maintain high efficiency and reliability while preventing commonality.
By independently controlling the off time of the secondary synchronous rectifier tube and using it as the basis for determining the opening time of the primary main switch tube, delay processing is avoided, and the opening time of the switch tube is optimized in combination with feedback control loops to prevent the occurrence of common phenomena.
Without affecting feedback response and circuit performance, the main switch tube and the synchronous rectifier tube are effectively prevented from being shared by the main switch tube, improving the reliability and efficiency of the isolated power supply, especially in different working modes, with a flexible anti-passing mechanism.
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Figure CN115473437B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an electronic circuit, and in particular to a control circuit of an isolated power supply and an isolated power supply. Background Art
[0002] With the increasing importance of environmental protection and energy conservation, the demand for power supply efficiency is becoming increasingly stringent. For switching power supplies, replacing traditional freewheeling diodes with synchronous rectifiers is an effective way to improve efficiency. When the power supply is operating in continuous current mode (CCM), controlling the synchronous rectifiers and the main switch simultaneously can lead to a serious risk of device failure, requiring special attention during control circuit design. For non-isolated switching power supplies, synchronous rectifier control can typically be synchronized with the main switch, making design complexity relatively simple. However, for isolated switching power supplies, since the synchronous rectifiers are located on the secondary side and the main switch on the primary side, they have different reference grounds, making control more challenging.
[0003] To prevent commonality, the prior art generally adopts the following two methods to control synchronous rectifiers.
[0004] The first type, independent control, involves turning the secondary synchronous rectifier on and off independently of the primary main switch control logic. The primary switch is typically detected by monitoring the voltage on the secondary winding to determine if it is on. Once the primary switch is on, the secondary synchronous rectifier is turned off. The main advantage of this type of product is its portability, as it doesn't require integration with the primary controller in an isolated switching power supply. However, its main disadvantage is its low reliability. Common current fluctuations can occur even with varying loads and input voltages, and current limiting during these common current fluctuations is often employed to prevent device failure, which in turn reduces efficiency. Furthermore, the synchronous rectification control logic relies on multiple signal detection features, making the detection circuit sensitive and susceptible to interference.
[0005] The second type, synchronous control, transmits the primary-side switch signal to the synchronous rectifier controller on the secondary side. The control signal to the primary-side main switch is delayed by a dead-time before driving the primary-side switch. The synchronous rectifier is turned off by the primary-side main switch control signal, and then the delayed control signal is used to turn on the primary-side main switch. The advantages of this type of product are simple control logic and higher reliability than independent control. The main disadvantage is that the reliability level of preventing common phenomena through delay is not the highest. This method is an open-loop control method, and the shutdown process of the synchronous rectifier takes time. If the delay time is set improperly, common phenomena will still occur. If more reliable anti-common phenomena performance is required, the delay needs to be set very high, which will affect the feedback control accuracy of the power supply. Furthermore, when the power supply system operates in discontinuous current mode, the existence of the zero current interval separates the turn-off moment of the synchronous rectifier from the turn-on moment of the main switch, eliminating the need for a delay to prevent crosstalk. In this case, delaying the control signal of the primary main switch becomes meaningless, hindering the performance of the power supply.
[0006] Therefore, for isolated power supplies, there is an urgent need for a control solution that can reliably solve the common problems of the main switch tube and the synchronous rectifier tube without sacrificing performance. Summary of the Invention
[0007] To solve the problem in the prior art of preventing the loss of feedback regulation accuracy, transient response capability or efficiency when the main switch tube and the synchronous rectifier tube are in common, the present invention proposes a control circuit of an isolated power supply and an isolated power supply.
[0008] One embodiment of the present invention provides a control circuit for an isolated power supply, the control circuit comprising: a secondary control signal generator for receiving a signal of a voltage on a secondary winding of the isolated power supply, generating a secondary switch tube control signal, the secondary switch tube control signal including shutdown time information of a secondary synchronous rectifier tube, the shutdown time information of the secondary synchronous rectifier tube being used to control the shutdown of the secondary synchronous rectifier tube; a primary original turn-on signal generator for receiving a feedback signal of an output voltage of the isolated power supply, generating a primary original turn-on time signal to indicate the turn-on time of the primary switch tube as a time to be turned on; A first turn-on time; a primary-side control signal generator, used to receive the secondary-side switch tube control signal and the primary-side original turn-on time signal to generate a primary-side switch tube control signal to prompt the turn-on time of the primary-side switch tube, wherein the primary-side control signal generator determines a second turn-on time based on the secondary-side switch tube control signal, the second turn-on time is the turn-off time of the secondary-side synchronous rectifier tube, and the primary-side turn-on signal generator further determines the turn-on time of the primary-side switch tube based on the later of the second turn-on time and the first turn-on time to generate the primary-side switch tube control signal.
[0009] Another embodiment of the present invention provides another control circuit of an isolated power supply, the isolated power supply control circuit comprising: a secondary side drive signal generator, for receiving a voltage signal on a secondary winding of the isolated power supply, generating a secondary side switch tube drive signal, the secondary side switch tube drive signal being used to control the turning on and off of the secondary side synchronous rectifier tube; a secondary side switch tube turn-off detector, coupled to the secondary side of the isolated power supply, for generating a turn-off confirmation signal when the secondary side synchronous rectifier tube has been turned off; a primary side original turn-on signal generator, receiving a feedback signal of the output voltage of the isolated power supply, generating a primary side original turn-on time signal to prompt The time when the primary side switch tube should be turned on is used as the first turn-on time; the primary side control signal generator is used to receive the shutdown confirmation signal and the primary side original turn-on time signal to generate a primary side switch tube control signal to prompt the turn-on time of the primary side switch tube, wherein the primary side control signal generator determines the second turn-on time based on the shutdown confirmation signal, and the second turn-on time is the time when it is confirmed that the secondary side synchronous rectifier tube has been turned off. The primary side turn-on signal generator further determines the turn-on time of the primary side switch tube based on the later time of the second turn-on time and the first turn-on time to generate the primary side switch tube control signal.
[0010] Another aspect of the present invention provides an isolated power supply, comprising: an isolated converter having a primary side and a secondary side, wherein the primary side includes a primary switching tube, and the secondary side includes a secondary winding and a synchronous rectifier tube; an isolated power supply control circuit as described in any of the above, used to control the primary switching tube and the synchronous rectifier tube.
[0011] The isolated power supply control circuit proposed in the present invention, the isolated power supply including the control circuit, and the control method can independently determine the shutdown time of the secondary-side synchronous rectifier tube, without relying on the detection of the conduction of the primary-side switch tube. The shutdown time of the secondary-side synchronous rectifier tube is then used as the basis for determining the actual turn-on time of the primary-side main switch tube, thereby achieving the purpose of preventing through-current without delaying the control signal of the primary-side main switch tube. In an environment without a shoot-through risk, the primary main switch can select the turn-on time under the feedback control operation of the control feedback loop of the primary switch in the control circuit to determine the actual turn-on time of the primary main switch without any additional delay processing, so that the feedback response and circuit performance are not affected by the anti-shoot-through design. At the same time, when the isolated power supply operates under conditions where a shoot-through risk exists, the primary main switch can only be turned on after the secondary synchronous rectifier tube is turned off when there is a confirmed shoot-through risk. This not only eliminates the possibility of shoot-through, but also because the control circuit only intervenes and corrects the turn-on time of the primary main switch in a relatively precise manner in individual cycles where a high shoot-through risk is determined, the impact on the feedback response performance is also kept to a minimum. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] In all the following drawings, the same reference numerals indicate elements having the same, similar or corresponding features or functions.
[0013] Figure 1 FIG2 shows a schematic structural diagram of a control circuit 101 according to an embodiment of the present invention;
[0014] Figure 2 shows a structural schematic diagram of a control circuit 101 according to another embodiment of the present invention;
[0015] Figure 3 A schematic block diagram of the structure of the primary side original opening signal generator 103 according to an embodiment of the present invention is shown;
[0016] Figure 4A FIG. 2 shows a schematic diagram of the specific structure of the primary side original opening signal generator 103 according to another embodiment of the present invention;
[0017] Figure 4B Shows the basis Figure 4A A schematic diagram of the specific structure of the oscillator 402 in the illustrated embodiment;
[0018] 5A to 5D A schematic diagram showing the specific structure of the primary side control signal generator 105 according to an embodiment of the present invention is shown;
[0019] Figure 6A and Figure 6B Shown according to 5A to 5D The working waveform diagram of the embodiment shown;
[0020] Figure 7 FIG2 shows a schematic structural diagram of a secondary side control signal generator 102 according to an embodiment of the present invention;
[0021] Figure 8 FIG2 shows a structural diagram of a secondary side control signal generator 102 according to another embodiment of the present invention;
[0022] Figure 9 FIG2 shows a structural diagram of a secondary side control signal generator 102 according to another embodiment of the present invention;
[0023] Figure 10 FIG2 shows a structural diagram of a secondary side control signal generator 102 according to another embodiment of the present invention;
[0024] Figure 11 A schematic diagram of the specific structure of an isolated power supply control circuit 101 according to another embodiment of the present invention is shown;
[0025] Figure 12AFIG2 shows a schematic structural diagram of a secondary side switch turn-off detector 1101 according to an embodiment of the present invention;
[0026] Figure 12B FIG. 1 is a structural diagram of a secondary-side switch turn-off detector 1101 according to another embodiment of the present invention. DETAILED DESCRIPTION
[0027] Specific embodiments of the present invention will be described in detail below. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the present invention. In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that these specific details are not necessarily required to practice the present invention. In other instances, well-known circuits, materials, or methods are not described in detail to avoid obscuring the present invention.
[0028] Throughout this specification, references to "one embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the present invention. Therefore, appearances of the phrases "in one embodiment," "in an embodiment," "an example," or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combinations and / or subcombinations in one or more embodiments or examples. Furthermore, those skilled in the art will appreciate that the figures provided herein are for illustrative purposes only and are not necessarily drawn to scale. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements present. "Instant" refers to a specific point in time, and "time," such as "on-time" or "off-time," refers to a specific time period. Identical reference numerals indicate identical elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0029] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element discussed below can be referred to as the second element without departing from the teachings of the present invention. As used herein, the term "and / or" includes any one of the associated listed items and all combinations of one or more of them.
[0030] Figure 1 FIG. 1 shows a schematic structural diagram of a control circuit 101 according to an embodiment of the present invention. Figure 1As shown, the isolated power supply system adopts a flyback power supply topology, including a primary side and a secondary side, wherein the primary side includes a rectifier bridge RB, and the input end of the rectifier bridge RB is coupled to an external AC power supply. In the illustrated embodiment, the primary side further includes the primary winding P1 of the isolation transformer T1 and the primary switch tube Q1. The secondary side includes the secondary winding S1 of the isolation transformer T1 and the synchronous rectifier tube SR. Furthermore, the isolated power supply system 100 may also include an input capacitor Cin, an absorption circuit CR, an output filter capacitor Cout, and a load 107 on the secondary side. Since the basic topology of the flyback power supply is well known to those skilled in the art, it will not be described in detail here.
[0031] Below Figure 1 Taking the flyback topology shown in FIG. 1 as an example, the isolated power supply control circuit 101 for controlling the isolated power supply system 100 is described. It should be noted that, although Figure 1 The power supply shown is a flyback topology, but the power supply system using the isolated power supply control circuit 101 is not limited to the flyback topology. Ordinary technicians in this field can understand that any isolated power supply topology with common risks between the main switch tube and the synchronous rectifier tube, such as single-ended forward, dual-tube forward, active clamp forward, resonant half-bridge LLC, resonant full-bridge LLC, phase-shifted full-bridge, etc., can be adapted to the isolated power supply control circuit 101 shown in the embodiment of the present invention.
[0032] like Figure 1As shown, the control circuit 101 of the isolated power supply receives a feedback signal VFB of the output voltage Vout of the isolated power supply 100 and derives the desired turn-on time K1 of the primary switch Q1 based on the output voltage feedback signal VFB. It also receives a voltage signal V_Forw on the secondary winding S1 of the isolated power supply 100 and derives the desired turn-off time K2 of the secondary synchronous rectifier SR based on the secondary winding voltage signal V_Forw. Here and in this application, the "desired turn-on time of the primary switch" refers to the time at which the primary main switch Q1 should be turned on, derived solely based on the design principles of the feedback control loop of the isolated power supply 100 using the output voltage feedback signal VFB and other possible feedback parameters, such as the output current feedback signal, as well as an internal clock signal and / or feedback loop compensation. "Determining the desired turn-on time K1 of the primary switch Q1" may involve directly including information about the desired turn-on time K1 in a generated signal, or may involve performing a specific operation on the time information contained in the signal, such as adding or subtracting a specific time offset, to derive the desired turn-on time K1. The "voltage on the secondary winding" is the voltage at the non-fixed potential end of the secondary winding, that is, the voltage at the common connection end of the synchronous rectifier switch tube SR and the secondary winding S1. The term "voltage signal on the secondary winding" is defined as a signal that can characterize the voltage on the secondary winding, for example, the signal formed by the voltage on the secondary winding after passing through a voltage divider, or the signal directly sampled from the non-fixed potential end of the secondary winding. Moments K1 and K2 are for each switching duty cycle, and multiple moments K1 and K2 will be generated in multiple switching duty cycles. Figure 1 In the embodiment shown, the synchronous rectifier SR is connected between the secondary winding S1 and the secondary ground SGND. At this time, the same-name terminal of the secondary winding directly provides the output voltage VOUT. VOUT does not change in steady state, so it is a fixed potential terminal. The opposite-name terminal of the secondary winding is connected to the synchronous rectifier SR. The voltage on the opposite-name terminal is the voltage on the secondary winding. In other embodiments, the synchronous rectifier SR can also be connected to Figure 1 The secondary winding shown is connected to the output terminal of the isolated power supply 100 . At this time, the voltage on the same-named terminals is the voltage on the secondary winding.
[0033] The control circuit 101 of the isolated power supply further includes a primary control signal generator 105, which is located on the primary side. The primary control signal generator 105 further obtains the actual turn-on time of the primary switch Q1 and generates a primary switch control signal PSG based on the turn-on time K1 of the primary switch Q1 and the turn-off time K2 of the secondary synchronous rectifier. When the turn-on time K1 of the primary switch Q1 is later than the turn-off time K2 of the secondary synchronous rectifier, the actual turn-on time of the primary switch Q1 corresponds to the turn-on time K1. When the turn-on time K1 of the primary switch Q1 is earlier than the turn-off time K2 of the secondary synchronous rectifier, the actual turn-on time of the primary switch Q1 is delayed to no earlier than the turn-off time K2 of the secondary synchronous rectifier.
[0034] The control circuit 101 independently determines the turn-off time K2 of the secondary-side synchronous rectifier tube, without relying on the detection of the conduction of the primary-side switch tube. The turn-off time K2 of the secondary-side synchronous rectifier tube is then used as the basis for determining the actual turn-on time of the primary-side main switch tube, thereby preventing the penetration of the primary main switch tube without delaying the control signal of the primary main switch tube. In an environment without shoot-through risk, such as when the isolated power supply operates in a discontinuous inductor current (DCM) mode or a steady-state continuous inductor current (CCM) mode, the primary switch Q1 can select the turn-on time K1 based on the feedback control operation of the primary switch control feedback loop within the control circuit 101 to determine the actual turn-on time of the primary main switch without any additional delay. This ensures that the feedback response and circuit performance are not affected by the anti-shoot-through design. Furthermore, in conditions where the isolated power supply operates with shoot-through risk, such as when a sudden load change occurs in the continuous inductor current (CCM) mode, the primary switch Q1 can be turned on only after the secondary synchronous rectifier is turned off when there is a confirmed shoot-through risk. This not only eliminates the possibility of shoot-through, but also minimizes the impact on feedback response performance because the control circuit only intervenes and adjusts the turn-on time of the primary switch in a more precise manner when a high shoot-through risk is determined.
[0035] In the illustrated embodiment, the isolated power supply control circuit 101 is partially connected to the secondary side of the isolated power supply 100 , and is partially connected to the primary side of the isolated power supply 100 .
[0036] In one embodiment, the primary switch control signal PSG can be a level signal, for example, a rising edge can prompt the turning on of the primary main switch. Furthermore, the primary switch control signal PSG can also include information about the turning-off time of the primary switch, for example, a falling edge can prompt the turning-off of the primary main switch. Thus, the primary switch control signal PSG includes all information for controlling the turning-on and turning-off of the primary switch Q1, thereby controlling the turning-on and turning-off of the primary switch Q1.
[0037] Similarly, in the illustrated embodiment, the control circuit 101 may further output a secondary synchronous rectifier drive signal SRG for turning the secondary synchronous rectifier SR on and off. The secondary synchronous rectifier drive signal SRG may be generated based on the secondary winding voltage signal V_Forw. The specific method and circuit structure for controlling the secondary synchronous rectifier SR will be further described below.
[0038] In the illustrated embodiment, the isolated power supply 100 further includes a sensing circuit 106. The primary-side control signal generator 105 receives the primary-side original turn-on time signal PSC and the secondary-side control signal SRoff, and generates the primary-side switch drive signal PSG based on the primary-side switch turn-on time information contained in the primary-side original turn-on time signal and the secondary-side switch turn-off time information contained in the secondary-side control signal. When the primary-side original turn-on time signal PSC also includes the primary-side switch turn-off time information, the primary-side control signal generator 105 can directly use the primary-side original turn-on time signal PSC to generate the primary-side switch drive signal PSG. When the primary-side original turn-on time signal PSC only includes the primary-side switch turn-on time information, the primary-side control signal generator 105 can combine other appropriate feedback signals, such as a signal detecting the primary-side switch current or a signal detecting the demagnetization of the primary-side switch drain, to determine the primary-side switch turn-off time. For those skilled in the art, the design can be carried out according to specific requirements and feedback characteristics to use appropriate signals to determine the turn-off moment of the primary-side switch tube, and the present invention does not impose any limitation on this.
[0039] Sensing circuit 106 is used to sense the output voltage VOUT on the secondary side and generate a feedback signal VFB. In the illustrated embodiment, sensing circuit 106 may be located outside of control circuit 101 and comprised of discrete components. In other embodiments, sensing circuit 106 may be integrated with control circuit 101 within a single die or chip. Common sensing circuits 106 may include, for example, a resistor divider, which is well known to those skilled in the art and will not be further described.
[0040] like Figure 1As shown, the control circuit 101 further includes a secondary-side control signal generator 102 for receiving a signal V_Forw representing the voltage on the secondary winding of the isolated power supply and generating a secondary-side switch control signal SRoff. The secondary-side switch control signal SRoff includes information about the turn-off time K2 of the secondary-side synchronous rectifier SR. The information about the turn-off time K2 of the secondary-side synchronous rectifier SR is used to control the turn-off of the secondary-side synchronous rectifier SR. Those skilled in the art will appreciate that the secondary-side switch control signal SRoff is not necessarily used to drive the secondary-side synchronous rectifier SR. In some embodiments, the secondary-side switch control signal SRoff can directly serve as the drive signal SRG of the secondary-side synchronous rectifier SR, acting on the gate of the secondary-side synchronous rectifier SR to turn it off. In other embodiments, SRoff can also serve as an intermediate signal, indirectly used to generate the drive signal SRG that ultimately drives the secondary-side synchronous rectifier. In yet other embodiments, SRoff may not directly or indirectly generate the drive signal that ultimately drives the secondary-side synchronous rectifier. In these embodiments, SRoff may share a common source signal with the drive signal SRG that ultimately drives the secondary-side synchronous rectifier. This source signal includes information about the turn-off time K2 of the secondary-side synchronous rectifier SR or all parameters that can be used to calculate the turn-off time K2 of the secondary-side synchronous rectifier SR. When SRoff is generated before SRG, the turn-off time K2 of the synchronous rectifier indicated by SRoff is a theoretical turn-off time, which may be slightly earlier than the actual turn-off time of the secondary-side synchronous rectifier. However, regardless of the relationship between the secondary-side switch control signal SRoff and the drive signal SRG that ultimately drives the secondary-side synchronous rectifier, as long as SRoff includes information about the turn-off time K2 of the secondary-side synchronous rectifier, the objectives of the present invention can be achieved.
[0041] The secondary-side control signal generator 102 can employ any common independent control method known in the art to set the shutdown of the synchronous rectifier SR based on the received signal V_Forw representing the voltage on the secondary winding of the isolated power supply. This allows the shutdown of the secondary-side control signal generator 102 to be independent of the conduction detection of the primary-side switch Q1. As discussed in the background art, those skilled in the art can generally select appropriate schemes and parameters based on existing techniques so that, when operating in steady state, the secondary-side control signal generator 102 can substantially prevent the synchronous rectifier SR and the primary-side switch Q1 from conducting together, without requiring additional anti-shootthrough or anti-flash measures. Furthermore, when the isolated power supply 100 operates in discontinuous inductor current mode, the secondary-side control signal generator 102 can shut off the synchronous rectifier SR after the inductor current returns to zero, thereby preventing post-zero oscillation caused by the continued conduction of the synchronous rectifier SR. However, this design is not sufficient to effectively prevent shootthrough and flash. The secondary-side control signal generator 102 will be described in more detail below.
[0042] The control circuit 101 further includes a primary-side original turn-on signal generator 103, which receives the feedback signal VFB of the isolated power supply's output voltage to generate a primary-side original turn-on time signal PSC to indicate the turn-on time of the primary-side switch. The primary-side control signal generator 105 determines a second turn-on time K2 based on the secondary-side switch control signal SRoff. The second turn-on time K2 is defined as the turn-off time K2 of the secondary-side synchronous rectifier. The primary-side control signal generator 105 also determines a first turn-on time K1 based on the primary-side original turn-on time signal PSC. The first turn-on time K1 is defined as the expected turn-on time of the primary-side switch. The primary-side control signal generator 105 further determines the actual turn-on time of the primary-side switch based on the later of the second turn-on time K2 and the first turn-on time K1 to generate the primary-side switch control signal PSG.
[0043] It should also be noted that, in theory, the second turn-on moment is exactly the same as the turn-off moment of the secondary-side synchronous rectifier tube indicated when the SRoff signal is generated, that is, both are time K2. However, in actual applications, SRoff may be delayed in the process of being transmitted from the secondary-side control signal generator 102 to the primary-side control signal generator 105 for comparison between the first turn-on moment and the second turn-on moment due to actual design and routing requirements. As a result, there may be a slight difference between the second turn-on moment used for comparison and the turn-off moment of the secondary-side synchronous rectifier tube indicated when the SRoff signal is generated. Since this delay is relatively small and can be ignored, in this case, the second turn-on moment is still considered to be the turn-off moment of the secondary-side synchronous rectifier tube.
[0044] In such Figure 2 In another embodiment shown, the secondary-side control signal generator 102 is a secondary-side controller, which is integrally connected to the secondary side. The control circuit 101 further includes a secondary-side switch control signal transmitter 108, which is configured to receive the secondary-side switch control signal SRoff and modulate the secondary-side switch control signal to transmit it from the secondary side to the primary side. Specifically, the secondary-side switch control signal transmitter 108 can transmit the secondary-side switch control signal SRoff using any common primary-to-secondary isolation communication method, such as optical coupling, magnetic coupling, or capacitive coupling transmission, or using on-off keying (OOK) technology to modulate and generate pulses.
[0045] Further Figure 2As shown, the control circuit 101 also includes a primary side original opening signal transmitter 104 for receiving the primary side original opening moment signal PSC, and modulating the primary side original opening moment signal and sending it from the secondary side to the primary side. Specifically, the primary side original opening signal transmitter 104 can adopt any common primary-secondary side isolation communication method, such as optical coupling, magnetic coupling or capacitive coupling transmission, or adopt on-off keying (OOK) technology to modulate and generate pulses to send the primary side original opening moment signal PSC. In addition, the primary side original opening signal generator can be connected to the secondary side as a whole, or part of the circuit can be connected to the secondary side and part of the circuit can be connected to the primary side.
[0046] Figure 3 The following is a schematic diagram illustrating the specific structure of a primary-side original turn-on signal generator 103 according to an embodiment of the present invention. The primary-side original turn-on signal generator uses a constant on-time (COT) feedback control method to control the primary-side switch. Specifically, the primary-side original turn-on signal generator 103 may include a first comparison module CMP1. The first comparison module CMP1 compares the feedback signal VFB of the isolated power supply output voltage with a first reference value Vref1. When the feedback signal VFB of the isolated power supply output voltage drops to the first reference value Vref1, the comparison signal PSO is generated, indicating that the time should be used as the turn-on time of the primary-side main switch. The comparison signal PSO can also be directly used as the primary-side original turn-on time signal PSC.
[0047] In other implementations, such as Figure 3 In the embodiment shown, the comparison signal PSO is used as the basis for the primary side original opening time signal PSC. Figure 3 As shown, the primary side original opening signal generator further includes: a first trigger RS1, having a set terminal S, a reset terminal R and an output terminal Q, wherein the set terminal S receives the comparison signal PSO, and the output terminal outputs the primary side original opening time signal PSC.
[0048] Figure 3 The embodiment shown further includes a primary conduction time timer Timer1, the output end of which is connected to the reset end R of the first trigger RS1, starts timing according to the comparison signal information, and outputs a reset signal to the reset end R of the first trigger RS1 after a preset time Tonp. Tonp can be used as the conduction time of the primary switch tube. It should be noted that the preset time measured by the timer of the present invention can be a fixed value or a variable value. Here, any signal containing the turn-on time information of the primary switch tube can be used to trigger the primary conduction time timer Timer1 to start timing. For example, the primary conduction time timer Timer1 can be as follows Figure 3 As in the embodiment shown, the PSC is directly received at the input end to obtain the turn-on time information of the primary side switch tube.
[0049] although Figure 3 The embodiment shown uses a constant on-time feedback control method, but those skilled in the art will appreciate that the primary side original turn-on signal generator 103 can use any feedback control method in the prior art that is suitable for controlling the primary side main switch based on the output voltage feedback signal VFB, and is not limited to constant on-time control. For example, Figure 4A FIG. 1 shows a schematic structural diagram of a primary side original opening signal generator 103 according to another embodiment of the present invention. Figure 4A As shown, in the primary side original turn-on signal generator 103, the primary side switch is controlled by a feedback control method based on the average value of the output voltage. Specifically, Figure 4A The primary-side original turn-on signal generator 103 shown includes a first error amplifier 401 and an oscillator 402. The first error amplifier 401 performs error amplification processing on the feedback signal VFB of the isolated power supply's output voltage and a second reference value VREF2, outputting an amplified error signal EA. The oscillator 402 receives the amplified error signal EA and generates a square wave signal as the primary-side switch control signal PSC. The frequency of the square wave signal is determined by the amplified error signal EA. The rising or falling edge of the square wave signal indicates the turn-on time of the primary-side switch. The oscillator 402 determines the arrival of an edge of the square wave signal based on the current frequency set by the EA.
[0050] Figure 4B Shows the basis Figure 4A Schematic diagram of the structure of the oscillator 402 of the embodiment shown. The oscillator 402 includes: a frequency setting current source 421, which generates a frequency setting current IFREQ according to the error amplification signal EA; a frequency setting capacitor C1, the first end of which receives the frequency setting current IFREQ, and the second end of which is connected to the reference ground SGND; a discharge branch 422, which in the embodiment shown includes a discharge control switch Q3 and a discharge resistor R1 connected in series, connected to both ends of the frequency setting capacitor C1; a second comparator CMP2, which has two input ends and one output end, one of which is connected to the first end of the frequency setting capacitor C1, and the other input receives a first reference value voltage Vth, and the output end outputs a signal POC, and POC controls the discharge control switch Q3. In some embodiments, the output signal POC can be used as the primary side original opening time signal PSC. As shown in FIG. Figure 4B In the illustrated embodiment, the oscillator may further include a timer 423 for adjusting the on-time of the signal POC to generate a primary side original on-time signal PSC, ultimately affecting the on-time of the primary side switch tube.
[0051] The discharge branch 422 is not limited to the structure of the discharge control switch Q3 and the discharge resistor R1 connected in series in the illustrated embodiment. For example, in other embodiments, a discharge current source can be used instead of the discharge resistor R1. The discharge branch starts or stops discharging by controlling the signal POC, so that the discharge branch 422 and the frequency setting capacitor C1 can form a discharge circuit with a capacitance time constant. In some embodiments, the capacitance time constant can be adjusted by adjusting the resistance value of R1 or adjusting the current size of the discharge current source, so that the discharge branch 422 can obtain different discharge times according to different needs, and ultimately affect the conduction time of the primary side switch tube corresponding to the primary side original turn-on time signal PSC. It should be noted that in some embodiments, the primary side original turn-on signal generator 103 can be a secondary side controller of the isolated power supply, connected to the secondary side of the isolated power supply. In other embodiments, the primary side original turn-on signal generator 103 can be partially connected to the secondary side of the isolated power supply and partially connected to the primary side of the isolated power supply, for example Figure 3 The first trigger RS1 and the primary side conduction time timer Timer1 in FIG4 can be connected to the primary side of the isolated power supply. For example, the first error amplifier 401 in FIG4 can be connected to the secondary side of the isolated power supply, and the oscillator 402 can be connected to the primary side of the isolated power supply. The error amplified signal EA or the comparison signal PSO can be Figure 2 The primary side original activation signal transmitter 104 is modulated and sent from the secondary side to the primary side.
[0052] Figure 5A FIG. 1 shows a schematic structural diagram of a primary side control signal generator 105 according to an embodiment of the present invention. Figure 5A As shown, the primary-side control signal generator 105 may include an anti-punch-through logic circuit. The anti-punch-through logic circuit receives the primary-side original turn-on signal PSC and the secondary-side switch control signal SRoff (generating the second turn-on time K2). When the first turn-on time K1 is earlier than the second turn-on time K2, the anti-punch-through logic circuit generates the primary-side switch control signal based on the secondary-side switch control signal SRoff, so that the turn-on time of the primary-side switch in the current cycle is no earlier than the second turn-on time.
[0053] exist Figure 5AIn the illustrated embodiment, the secondary switch control signal is a level signal. In this case, the punch-through prevention logic circuit includes a first logic gate that receives PSC and SRoff. When the primary switch original turn-on timing signal PSC indicates that the primary switch Q1 should be turned on, and the secondary switch control signal SRoff indicates that the secondary synchronous rectifier SR has reached its turn-off timing K2, the output terminal outputs a primary switch turn-on timing signal PON to indicate the arrival of the primary switch turn-on timing. In the illustrated embodiment, the first logic gate is a first AND gate AND1, having two inputs and one output. The first input terminal receives the primary switch original turn-on timing signal PSC, and the second input terminal receives the inverted signal of the secondary switch control signal SRoff. The output terminal outputs a primary switch turn-on timing signal PON, which also includes information about the turn-off timing of the primary switch Q1. In some embodiments, the primary switch turn-on timing signal PON can directly serve as the primary switch control signal PSG.
[0054] In other implementations, such as Figure 5B In the embodiment shown, the primary switch tube turn-on time signal PON is used as the basis for generating the primary switch tube control signal PSG. Figure 5B As shown, the primary side control signal generator further includes: a second trigger RS2, having a set terminal S, a reset terminal R and an output terminal Q, wherein the set terminal S receives the turn-on time signal PON of the primary side switch tube, and the output terminal outputs the primary side switch tube control signal PSG.
[0055] Figure 5B The embodiment shown further includes a third comparison module that compares the current Ip flowing through the primary switch tube with a third reference value Ilimit. The output end of the third comparison module is connected to the reset end R of the second flip-flop RS2. When the current flowing through the primary switch tube rises to the third reference value Ilimit, a reset signal is output to the reset end R of the second flip-flop. Figure 5BThe illustrated embodiment includes a third comparator CMP3, which has two inputs and one output. One input receives the current (primary current) Ip flowing through the primary switch, and the other receives a third reference value Ilimit. The output is connected to the reset terminal R of the second flip-flop RS2. When the current flowing through the primary switch reaches the third reference value Ilimit, the comparator outputs a reset signal to the reset terminal R of the second flip-flop RS2. The primary switch control signal PSG is triggered based on the turn-on timing of the primary switch. After a time Tonp, the current flowing through the primary switch reaches the third reference value Ilimit, and a reset signal is output to the reset terminal R of the second flip-flop RS2. Tonp can be used as the conduction time of the primary switch, that is, the conduction time of the primary switch is obtained by detecting the peak current of Q1. Here, the reset signal can also be provided by a timer. Any signal containing the turn-on time information of the primary-side switch tube can be used to trigger the timer to start timing. After a preset time, the timer outputs a bit signal to the reset terminal R. The turn-on time of the primary-side switch tube is the preset time. The preset time can be a fixed value or a variable value. In addition, in some embodiments, both the third comparison module and the timer can be included, and the preset time or time Tonp is selected as the turn-on time of the primary-side switch tube.
[0056] Figure 5C FIG. 1 shows a schematic diagram of the specific structure of the primary side control signal generator 105 according to another embodiment of the present invention. Figure 5A The embodiment shown, Figure 5C The illustrated embodiment differs in that the secondary-side switch control signal SRoff is a pulse signal. In this case, the anti-punch-through logic circuit further includes a first latch, Latch1, which receives and latches the secondary-side switch control signal SRoff and outputs a latch signal SRL. In the illustrated embodiment, latch Latch1 is an RS flip-flop. Accordingly, the two inputs of a first AND gate AND1, implemented as a first logic gate, receive the primary-side original turn-on timing signal PSC and the latch signal SRL, respectively. The first AND gate AND1 outputs the primary-side switch turn-on timing signal PON. In some embodiments, the primary-side switch turn-on timing signal PON can be directly used as the primary-side switch control signal PSG.
[0057] Furthermore, the primary-side switch turn-on timing signal PON output by the first AND gate AND1 is further provided to the first latch Latch1 for resetting the first latch Latch1 based on the turn-on timing information of the primary-side switch. Similarly, the signal for resetting the first latch Latch1 is not limited to the primary-side switch turn-on timing signal PON; any signal containing the turn-on timing information of the primary-side switch will suffice.
[0058] In other implementations, such as Figure 5D In the embodiment shown, the primary switch tube turn-on time signal PON is used as the basis for generating the primary switch tube control signal PSG. Figure 5D As shown, the primary side control signal generator further includes: a second trigger RS2, having a set terminal S, a reset terminal R and an output terminal Q, wherein the set terminal S receives the turn-on time signal PON of the primary side switch tube, and the output terminal outputs the primary side switch tube control signal PSG. Figure 5D The embodiment shown in Figure 5B The difference between the illustrated embodiment and the embodiment shown is that the secondary side switch control signal SRoff is a pulse signal, and other similar structures are not described in detail.
[0059] Figure 6A and Figure 6B Shown according to Figures 5A to 5D The working waveform diagram of the primary side control signal generator 105 in the embodiment shown is not exclusive and is only used as an example to illustrate the working principle of the primary side control signal generator 105. Figure 3 and parts of Figure 4. Figure 6AThe following waveforms illustrate the operation of the isolated power supply 100 in continuous current mode. For ease of description, the primary current Ip and the secondary current Is are combined into a single waveform, collectively referred to as "inductor current." Those skilled in the art will understand that the term "inductor current" in the illustrated embodiment does not refer to the actual current, but rather to the combination of the waveforms of the primary and secondary currents Ip and Is. Furthermore, for ease of explanation, the waveforms herein and below assume that the on-time of the secondary synchronous rectifier can be adjusted with load variations. Before time T1, the average load current is I1, and the isolated power supply 100 is in steady state. Operating conditions are ideal. Relying solely on the constant on-time feedback loop design of the primary switch, the appropriate dead time Tdead is established between the primary switch Q1 and the synchronous rectifier SR to prevent crosstalk. At this point, when the feedback signal VFB falls below the first reference voltage Vref1, causing PSC to be high, the synchronous rectifier is already turned off, SRoff is low, and the inverted output of the first AND gate AND1 is high, setting the second flip-flop RS2. The second trigger RS2 outputs PSG at a high level, signaling the primary switch to turn on. The inductor current increases, and VFB rises accordingly. When the current flowing through the primary switch reaches the third reference value Ilimit or the timer expires, the second trigger RS2 is reset, PSG goes low, and turns off. The synchronous rectifier SR turns on and begins freewheeling, causing the inductor current to decrease, and VFB to decrease accordingly. Throughout this process, SRoff does not affect the turn-on timing of the primary switch. The theoretical turn-on timing of the primary switch is K1, and the actual turn-on timing of the primary switch is determined solely by the inherent delay caused by the PSC transmission to form PSG, which causes the primary main switch to turn on. No additional delay is added, resulting in excellent feedback performance. When time T1 arrives, the average load current jumps from I1 to I2, and the isolated power supply 100 enters the transient response phase. As the load current increases, VFB drops rapidly to the VREF1 level, and PSC jumps to high. However, at this time, the secondary-side synchronous rectifier SR has not yet turned off under independent control, and SRoff is still high, with the inverted phase at a low level. At this time, the first AND gate AND1 outputs a low level. Until the synchronous rectifier reaches the turn-off moment, SRoff becomes low, and the first AND gate AND1 outputs a high level, causing PSG to jump to a high level, turning on the primary-side switch tube and preventing possible punch-through problems. When the transient response ends at time T2 and the steady state is re-established, the primary-side control signal generator returns to the state before time T1, and SRoff no longer has a practical impact on PSG.
[0060] Figure 6BThe following waveforms illustrate the operating waveforms of the isolated power supply 100 operating in discontinuous current mode. In discontinuous inductor current mode, the synchronous rectifier SR turns off after the inductor current returns to zero to prevent oscillation, and SRoff simultaneously decreases. Therefore, regardless of whether the isolated power supply 100 is in steady state or in a transient state due to a load current jump, SRoff will inevitably decrease before VFB drops to VREF1 due to the existence of the zero current interval. Therefore, SRoff has no impact on the generation of PSG in discontinuous current mode, and the theoretical turn-on time of the primary switch is also K1. Thus, in discontinuous inductor current mode, the actual turn-on time of the primary switch is determined solely by the inherent delay in turning on the primary main switch due to the transmission of the PSC to form the PSG, without any additional delay, resulting in excellent feedback performance.
[0061] It should be noted that Figure 6A and Figure 6B The PSC signal conduction time is affected by Figure 3 The timer Timer1 is affected by or / and is affected by Figure 4A and Figure 4B The combined influence of factors such as the oscillator in the middle and whether the oscillator includes a timer. Accordingly, the on-time of the PSG signal Tonp is not only affected by the on-time of the signal PSC, but also by Figures 5A to 5D Due to the influence of the third comparison module or timer, the shutdown time may be consistent with or inconsistent with the shutdown time of the signal PSC. Of course, the on-time of the PSC signal and the on-time of the PSG signal can be generated by other mechanisms in addition to timing or Q1 peak current detection.
[0062] Next, the secondary control signal generator 102 is described. In one embodiment, the secondary control signal generator 102 also employs a constant on-time (COT) control mode. The secondary control signal generator 102 receives a voltage signal V_Forw on the secondary winding. When the voltage signal V_Forw on the secondary winding is equal to a fourth reference value VREF4, the secondary synchronous rectifier is turned on and timing is initiated. After a first estimated time Tson, the secondary switch control signal SRoff is generated to indicate the secondary synchronous rectifier's turn-off time K2. The first estimated time Tson can be a fixed or variable value. In some embodiments, the secondary control signal generator 102 can further determine whether the secondary inductor current has crossed zero, thus entering a zero current interval, based on the voltage signal V_Forw on the secondary winding. Upon entering the zero current interval, the secondary switch control signal SRoff is generated to indicate the secondary synchronous rectifier's turn-off time K2, regardless of whether the first estimated time Tson has elapsed. In this way, SRoff can take into account both CCM and DCM operating conditions. In CCM, the COT mode is used for shutdown, and in DCM, the inductor is shut down in time when the inductor current crosses zero.
[0063] As mentioned above, the secondary side switch tube control signal SRoff can further include the turn-on information of the secondary side synchronous rectifier tube, so that SRoff can be used as the driving signal of the secondary side switch tube, directly used to drive the secondary side synchronous rectifier tube, or generate the driving signal of the secondary side synchronous rectifier tube based on SRoff.
[0064] When the constant on-time (COT) mode is used for control, in one embodiment, the secondary-side synchronous rectifier tube turn-on information included in the secondary-side switch tube control signal SRoff can also be used to prompt the secondary-side synchronous rectifier tube to turn on to start timing.
[0065] Figure 7 FIG. 1 shows a schematic structural diagram of a secondary side control signal generator 102 according to an embodiment of the present invention. Figure 7As shown, the secondary-side control signal generator includes a fourth comparator CMP4, a third flip-flop RS3, and a secondary-side control timer Timer2. The fourth comparator CMP4 has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives the voltage signal V_Forw on the secondary winding, the second input terminal receives the fourth reference value VREF4, and the output terminal outputs a signal CMP_S. The third flip-flop RS3 has a set terminal S, a reset terminal R, and an output terminal Q. The set terminal S of the third flip-flop is connected to the output terminal of the fourth comparator CMP4. The secondary-side control timer Timer2 has a timing start terminal and a timing result output terminal. The timing start terminal begins timing after the secondary-side synchronous rectifier is prompted to turn on. After a first estimated time Tson, the timing result output terminal outputs the timing result to the reset terminal R of the third flip-flop.
[0066] In the illustrated embodiment, the output signal SRP of the output terminal Q of the third flip-flop RS3 is connected to the timing start terminal of the secondary side control timer Timer2 to prompt the secondary side synchronous rectifier to turn on to start timing.
[0067] In another embodiment, the output signal CMP_S of the output terminal of the fourth comparator CMP4 can be used to prompt the secondary-side synchronous rectifier to turn on and start timing. In this case, the output signal CMP_S of the output terminal of the fourth comparator CMP4 is directly connected to the timing start terminal of the secondary-side control timer Timer2.
[0068] As mentioned above, any signal containing secondary-side synchronous rectifier shutdown information can be used as the secondary-side switch control signal SRoff. For example, in one embodiment, the output signal SRP at the output end of the second trigger can be used as the secondary-side switch control signal SRoff.
[0069] In another embodiment, the output signal SRPoff of the secondary-side control timer Timer2 at the timing result output terminal can be used as the secondary-side switch control signal SRoff. In this case, the output signal of the timing result output terminal can be a single pulse signal.
[0070] In the illustrated embodiment, the secondary-side control signal generator 102 further includes a second AND gate AND2 having two inputs and one output, the two inputs being connected to the output of the fourth comparator CMP4 and the output Q of the third flip-flop, respectively. In the illustrated embodiment, the output signal SRC at the output of the second AND gate AND2 serves as the secondary-side switch control signal SRoff. When the isolated power supply operates in CCM mode, after the synchronous rectifier is turned on, V_Forw is approximately equal to the secondary-side ground potential and is always less than VREF4. At this point, the fourth comparator CMP2 outputs a high level to the input of the second AND gate AND2. The output of the second AND gate AND2 is solely dependent on the output Q of the third flip-flop RS3. In other words, the timing result determines the output of the second AND gate AND2. When the isolated power supply operates in DCM mode, if the secondary-side control timer Timer2 has not reached the first estimated time Tson and the inductor current crosses zero, the secondary side will oscillate, causing V_Forw to jump above VREF4. At this time, the fourth comparator CMP4 outputs a low level, causing the output of the second AND gate AND2 to immediately go low, prompting the secondary-side synchronous rectifier to shut down.
[0071] Furthermore, the secondary-side control signal generator 102 can generate a secondary-side synchronous rectifier driving signal SRG. In the illustrated embodiment, SRC=SRG. In other embodiments, SRG can also be indirectly generated by SRC.
[0072] In the illustrated embodiment, in order to make the turn-off time of the secondary-side synchronous rectifier more accurate in steady state, make the dead time close to the optimal time to improve efficiency, and enable the primary-side main switch to be turned on according to the primary-side turn-on time under most load conditions and operating conditions, thereby improving transient response capability, the secondary-side control signal generator 102 further includes a synchronous rectification time prediction circuit 701 for predicting the turn-off time of the synchronous rectifier to variably generate a first estimated time Tson. The output end of the synchronous rectification time prediction circuit 701 outputs information about the first estimated time Tson to the secondary-side control timer Timer2. The first estimated time Tson represents the conduction time of the secondary-side synchronous rectifier. Those skilled in the art will understand that any prediction scheme that can predict the turn-off time of the synchronous rectifier (or predict the turn-off time by predicting the conduction time of the secondary-side synchronous rectifier) can be applied here. Regarding how to predict the turn-off moment of the secondary synchronous rectifier, relevant solutions already exist in the prior art. For example, in the illustrated embodiment, the input end of the synchronous rectification time prediction circuit 701 can receive the voltage signal V_Forw on the secondary winding, and generate a first estimated time Tson based on the voltage signal V_Forw on the secondary winding. After the synchronous rectifier SR is turned on and Tson has passed, the turn-off moment of the synchronous rectifier SR is reached. For example, in other embodiments, Tson can be generated based on the current switching frequency by receiving the CMP_S signal via the time prediction circuit. The specific algorithm will not be repeated here.
[0073] Figure 8 FIG. 1 shows a schematic diagram of the specific structure of the secondary side control signal generator 102 according to another embodiment of the present invention. Figure 2 In the illustrated embodiment, the isolated power supply control circuit 101 further includes a first delay circuit 801, which is configured to delay the shutdown of the secondary synchronous rectifier to reduce the interval between the secondary switch turn-off time and the primary switch turn-on time. The first delay circuit 801 does not delay the secondary switch turn-off time indicated by the secondary switch control signal SRoff. In the illustrated embodiment, the first delay circuit 801 receives the output signal SRC from the output terminal of the second AND gate AND2 and delays it to serve as the secondary synchronous rectifier drive signal SRG. When SRC also serves as the secondary switch control signal SRoff, the secondary switch turn-off time indicated by SRoff is earlier than the actual turn-off time of the secondary switch. This delay can partially offset the delay caused by the generation and transmission of the primary switch control signal PSC to the primary side, which causes the primary main switch to actually turn on, further optimizing the dead time and improving efficiency.
[0074] Those skilled in the art will appreciate that, in other embodiments, the position of the first delay circuit 801 may be different from Figure 8 As shown, as long as the first delay circuit 801 does not delay the turn-off time of the secondary-side switch tube indicated by the secondary-side switch tube control signal SRoff, but only delays the actual turn-off time of the secondary-side synchronous rectifier tube.
[0075] Further, such as Figure 9 As shown, in another embodiment, the delay time of the first delay circuit 801 is adjustable, and the control circuit 101 further includes a transient determination circuit 802. The transient determination circuit 802 determines whether a load jump occurs in the isolated power supply. When the transient determination circuit 802 determines that a load jump occurs, it outputs a transient signal to the first delay circuit to reduce the delay time of the first delay circuit 801.
[0076] In steady-state conditions, the actual turn-on time of the primary main switch is primarily determined by the time at which the primary main switch should be turned on. In this case, the dead time is the difference between the PSC's prompt time and the SRoff's prompt time, plus the delay in the PSC's transmission to the primary side, which ultimately turns on the main switch, minus the delay of the first delay circuit 801. This dead time provides a large safety margin, allowing for more ideal modulation to improve efficiency. However, during a load transition, the primary switch may turn on earlier than in steady-state conditions, with the PSC's prompt time essentially equal to the SRoff's prompt time. Continuing with the steady-state delay parameters at this point could increase the risk of punch-through. However, reducing the delay time of the first delay circuit 801 when determining transient conditions allows for a greater safety margin for transient conditions. Furthermore, since transient conditions occur less frequently than steady-state conditions, efficiency is not excessively compromised.
[0077] Regarding the judgment algorithm of the transient judgment circuit 802, relevant descriptions have been provided in the prior art, and thus will not be repeated here.
[0078] Figure 10 FIG. 1 shows a schematic diagram of a specific structure of a secondary side control signal generator 102 according to another embodiment of the present invention. Figure 9 In the illustrated embodiment, the delay time of the first delay circuit 801 is adjustable, and the control circuit further includes a dead time detection circuit 803. The dead time detection circuit 803 is configured to calculate the dead time of the previous operating cycle and compare the calculated dead time with a dead time reference Tref_D. When the dead time is less than the dead time reference Tref_D, the dead time detection circuit 1303 adjusts to reduce the delay time of the first delay circuit 801. When the dead time is greater than the dead time reference Tref_D, the dead time detection circuit 803 adjusts to increase the delay time of the first delay circuit 801. Thus, the timely response of the dead time detection circuit 803 ensures that the dead time remains within the target range, thereby maximizing efficiency.
[0079] As to how to detect the dead time, there are corresponding design solutions in the prior art, which will not be described in detail in this invention. A person skilled in the art will understand that any method capable of detecting the dead time can be applied to Figure 10 In the embodiment shown, corresponding effects are thereby achieved.
[0080] Figure 11 FIG. 1 is a schematic diagram showing the structure of a control circuit 101 according to another embodiment of the present invention. Figure 11 The control circuit 101 shown is also suitable for application to Figure 1 In order to avoid repeated description, the above description Figures 2 to 10 The relevant embodiments have been described in detail, and those skilled in the art can easily apply them in the same manner. Figure 11 The solutions and technical features in the illustrated embodiments will not be described again, but are still part of the disclosed embodiments of the present invention. Figure 2 The embodiment shown, Figure 11 In the illustrated embodiment, the secondary control signal generator 102 receives a signal V_Forw representing the voltage on the secondary winding of the isolated power supply and generates a signal, a secondary synchronous rectifier drive signal SRG, for controlling the turning on and off of the secondary synchronous rectifier. The control circuit 101 further includes a secondary switch turn-off detector 1101, coupled to the secondary side of the isolated power supply, for generating a turn-off confirmation signal SRD when the secondary synchronous rectifier has turned off. The primary original turn-on signal generator 103 generates a primary original turn-on timing signal PSC based on a feedback signal VFB representing the output voltage of the isolated power supply. The primary control signal generator 105 receives the turn-off confirmation signal SRD and the primary original turn-on timing signal PSC to generate a primary switch control signal PSG indicating the turn-on timing of the primary switch. The primary control signal generator determines a first turn-on timing K1 based on the turn-off confirmation signal SRD and a second turn-on timing K2 based on the primary original turn-on timing signal PSC. The primary-side control signal generator 105 further determines the turn-on time of the primary-side switch based on the later of the second turn-on time K2 and the first turn-on time K1 to generate the primary-side switch control signal PSG.
[0081] Since there may be a long delay between determining the turn-off moment of the secondary-side synchronous rectifier tube and finally generating the drive signal, and there is also a turn-off delay when the drive signal turns off the synchronous rectifier tube, therefore, generating the SRD signal by detecting that the secondary-side synchronous rectifier tube has been turned off to confirm the second turn-on moment K2 has higher reliability than using the SRoff signal to confirm the second turn-on moment K2, and is suitable for occasions requiring particularly high reliability.
[0082] like Figure 12A As shown, in one embodiment, the secondary switch turn-off detector 1101 receives a voltage signal V_Forw on the secondary winding of the isolated power supply and compares it with a first turn-off reference value VREFD1 (corresponding to the voltage value on the secondary winding after the synchronous rectifier is turned on during the freewheeling period) and a second turn-off reference value VREFD2 (corresponding to the voltage value on the secondary winding when the parasitic body diode of the synchronous rectifier is turned on after the synchronous rectifier is turned off). The comparison result is then logically determined through a logic gate (e.g., AND gate AND4) and a turn-off confirmation signal SRD is output. When the voltage signal V_Forw on the secondary winding drops from VREFD1 to VREFD2, it is determined that the secondary synchronous rectifier has been turned off, and the turn-off confirmation signal SRD is generated.
[0083] like Figure 12B As shown, in another embodiment, the secondary side switch tube shutdown detector 1101 includes a current sensing circuit 1221, which receives and outputs a current sensing signal Isen representing the current flowing through the secondary side synchronous rectifier tube SR, and a current zero-crossing edge detection circuit 1222, which receives the current sensing signal Isen. When the current sensing signal Isen indicates that the current on the secondary side synchronous rectifier tube SR has a falling edge and crosses zero, it is determined that the secondary side synchronous rectifier tube SR is turned off and a shutdown confirmation signal SRD is generated.
[0084] Those skilled in the art will appreciate that the method for detecting the shutdown of the secondary synchronous rectifier tube and the structure of the secondary switch tube shutdown detector 1101 are not limited to Figure 12A and 12B The two embodiments described above are exemplary rather than restrictive. In other embodiments, any other circuit suitable for detecting the shutdown of the secondary-side synchronous rectifier tube SR can be used as the secondary-side switch tube shutdown detector 1101 while still being within the scope of the claims of the present invention.
[0085] The above description of the control method and steps according to the embodiments of the present invention is only exemplary and is not intended to limit the present invention. In addition, some well-known control steps and the control parameters used are not given or described in detail to make the present invention clear, concise and easy to understand. Those skilled in the art of the invention should understand that the step numbers used in the above description of the control method and steps according to the various embodiments of the present invention are not intended to indicate the absolute sequence of the steps. These steps are not implemented in the order of the step numbers, but may be implemented in different orders, or may be implemented simultaneously and in parallel, and are not limited to the described embodiments.
[0086] While the present invention has been described with reference to several exemplary embodiments, it should be understood that the terms used are descriptive and illustrative, rather than restrictive. Since the present invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above-described embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope of the appended claims. All changes and modifications that fall within the scope of the claims or their equivalents are intended to be covered by the appended claims.
Claims
1. A control circuit for an isolated power supply, the control circuit comprising: a secondary-side control signal generator, configured to receive a signal indicating the voltage on the secondary winding of the isolated power supply and generate a secondary-side switch control signal, wherein the secondary-side switch control signal includes information indicating when the secondary-side synchronous rectifier is turned off, and the information indicating when the secondary-side synchronous rectifier is turned off is used to control the secondary-side synchronous rectifier to turn off; A primary side original turn-on signal generator receives a feedback signal of the output voltage of the isolated power supply and generates a primary side original turn-on time signal to indicate the turn-on time of the primary side switch tube as the first turn-on time; A primary-side control signal generator is used to receive the secondary-side switch tube control signal and the primary-side original turn-on time signal to generate a primary-side switch tube control signal to indicate the turn-on time of the primary-side switch tube, wherein the primary-side control signal generator determines a second turn-on time based on the secondary-side switch tube control signal, and the second turn-on time is the turn-off time of the secondary-side synchronous rectifier tube. The primary-side control signal generator further determines the turn-on time of the primary-side switch tube based on the later of the second turn-on time and the first turn-on time to generate the primary-side switch tube control signal.
2. The control circuit according to claim 1, wherein: The primary side control signal generator is a primary side controller of the isolated power supply, and is used for connecting to the primary side of the isolated power supply.
3. The control circuit according to claim 1, wherein: The isolated power supply control circuit further includes: a secondary side switch tube control signal transmitter, which is used to receive the secondary side switch tube control signal and modulate the secondary side switch tube control signal and send it from the secondary side to the primary side.
4. The control circuit according to claim 1, wherein: The isolated power supply control circuit further includes: a primary side original turn-on signal transmitter, which is used to receive the primary side original turn-on time signal, and modulate the primary side original turn-on time signal and send it from the secondary side to the primary side.
5. The control circuit according to claim 1, wherein: The primary switch tube control signal further includes the turn-off time information of the primary switch tube to control the turn-off of the primary switch tube.
6. The control circuit according to claim 1, wherein: The primary side original opening signal generator includes: The first comparison module compares the feedback signal of the output voltage of the isolated power supply with a first reference value, and generates the primary side original opening time signal when the feedback signal of the output voltage of the isolated power supply drops to the first reference value.
7. The control circuit according to claim 1, wherein: The primary side original opening signal generator includes: a first comparison module, configured to compare a feedback signal of the output voltage of the isolated power supply with a first reference value, and to generate a comparison signal when the feedback signal of the output voltage of the isolated power supply drops below the first reference value; A first trigger has a set terminal, a reset terminal and an output terminal, wherein the set terminal receives the comparison signal, and the output terminal outputs the original turn-on time signal of the primary side; A primary side on-time timer has an output terminal connected to the reset terminal of the first trigger, starts timing according to the comparison signal, and outputs a reset signal to the reset terminal of the first trigger after a preset time has passed.
8. The control circuit according to claim 1, wherein: The primary side original opening signal generator includes: a first error amplifier, performing error amplification processing on a feedback signal of the output voltage of the isolated power supply and a second reference value, and outputting an error amplified signal; An oscillator receives the error amplified signal and generates a square wave signal as a primary side original turn-on time signal, wherein the frequency of the square wave signal is determined by the error amplified signal, and the rising or falling edge of the square wave signal indicates the turn-on time of the primary side switch tube in the next cycle.
9. The control circuit according to claim 7 or 8, characterized in that: The isolated power supply control circuit further includes: a primary side original start-up signal transmitter, which is used to receive the error amplification signal or the comparison signal, and modulate the error amplification signal or the comparison signal and send it from the secondary side to the primary side.
10. The control circuit according to claim 1, wherein: The primary-side control signal generator includes: an anti-punch-through logic circuit, which receives the primary-side original turn-on time signal and the secondary-side switch tube control signal, and when the second turn-on time is later than the first turn-on time, generates a primary-side switch tube turn-on time signal based on the secondary-side switch tube control signal so that the turn-on time of the primary-side switch tube in the current cycle is not earlier than the second turn-on time.
11. The control circuit according to claim 10, wherein: The secondary-side switch tube control signal is a level signal. The anti-punch-through logic circuit includes: a first logic gate having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives the primary-side original turn-on time signal, the second input terminal receives the inverted signal of the secondary-side switch tube control signal, and the output terminal outputs the primary-side switch tube turn-on time signal to indicate that the primary-side switch tube should be turned on when the primary-side original turn-on time signal indicates that the primary-side switch tube should be turned on and the secondary-side switch tube control signal indicates that the turn-off time of the secondary-side synchronous rectifier tube has arrived.
12. The control circuit according to claim 11, wherein: The primary side control signal generator further comprises: A second trigger has a set terminal, a reset terminal and an output terminal, wherein the set terminal receives the primary switch tube turn-on time signal, and the output terminal outputs the primary switch tube control signal; a third comparison module, which compares the current of the primary switch tube with a third reference value; an output end of the third comparison module is connected to a reset end of the second trigger; and a reset signal is output to the reset end of the second trigger when the current of the primary switch tube rises to the third reference value.
13. The control circuit according to claim 10, wherein: The secondary side switch control signal is a pulse signal, and the anti-punch-through logic circuit includes: A first latch receives and latches the secondary side switch control signal and outputs a latch signal; The first logic gate receives the primary side original turn-on time signal and the latch signal respectively, wherein, when the primary side original turn-on time signal has prompted that the primary side main switch tube should be turned on and the latch signal prompts that the turn-off time of the secondary side synchronous rectifier tube has arrived, the output end outputs the primary side switch tube turn-on time signal to prompt that the turn-on time of the primary side switch tube has arrived.
14. The control circuit according to claim 13, wherein: The primary side control signal generator further comprises: a second flip-flop having a set terminal, a reset terminal, and an output terminal, wherein the set terminal receives the primary switch tube turn-on time signal, the output terminal outputs the primary switch tube control signal, and the primary switch tube control signal is further input into the first latch for resetting the first latch according to the turn-on time information of the primary switch tube; a third comparison module, which compares the current of the primary switch tube with a third reference value; an output end of the third comparison module is connected to a reset end of the second trigger; and a reset signal is output to the reset end of the second trigger when the current of the primary switch tube rises to the third reference value.
15. The control circuit according to claim 10, wherein: The primary side switch tube turn-on time signal is used as the primary side switch tube control signal.
16. The control circuit according to claim 1, wherein: The secondary side control signal generator generates the secondary side switch tube control signal in different ways in the inductor current discontinuous mode and the inductor current continuous mode. In the inductor current discontinuous mode, the secondary side control signal generator generates the secondary side switch tube control signal at the latest when the secondary side enters the zero current interval to prompt the secondary side synchronous rectifier tube to turn off.
17. The control circuit according to claim 1, wherein: The secondary control signal generator receives the voltage signal on the secondary winding. When the voltage signal on the secondary winding is the same as a fourth reference value, the secondary synchronous rectifier is prompted to turn on and start timing. After the first expected time has passed, the secondary switch tube control signal is generated to prompt the shutdown time of the secondary synchronous rectifier.
18. The control circuit according to claim 17, wherein: In the discontinuous inductor current mode, the secondary side control signal generator further determines whether the secondary side enters the zero current interval based on the voltage signal on the secondary winding. When the secondary side enters the zero current interval, regardless of whether the first estimated time is completed, the secondary side switch tube control signal is generated to prompt the shutdown moment of the secondary side synchronous rectifier tube.
19. The control circuit according to claim 17, wherein: The secondary side switch tube control signal is also used to prompt the secondary side synchronous rectifier tube to turn on to start timing.
20. The control circuit according to claim 17, wherein: The secondary side control signal generator includes: a fourth comparator having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives the voltage signal on the secondary winding, and the second input terminal receives the fourth reference value; a fourth flip-flop having a set terminal, a reset terminal and an output terminal, wherein the set terminal is connected to the output terminal of the fourth comparator; The secondary side control timer has a timing start end and a timing result output end, wherein the timing start end starts timing after prompting the secondary side synchronous rectifier tube to be turned on, and after the first estimated time, the timing result output end outputs the timing result to the reset end of the fourth trigger.
21. The control circuit according to claim 20, wherein: The output signal of the output terminal of the fourth comparator or the fourth trigger is used to prompt the secondary-side synchronous rectifier to turn on.
22. The control circuit according to claim 21, wherein: An output signal of the output terminal of the fourth trigger serves as the secondary side switch control signal.
23. The control circuit according to claim 21, wherein: The output signal of the secondary side control timer at the timing result output terminal is used as the secondary side switch control signal, and the output signal of the timing result output terminal is a single pulse signal.
24. The control circuit according to claim 21, wherein: Further including: The second AND gate has two input terminals and an output terminal, wherein the two input terminals are respectively connected to the output terminal of the fourth comparator and the output terminal of the fourth trigger.
25. The control circuit according to claim 24, wherein: The output signal of the output terminal of the second AND gate serves as the control signal of the secondary side switch tube.
26. The control circuit according to claim 21, wherein: It further includes a synchronous rectification time prediction circuit for predicting the turn-off moment of the secondary-side synchronous rectifier tube, thereby variably generating the first estimated time as the turn-on time of the secondary-side synchronous rectifier tube, and the output end of the synchronous rectification time prediction circuit outputs the first estimated time to the secondary-side control timer.
27. The control circuit according to claim 26, wherein: An input end of the synchronous rectification time prediction circuit receives a voltage signal on the secondary winding, and generates the first estimated time according to the voltage signal on the secondary winding.
28. The control circuit according to claim 1, wherein: The isolated power supply control circuit further includes: a first delay circuit, which is used to delay the shutdown of the secondary side switch tube to reduce the interval between the shutdown moment of the secondary side switch tube and the turn-on moment of the primary side switch tube, wherein the first delay circuit does not delay the shutdown moment of the secondary side switch tube indicated by the secondary side switch tube control signal.
29. The control circuit according to claim 28, wherein: The delay time of the first delay circuit is adjustable. The control circuit further includes a transient judgment circuit, which judges whether a load jump occurs in the isolated power supply. When the transient judgment circuit judges that a load jump occurs, the transient signal is output to the first delay circuit to reduce the delay time of the first delay circuit.
30. The control circuit according to claim 29, wherein: The delay time of the first delay circuit is adjustable. The control circuit further includes a dead time detection circuit. The dead time detection circuit is used to calculate the dead time of the previous working cycle and compare the calculated dead time with a dead time reference. When the dead time is less than the reference value, the dead time detection circuit adjusts to reduce the delay time of the first delay circuit. When the dead time is greater than the dead time reference value, the dead time detection circuit adjusts to increase the delay time of the first delay circuit.
31. A control circuit for an isolated power supply, the isolated power supply control circuit comprising: a secondary-side control signal generator, configured to receive a voltage signal on a secondary winding of the isolated power supply and generate a secondary-side switch tube drive signal, wherein the secondary-side switch tube drive signal is used to control the switching on and off of the secondary-side synchronous rectifier tube; a secondary-side switch-off detector coupled to the secondary side of the isolated power supply, configured to generate a shutdown confirmation signal when the secondary-side synchronous rectifier tube has been turned off; A primary side original turn-on signal generator receives a feedback signal of the output voltage of the isolated power supply and generates a primary side original turn-on time signal to indicate the turn-on time of the primary side switch tube as the first turn-on time; A primary-side control signal generator is used to receive the shutdown confirmation signal and the primary-side original turn-on time signal to generate a primary-side switch tube control signal to prompt the turn-on time of the primary-side switch tube, wherein the primary-side control signal generator determines a second turn-on time based on the shutdown confirmation signal, and the second turn-on time is the time when it is confirmed that the secondary-side synchronous rectifier tube has been turned off. The primary-side control signal generator further determines the turn-on time of the primary-side switch tube based on the later of the second turn-on time and the first turn-on time to generate the primary-side switch tube control signal.
32. An isolated power supply, comprising: An isolation converter having a primary side and a secondary side, wherein the primary side includes a primary switch tube, and the secondary side includes a secondary winding and a synchronous rectifier tube; The isolated power supply control circuit according to any one of claims 1 or 31, is used to control the primary side switch tube and the synchronous rectifier tube.
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