A clock division coefficient switching circuit and method thereof

Abstract

This invention relates to a clock division factor switching circuit and method, belonging to the field of clock division technology. The clock division factor switching circuit includes: a configuration unit, a synchronization unit, an update unit, and a clock divider; the synchronization unit is connected to both the configuration unit and the update unit; the update unit is connected to both the configuration unit and the clock divider; the method is applied to the update unit and includes: upon receiving a synchronization division factor marker signal sent by the synchronization unit, obtaining a division factor signal from the configuration unit; converting the division factor signal into a division factor update signal matching the clock divider; buffering the division factor update signal; and upon receiving a complete clock cycle output signal sent by the clock divider, sending the division factor update signal to the clock divider. In this invention, a smooth switching of the output divided clock can be achieved without shutting down the clock divider, reducing the operation process and time, and providing high reliability.

Description

Technical Field

[0001] This invention relates to the field of clock frequency division technology, and in particular to a clock frequency division coefficient switching circuit and method thereof. Background Technology

[0002] Clock dividers are widely used in chips to provide clock sources for various IPs. Typically, chips include a dedicated clock management unit for configuring the divider's division factor and clock gating. In traditional clock divider operation, switching the division factor can lead to abnormal output clock readings. Current methods involve adding a clock gating cell to first disable the divider's output clock, then changing the division factor, and finally enabling the clock again to switch the clock. However, this method often results in abnormal output clock readings due to incorrect signal acquisition timing, leading to low reliability. Furthermore, the process is cumbersome, time-consuming to switch division factors, and requires an additional clock gating cell. Summary of the Invention

[0003] This invention provides a clock division coefficient switching circuit and method to solve the problems of cumbersome operation process, long switching time and low reliability in existing methods.

[0004] In a first aspect, the present invention provides a clock division factor switching method, wherein the clock division factor switching circuit includes: a configuration unit, a synchronization unit, an update unit, and a clock divider; the synchronization unit is connected to the configuration unit and the update unit respectively; the update unit is connected to the configuration unit and the clock divider respectively; the method is applied to the update unit, and the method includes:

[0005] Upon receiving the synchronization division coefficient marker signal sent by the synchronization unit, the synchronization unit obtains the division coefficient signal from the configuration unit; wherein, the synchronization division coefficient marker signal is generated by the synchronization unit according to the division coefficient synchronization request signal sent by the configuration unit;

[0006] The frequency division coefficient signal is converted into a frequency division coefficient update signal that matches the clock frequency divider;

[0007] Cache the frequency division coefficient update signal;

[0008] Upon receiving the complete clock cycle output signal from the clock divider, the frequency division coefficient update signal is sent to the clock divider.

[0009] A further technical solution is that the updating unit includes an acquisition unit and a conversion unit; the acquisition unit is connected to the conversion unit; the acquisition unit is connected to the configuration unit and the synchronization unit respectively; the conversion unit is connected to the clock divider, and the step of converting the division coefficient signal into a division coefficient update signal matching the clock divider includes:

[0010] The acquisition unit receives the frequency division coefficient signal sent by the configuration unit, converts the frequency division coefficient signal into a frequency division coefficient buffer signal, and sends the frequency division coefficient buffer signal to the conversion unit;

[0011] The conversion unit receives the frequency division coefficient buffer signal and converts the frequency division coefficient buffer signal into the frequency division coefficient update signal that matches the clock frequency divider.

[0012] Secondly, the present invention also provides a clock division factor switching method, wherein the clock division factor switching circuit includes: a configuration unit, a synchronization unit, an update unit, and a clock divider; the synchronization unit is connected to the configuration unit and the update unit respectively; the update unit is connected to the configuration unit and the clock divider respectively; the method is applied to the synchronization unit, and the method includes:

[0013] Receive the frequency division coefficient synchronization request signal sent by the configuration unit;

[0014] Generate a synchronization frequency division coefficient marker signal based on the frequency division coefficient synchronization request signal;

[0015] The synchronization division coefficient marker signal is sent to the update unit. When the update unit receives the synchronization division coefficient marker signal sent by the synchronization unit, it obtains the division coefficient signal from the configuration unit; converts the division coefficient signal into a division coefficient update signal that matches the clock divider; buffers the division coefficient update signal; and sends the division coefficient update signal to the clock divider when it receives the complete clock cycle output signal sent by the clock divider.

[0016] A further technical solution is that, after generating the synchronization frequency division coefficient marker signal based on the frequency division coefficient synchronization request signal, the method further includes:

[0017] Send a frequency division coefficient response signal to the configuration unit.

[0018] Thirdly, the present invention provides a clock division factor switching circuit, which includes: a configuration unit, a synchronization unit, an update unit, and a clock divider; the synchronization unit is connected to the configuration unit and the update unit respectively; the update unit is connected to the configuration unit and the clock divider respectively.

[0019] The configuration unit is used to send a frequency division coefficient synchronization request signal to the synchronization unit and a frequency division coefficient signal to the update unit.

[0020] The synchronization unit is used to receive the frequency division coefficient synchronization request signal sent by the configuration unit; generate a synchronization frequency division coefficient marker signal according to the frequency division coefficient synchronization request signal; and send the synchronization frequency division coefficient marker signal to the update unit.

[0021] The update unit is configured to, upon receiving the synchronization division coefficient flag signal sent by the synchronization unit, obtain the division coefficient signal from the configuration unit; convert the division coefficient signal into a division coefficient update signal that matches the clock divider; buffer the division coefficient update signal; and, upon receiving the complete clock cycle output signal sent by the clock divider, send the division coefficient update signal to the clock divider.

[0022] A further technical solution is that the update unit includes an acquisition unit and a conversion unit, the acquisition unit being connected to the conversion unit; the acquisition unit is connected to the configuration unit and the synchronization unit respectively; the conversion unit is connected to the clock divider.

[0023] The acquisition unit is used to receive the frequency division coefficient signal sent by the configuration unit and convert the frequency division coefficient signal into a frequency division coefficient buffer signal.

[0024] The conversion unit is used to receive the frequency division coefficient buffer signal and convert the frequency division coefficient buffer signal into the frequency division coefficient update signal that matches the clock frequency divider.

[0025] A further technical solution is that the synchronization unit is also used to send the frequency division coefficient response signal to the configuration unit after generating the synchronization frequency division coefficient mark signal according to the frequency division coefficient synchronization request signal.

[0026] A further technical solution is that the synchronization unit includes a first trigger and a second trigger; the first trigger is connected to the second trigger; the first trigger is also connected to the configuration unit; and the second trigger is connected to the acquisition unit.

[0027] A further technical solution is that the acquisition unit includes a first selector and a third trigger; the first selector is connected to the third trigger; the first selector is also connected to the configuration unit and the second trigger respectively; the third trigger is connected to the conversion unit.

[0028] A further technical solution is that the conversion unit includes a second selector and a fourth flip-flop; the second selector is connected to the fourth flip-flop; the second selector is connected to the third flip-flop and the clock divider respectively; and the fourth flip-flop is connected to the clock divider.

[0029] Beneficial effects:

[0030] Upon receiving the synchronization division coefficient marker signal from the synchronization unit, the division coefficient signal is obtained from the configuration unit. This signal is then converted into a division coefficient update signal that matches the clock divider and buffered. When the clock divider sends a complete clock cycle output signal, the division coefficient update signal is sent to the clock divider. Since the clock divider may not have yet output a complete clock cycle, the division coefficient update signal is buffered in a trigger. Once the clock divider outputs a complete clock cycle, the update signal is input to the clock divider so that it outputs a new divided clock, thus achieving a smooth switching effect.

[0031] Existing methods switch clocks by disabling the clock divider, which is prone to clock anomalies and has low reliability. In this invention, a smooth switching of the output clock frequency can be achieved without disabling the clock divider, reducing the operation process and time, and ensuring high reliability. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0034] Figure 1 This is a flowchart illustrating a clock division coefficient switching method provided in Embodiment 1 of the present invention;

[0035] Figure 2This is a flowchart illustrating a clock division coefficient switching method provided in Embodiment 2 of the present invention;

[0036] Figure 3 This is another flowchart illustrating a clock division coefficient switching method provided in Embodiment 3 of the present invention;

[0037] Figure 4 This is a structural diagram of a clock division coefficient switching circuit provided in Embodiment 4 of the present invention.

[0038] Figure Labels

[0039] Configuration unit 10, synchronization unit 21, first trigger 211, second trigger 212, acquisition unit 22, first selector 221, third trigger 222, conversion unit 23, second selector 231, fourth trigger 232, clock divider 30, update unit 40. Detailed Implementation

[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0042] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0043] It should also be further understood that the term “and / or” as used in this specification and the appended claims refers to any combination of one or more of the associated listed items, as well as all possible combinations, and includes such combinations.

[0044] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrases "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0045] Example 1

[0046] See Figure 1 Embodiment 1 of the present invention provides a clock division factor switching method. The clock division factor switching circuit of the method includes: a configuration unit, a synchronization unit, an update unit, and a clock divider; the synchronization unit is connected to the configuration unit and the update unit respectively; the update unit is connected to the configuration unit and the clock divider respectively. The clock division factor switching method of Embodiment 1 is applied to the update unit, and the flowchart of the clock division factor switching method of Embodiment 1 is shown below. Figure 1 As shown, it includes the following steps: S101-S104.

[0047] S101, upon receiving the synchronization division coefficient marker signal sent by the synchronization unit, the synchronization unit obtains the division coefficient signal from the configuration unit; wherein, the synchronization division coefficient marker signal is generated by the synchronization unit according to the division coefficient synchronization request signal sent by the configuration unit.

[0048] In this embodiment of the invention, after the synchronization unit synchronizes the beat, a synchronization frequency division coefficient marker signal (div_change_sync) is generated. The generated synchronization frequency division coefficient marker signal (div_change_sync) indicates that the currently received frequency division coefficient signal (div_factor[x:0]) can be acquired. The update unit includes a selector and a trigger; the update unit can acquire the frequency division coefficient signal (div_factor[x:0]) through the selector and the trigger and cache the frequency division coefficient signal (div_factor[x:0]) in the trigger. Here, x in the frequency division coefficient signal (div_factor[x:0]) refers to the bit width, which can be set according to actual needs. The frequency division coefficient signal (div_factor[x:0]) refers to the unsynchronized frequency division coefficient that needs to be updated sent by the configuration unit, which can specifically be the main control CPU chip.

[0049] S102, convert the frequency division coefficient signal into a frequency division coefficient update signal that matches the clock frequency divider.

[0050] Specifically, as mentioned above, the synchronization unit performs a synchronization cycle on the frequency division coefficient synchronization request signal sent by the configuration unit. After the synchronization cycle, a synchronization frequency division coefficient marker signal (div_change_sync) is generated, indicating that the current frequency division coefficient signal (div_change_sync) can be acquired. Optionally, after the frequency division coefficient signal (div_factor[x:0]) is acquired, the synchronization unit sends an acknowledgment signal (div_change_ack) to the configuration unit so that the configuration unit knows that the current frequency division coefficient signal (div_factor[x:0]) has been acquired, thus improving stability. It should be noted that, in another embodiment, after the frequency division coefficient signal (div_factor[x:0]) is acquired, it is not necessary to send an acknowledgment signal (div_change_ack) to the configuration unit to achieve the same smooth clock switching effect as in this scheme.

[0051] In one embodiment, the update unit includes an acquisition unit and a conversion unit; the acquisition unit is connected to the conversion unit; the acquisition unit is connected to the configuration unit and the synchronization unit respectively; the conversion unit is connected to the clock divider, and the step of converting the division coefficient signal into a division coefficient update signal matching the clock divider includes:

[0052] The acquisition unit receives the frequency division coefficient signal sent by the configuration unit, converts the frequency division coefficient signal into a frequency division coefficient buffer signal, and sends the frequency division coefficient buffer signal to the conversion unit;

[0053] The conversion unit receives the frequency division coefficient buffer signal and converts the frequency division coefficient buffer signal into the frequency division coefficient update signal that matches the clock frequency divider.

[0054] Specifically, by receiving the synchronous division coefficient marker signal (div_change_sync) and the division coefficient signal (div_factor[x:0]), the division coefficient signal (div_factor[x:0]) is first converted into a synchronous division coefficient buffer signal (div_factor_sync[x:0]) corresponding to the synchronous division coefficient marker signal (div_change_sync) through a flip-flop and a selector, and then converted into a division coefficient update signal (div_factor_new[x:0]) matching the clock divider. The division coefficient update signal (div_factor_new[x:0]) is then latched in the flip-flop, so that after the clock divider outputs a complete clock cycle, the division coefficient update signal (div_factor_new[x:0]) is input into the clock divider so that the clock divider outputs a new divided clock.

[0055] S103, buffer the frequency division coefficient update signal.

[0056] Specifically, as mentioned above, after converting the division factor signal (div_factor[x:0]) into a division factor update signal (div_factor_new[x:0]) that matches the clock divider, since the clock divider may not have output a complete clock cycle yet, the division factor update signal (div_factor_new[x:0]) is buffered in a flip-flop so that it can be input into the clock divider after the clock divider outputs a complete clock cycle, thereby enabling the clock divider to output a new divided clock and achieving a smooth switching effect.

[0057] S104: Upon receiving the complete clock cycle output signal from the clock divider, send the frequency division coefficient update signal to the clock divider.

[0058] Specifically, after the clock divider outputs a complete clock cycle, it sends a clock cycle output complete signal (div_factor_update). After the clock cycle output complete signal (div_factor_update) is acquired by the selector, the synchronous division coefficient buffer signal (div_factor_sync[x:0]) is converted into a division coefficient update signal (div_factor_new[x:0]). Then, the division coefficient update signal (div_factor_new[x:0]) is input into the clock divider, thereby enabling the clock divider to smoothly switch the output divided clock.

[0059] Example 2

[0060] See Figure 2 Embodiment 2 of the present invention also provides a clock division factor switching method. The clock division factor switching circuit of this method includes: a configuration unit, a synchronization unit, an update unit, and a clock divider; the synchronization unit is connected to the configuration unit and the update unit respectively; the update unit is connected to the configuration unit and the clock divider respectively. The clock division factor switching method of Embodiment 2 is applied to the synchronization unit, and the flowchart of the clock division factor switching method of Embodiment 2 is shown below. Figure 2 As shown, it includes the following steps: S201-S203.

[0061] S201, Receive the frequency division coefficient synchronization request signal sent by the configuration unit.

[0062] In this embodiment of the invention, the synchronization unit includes a trigger. A synchronization frequency division coefficient marker signal (div_change_sync) is generated by synchronizing the frequency division coefficient update request signal (div_change_req). The generated synchronization frequency division coefficient marker signal (div_change_sync) indicates that the currently received frequency division coefficient signal (div_factor[x:0]) can be acquired. The update unit includes a selector and a trigger; the update unit can acquire the frequency division coefficient signal (div_factor[x:0]) through the selector and the trigger and cache the frequency division coefficient signal (div_factor[x:0]) in the trigger. Here, x in the frequency division coefficient signal (div_factor[x:0]) refers to the bit width, which can be set according to actual needs. The frequency division coefficient signal (div_factor[x:0]) refers to the unsynchronized frequency division coefficient that needs to be updated sent by the configuration unit, which can specifically be a main control CPU chip.

[0063] S202, Generate a synchronization frequency division coefficient marker signal based on the frequency division coefficient synchronization request signal.

[0064] Specifically, a synchronous frequency division coefficient marker signal (div_change_sync) is generated by synchronizing the frequency division coefficient update request signal (div_change_req). The generated synchronous frequency division coefficient marker signal (div_change_sync) indicates that the currently received frequency division coefficient signal (div_factor[x:0]) can be acquired.

[0065] S103, the synchronization division coefficient marker signal is sent to the update unit, wherein, when the update unit receives the synchronization division coefficient marker signal sent by the synchronization unit, it obtains the division coefficient signal from the configuration unit; converts the division coefficient signal into a division coefficient update signal that matches the clock divider; buffers the division coefficient update signal; and when it receives the clock cycle output complete signal sent by the clock divider, it sends the division coefficient update signal to the clock divider.

[0066] Specifically, by sending a synchronous division factor flag signal (div_change_sync) to the update unit, it indicates that the current division factor signal (div_change_sync) can be acquired. After acquiring the division factor signal (div_factor[x:0]), the update unit converts it into a division factor update signal (div_factor_new[x:0]) that matches the clock divider and caches the update signal (div_factor_new[x:0]) in the flip-flop. After the clock divider outputs a complete clock cycle, it sends a clock cycle output complete signal (div_factor_update). After the selector acquires the clock cycle output complete signal (div_factor_update), it inputs the division factor update signal (div_factor_new[x:0]) into the clock divider to achieve a smooth switching of the divided clock.

[0067] Example 3

[0068] See Figure 3 Embodiment 3 of the present invention also provides a clock division factor switching method. The clock division factor switching circuit of this method includes: a configuration unit, a synchronization unit, an update unit, and a clock divider; the synchronization unit is connected to the configuration unit and the update unit respectively; the update unit is connected to the configuration unit and the clock divider respectively. The clock division factor switching method of Embodiment 2 is applied to the synchronization unit. The difference between the clock division factor switching method of Embodiment 3 and the clock division factor switching method of Embodiment 2 is that the latter also includes step S204.

[0069] S204, send a frequency division coefficient response signal to the configuration unit.

[0070] Specifically, the synchronization unit uses a trigger to synchronize the frequency division coefficient synchronization request signal sent by the configuration unit. After the synchronization cycle, a synchronization frequency division coefficient marker signal (div_change_sync) is generated, indicating that the current frequency division coefficient signal (div_change_sync) can be acquired. After the frequency division coefficient signal (div_factor[x:0]) is acquired, the synchronization unit sends an acknowledgment signal (div_change_ack) to the configuration unit so that the configuration unit knows that the current frequency division coefficient signal (div_factor[x:0]) has been acquired, thus improving stability. It should be noted that in another embodiment, after the frequency division coefficient signal (div_factor[x:0]) is acquired, it is not necessary to send an acknowledgment signal (div_change_ack) to the configuration unit to achieve the same smooth clock switching effect as in this scheme.

[0071] Example 4

[0072] See Figure 4 , Figure 4 A clock division factor switching circuit is provided in Embodiment 3 of the present invention. The clock division factor switching circuit includes: a configuration unit 10, a synchronization unit 21, an update unit 40, and a clock divider 30; the synchronization unit 21 is connected to the configuration unit 10 and the update unit 40 respectively; the update unit 40 is connected to the configuration unit 10 and the clock divider 30 respectively.

[0073] The configuration unit 10 is used to send a frequency division coefficient synchronization request signal to the synchronization unit 21 and a frequency division coefficient signal to the update unit 40.

[0074] The synchronization unit 21 is used to receive the frequency division coefficient synchronization request signal sent by the configuration unit 10; generate a synchronization frequency division coefficient mark signal according to the frequency division coefficient synchronization request signal; and send the synchronization frequency division coefficient mark signal to the update unit 40.

[0075] The update unit 40 is configured to, upon receiving the synchronization division coefficient marker signal sent by the synchronization unit 21, obtain the division coefficient signal from the configuration unit 10; convert the division coefficient signal into a division coefficient update signal that matches the clock divider 30; buffer the division coefficient update signal; and send the division coefficient update signal to the clock divider 30 upon receiving the complete clock cycle output signal sent by the clock divider 30.

[0076] Specifically, the synchronization unit 21 receives the frequency division coefficient synchronization request signal (div_change_req) sent by the configuration unit 10 and generates a synchronization frequency division coefficient mark signal (div_change_sync) for the synchronization beat. Then, the update unit 40 collects the frequency division coefficient signal (div_factor[x:0]) sent by the configuration unit 10 and converts it into a synchronization frequency division coefficient buffer signal (div_factor_sync[x:0]) corresponding to the synchronization frequency division coefficient mark signal (div_change_sync). Then, the synchronization frequency division coefficient buffer signal (div_factor_sync[x:0]) is converted into a frequency division coefficient update signal (div_factor_new[x:0]) that matches the clock divider 30. This ensures that after the clock divider 30 outputs a complete clock cycle, the frequency division coefficient update signal (div_factor_new[x:0]) is input into the clock divider 30 so that the clock divider 30 outputs a new frequency division clock, thereby achieving a smooth switching effect.

[0077] Furthermore, the synchronization unit 21 is also used to send a frequency division coefficient response signal to the configuration unit 10 after generating a synchronization frequency division coefficient marker signal according to the frequency division coefficient synchronization request signal.

[0078] Specifically, the current frequency division factor signal (div_change_sync) can be acquired. After the frequency division factor signal (div_factor[x:0]) is acquired, the synchronization unit will send an acknowledgment signal (div_change_ack) to the configuration unit so that the configuration unit 10 knows that the current frequency division factor signal (div_factor[x:0]) has been acquired.

[0079] Furthermore, the update unit 40 includes an acquisition unit 22 and a conversion unit 23, wherein the acquisition unit 22 is connected to the conversion unit 23; the acquisition unit 22 is also connected to the configuration unit 10 and the synchronization unit 21 respectively; and the conversion unit 23 is connected to the clock divider 30.

[0080] Specifically, the synchronization unit 21 synchronizes the frequency division coefficient synchronization request signal (div_change_req) sent by the configuration unit 10 and outputs a synchronization frequency division coefficient marker signal (div_change_sync). The acquisition unit 22 acquires the frequency division coefficient signal (div_factor[x:0]) sent by the configuration unit 10 and converts it into a synchronization frequency division coefficient buffer signal (div_factor_sync[x:0]) corresponding to the synchronization frequency division coefficient marker signal (div_change_sync). After the frequency division coefficient signal (div_factor[x:0]) is acquired, the synchronization unit 21 also sends an acknowledgment signal (div_change_ack) to the configuration unit 10 to inform that the current frequency division coefficient signal (div_factor[x:0]) has been acquired. The conversion unit 23 converts the update signal (div_factor_sync[x:0]) into a frequency division coefficient update signal (div_factor_new[x:0]) that matches the clock divider 30.

[0081] Furthermore, the synchronization unit 21 includes a first trigger 211 and a second trigger 212; the first trigger 211 is connected to the configuration unit 10 and the second trigger 212 respectively; the second trigger 212 is connected to the acquisition unit 22.

[0082] Specifically, the frequency division coefficient synchronization request signal (div_change_req) sent by the configuration unit 10 is synchronized by the first trigger 211 and the second trigger 212, and then a synchronization frequency division coefficient mark signal (div_change_sync) is output so that the acquisition unit can acquire the frequency division coefficient signal (div_factor[x:0]) after acquiring the synchronization frequency division coefficient mark signal (div_change_sync).

[0083] Furthermore, the acquisition unit 22 includes a first selector 221 and a third trigger 222; the first selector 221 is connected to the third trigger 222; the first selector 221 is also connected to the configuration unit 10 and the second trigger 212 respectively; the third trigger 222 is connected to the conversion unit 23.

[0084] Specifically, the frequency division coefficient signal (div_factor[x:0]) is acquired through the first selector 221 and the third trigger 222, and then the third trigger 222 outputs an update signal (div_factor_sync[x:0]) corresponding to the synchronization frequency division coefficient marker signal (div_change_sync). The first selector 221 can select and determine the input signal, and the third trigger 222 can buffer and transform the signal input to the first selector 221. The third trigger 222 can perform layered changes through relevant tables in the database, making data processing faster and more efficient.

[0085] Furthermore, the conversion unit 23 includes a second selector 231 and a fourth flip-flop 232; the second selector 231 is connected to the fourth flip-flop 232; the second selector 231 is also connected to the third flip-flop 222 and the clock divider 30 respectively; the fourth flip-flop 232 is connected to the clock divider 30.

[0086] Specifically, after receiving the complete clock cycle output signal (div_factor_update) from the clock divider, the fourth flip-flop 232 converts the update signal (div_factor_sync[x:0]) into a division coefficient update signal (div_factor_new[x:0]) after acquiring the complete clock cycle output signal (div_factor_update) through the second selector 231. This division coefficient update signal (div_factor_new[x:0]) is then input into the clock divider 30, enabling the clock divider 30 to smoothly switch the output divided clock. The second selector 231 can select and determine the input signal, and the fourth flip-flop 232 can buffer and convert the signal input to the second selector 231. The fourth flip-flop 232 can perform layered changes through relevant tables in the database, making data processing faster and more efficient.

[0087] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0088] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Since these modifications and variations fall within the scope of the claims and their equivalents, this invention also intends to include these modifications and variations.

[0089] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for switching clock division coefficients, characterized in that, The clock division factor switching circuit includes: a configuration unit, a synchronization unit, an update unit, and a clock divider; the synchronization unit is connected to the configuration unit and the update unit respectively; the update unit is connected to the configuration unit and the clock divider respectively; the method is applied to the update unit, and the method includes: Upon receiving the synchronization division coefficient marker signal sent by the synchronization unit, the synchronization unit obtains the division coefficient signal from the configuration unit; wherein, the synchronization division coefficient marker signal is generated by the synchronization unit according to the division coefficient synchronization request signal sent by the configuration unit; The frequency division coefficient signal is converted into a frequency division coefficient update signal that matches the clock frequency divider; Cache the frequency division coefficient update signal; Upon receiving the complete clock cycle output signal from the clock divider, the frequency division coefficient update signal is sent to the clock divider.

2. The clock division coefficient switching method according to claim 1, characterized in that, The update unit includes a data acquisition unit and a conversion unit; the data acquisition unit is connected to the conversion unit; the data acquisition unit is also connected to the configuration unit and the synchronization unit. The conversion unit is connected to the clock divider, and the step of converting the division coefficient signal into a division coefficient update signal that matches the clock divider includes: The acquisition unit receives the frequency division coefficient signal sent by the configuration unit, converts the frequency division coefficient signal into a frequency division coefficient buffer signal, and sends the frequency division coefficient buffer signal to the conversion unit; The conversion unit receives the frequency division coefficient buffer signal and converts the frequency division coefficient buffer signal into the frequency division coefficient update signal that matches the clock frequency divider.

3. A method for switching clock division coefficients, characterized in that, The clock division factor switching circuit includes: a configuration unit, a synchronization unit, an update unit, and a clock divider; the synchronization unit is connected to the configuration unit and the update unit respectively; the update unit is connected to the configuration unit and the clock divider respectively; the method is applied to the synchronization unit, and the method includes: Receive the frequency division coefficient synchronization request signal sent by the configuration unit; Generate a synchronization frequency division coefficient marker signal based on the frequency division coefficient synchronization request signal; The synchronization division coefficient marker signal is sent to the update unit. When the update unit receives the synchronization division coefficient marker signal sent by the synchronization unit, it obtains the division coefficient signal from the configuration unit; converts the division coefficient signal into a division coefficient update signal that matches the clock divider; buffers the division coefficient update signal; and sends the division coefficient update signal to the clock divider when it receives the complete clock cycle output signal sent by the clock divider.

4. The clock division coefficient switching method according to claim 3, characterized in that, After generating the synchronization frequency division coefficient marker signal based on the frequency division coefficient synchronization request signal, the method further includes: Send a frequency division coefficient response signal to the configuration unit.

5. A clock division coefficient switching circuit, characterized in that, The clock division factor switching circuit includes: a configuration unit, a synchronization unit, an update unit, and a clock divider; the synchronization unit is connected to the configuration unit and the update unit respectively; the update unit is connected to the configuration unit and the clock divider respectively. The configuration unit is used to send a frequency division coefficient synchronization request signal to the synchronization unit and a frequency division coefficient signal to the update unit. The synchronization unit is used to receive the frequency division coefficient synchronization request signal sent by the configuration unit; generate a synchronization frequency division coefficient marker signal according to the frequency division coefficient synchronization request signal; and send the synchronization frequency division coefficient marker signal to the update unit. The update unit is configured to, upon receiving the synchronization division coefficient flag signal sent by the synchronization unit, obtain the division coefficient signal from the configuration unit; convert the division coefficient signal into a division coefficient update signal that matches the clock divider; buffer the division coefficient update signal; and, upon receiving the complete clock cycle output signal sent by the clock divider, send the division coefficient update signal to the clock divider.

6. The clock division coefficient switching circuit according to claim 5, characterized in that, The update unit includes a data acquisition unit and a conversion unit, wherein the data acquisition unit is connected to the conversion unit; the data acquisition unit is connected to the configuration unit and the synchronization unit respectively; and the conversion unit is connected to the clock divider. The acquisition unit is used to receive the frequency division coefficient signal sent by the configuration unit and convert the frequency division coefficient signal into a frequency division coefficient buffer signal. The conversion unit is used to receive the frequency division coefficient buffer signal and convert the frequency division coefficient buffer signal into the frequency division coefficient update signal that matches the clock frequency divider.

7. The clock division coefficient switching circuit according to claim 5, characterized in that, The synchronization unit is further configured to send a frequency division coefficient response signal to the configuration unit after generating a synchronization frequency division coefficient marker signal based on the frequency division coefficient synchronization request signal.

8. The clock division coefficient switching circuit according to claim 6, characterized in that, The synchronization unit includes a first trigger and a second trigger; the first trigger is connected to the second trigger; the first trigger is also connected to the configuration unit; and the second trigger is connected to the acquisition unit.

9. The clock division coefficient switching circuit according to claim 8, characterized in that, The acquisition unit includes a first selector and a third trigger; the first selector is connected to the third trigger; the first selector is also connected to the configuration unit and the second trigger; the third trigger is connected to the conversion unit.

10. The clock division coefficient switching circuit according to claim 9, characterized in that, The conversion unit includes a second selector and a fourth flip-flop; the second selector is connected to the fourth flip-flop; the second selector is connected to the third flip-flop and the clock divider respectively; the fourth flip-flop is connected to the clock divider.

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