A layout structure on a substrate and a preparation method thereof

Abstract

The present invention provides a layout structure on a substrate and a preparation method thereof. In this layout structure, the gate material for transistor devices is simultaneously formed in a monitoring area to serve as a first cushion layer, raising the mesa height of the monitoring area, so that the film layer to be detected in the monitoring area can be formed at a higher position. Furthermore, the depth of the groove above the film layer to be detected can be reduced, making it easy for the groove to be filled with material without forming an internal notch, thereby avoiding the residue of pollutants in the internal notch and making it difficult to remove.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a layout structure on a substrate and a preparation method thereof. Background Art

[0002] For high-voltage transistor devices (such as, laterally diffused metal oxide semiconductor LDMOS, etc.), in order to reduce the surface field strength of the transistor device, a field plate structure is usually provided on the side where the gate faces the drain, and the provided field plate structure is, for example, a contact field plate structure (CFP).

[0003] Specifically, reference can be made to Figure 1 and Figure 2 As shown, the contact field plate structure CFP includes a field dielectric layer 30A and a hole field plate 50A formed on the field dielectric layer 30A. Since the thickness of the field dielectric layer 30A of the contact field plate structure CFP is crucial for reducing the field strength, it is necessary to monitor it (for example, thickness monitoring). In order to realize the monitoring of the field dielectric layer 30A, generally, when preparing the field dielectric layer 30A, a part for monitoring is formed in the monitoring area BB at the same time to form a film layer to be detected 30B.

[0004] Continuing to refer to Figure 1 As shown, in order to ensure that the film layer condition of the film layer to be detected 30B in the monitoring area BB is close to the film layer condition of the field dielectric layer 30A in the device area AA, the film layer to be detected 30B is usually detected after the through hole 40A for forming the hole field plate is formed. At this time, a groove 40B needs to be opened in the monitoring area BB to expose the film layer to be detected 30B for easy detection. Then, referring to Figure 2 As shown, that is, a conductive material is filled in the through hole 40A to form a hole field plate 50A, and the conductive material is also formed in the groove 40B. However, due to the large size of the groove 40B, an inner notch 40B' will still be formed when the conductive material is formed in the groove 40B. This inner notch 40B' is prone to the accumulation of contaminants and is difficult to remove (for example, the polishing liquid in the chemical mechanical polishing process is easy to remain in the inner notch 40B'), thus becoming a source of defects in device processing. Summary of the Invention

[0005] The purpose of the present invention is to provide a layout structure on a substrate to solve the problem that the arranged monitoring structure is prone to form an inner notch, resulting in the residue of contaminants.

[0006] To solve the above technical problems, the present invention provides a layout structure on a substrate, including: a substrate having a device region and a monitoring region; a gate material layer formed in the device region to form a gate in a transistor device and also formed on the substrate in the monitoring region to form a first cushion layer; a first dielectric material layer formed in the device region to form a field dielectric layer of the transistor device and also formed in the monitoring region and covering the first cushion layer to form a film layer to be detected of a monitoring structure; and a second dielectric material layer covering the device region and the monitoring region, and through holes are further formed in a portion of the second dielectric material layer located in the device region, the through holes are used to fill hole field plates, and a groove is formed in a portion of the second dielectric material layer located in the monitoring region, and the bottom of the groove exposes the film layer to be detected located on the first cushion layer.

[0007] Optionally, a second cushion layer is further provided in the monitoring region, and the second cushion layer is provided below the first cushion layer and / or between the first cushion layer and the film layer to be detected.

[0008] Optionally, the first cushion layer is formed above the second cushion layer, and the height of the top surface of the first cushion layer relative to the top surface of the substrate is greater than or equal to

[0009] Optionally, the depth of the through hole is

[0010] Optionally, the depth of the groove can be less than or equal to

[0011] Optionally, both the width and the length of the groove are greater than or equal to 30 μm.

[0012] Optionally, the layout structure further includes a conductive material layer, the conductive material layer fills the through holes to form hole field plates, and the conductive material layer also fills the groove.

[0013] The present invention also provides a method for preparing a layout structure on a substrate, including: providing a substrate having a device region and a monitoring region; forming a gate material layer, wherein a portion of the gate material layer located in the device region is used to form the gate of a transistor device, and a portion of the gate material layer located in the monitoring region is used to form a first cushion layer; forming a first dielectric material layer, wherein a portion of the first dielectric material layer located in the device region is used to form the field dielectric layer of the transistor device, and a portion of the first dielectric material layer located in the monitoring region covers the first cushion layer to form a film layer to be detected of a monitoring structure; and forming a second dielectric material layer to cover the device region and the monitoring region, forming a through hole in a portion of the second dielectric material layer located in the device region, the bottom of the through hole exposing the field dielectric layer, and forming a groove in a portion of the second dielectric material layer located in the monitoring region, the bottom of the groove exposing the film layer to be detected located on the first cushion layer.

[0014] Optionally, before forming the second dielectric material layer, it further includes: forming an etching adjustment layer on the film layer to be detected. And the method for forming the groove includes: performing a first etching step to etch the second dielectric material layer and etching to the etching adjustment layer; performing a second etching step to etch the etching adjustment layer and stopping the etching on the film layer to be detected.

[0015] Optionally, after forming the through hole and the groove, it further includes: depositing a conductive material layer, the conductive material layer filling the through hole to form a hole field plate, and the conductive material layer also filling the groove.

[0016] In the layout structure on the substrate provided by the present invention, the gate material for the transistor device is simultaneously formed in the monitoring region to be used as the first cushion layer, raising the mesa height of the monitoring region, so that the film layer to be detected in the monitoring region can be formed at a higher position, and thus the depth of the groove above the film layer to be detected can be reduced. In this way, when forming the conductive material layer subsequently, the conductive material layer can easily fill the groove, avoiding the formation of a concave notch in the groove and resulting in pollutant residue. Description of the Drawings

[0017] Figure 1 It is a schematic diagram of a layout structure on a substrate without showing the hole field plate.

[0018] Figure 2 It is a schematic diagram of a layout structure on a substrate showing the hole field plate.

[0019] Figure 3 It is a schematic diagram of a layout structure on a substrate in an embodiment of the present invention without showing the hole field plate.

[0020] Figure 4 The schematic diagram of the layout structure on the substrate in an embodiment of the present invention shows the hole field plate.

[0021] Figure 5 The flowchart of the preparation of the layout structure on the substrate in an embodiment of the present invention.

[0022] Figures 6 - 10 The schematic diagram of the layout structure on the substrate in an embodiment of the present invention during its preparation process.

[0023] Among them, the reference numerals are as follows:

[0024] 30A - Field dielectric layer;

[0025] 30B - Film layer to be detected;

[0026] 40A - Through hole;

[0027] 40B - Groove;

[0028] 40B’ - Concave notch;

[0029] 50A - Hole field plate;

[0030] 100 - Substrate;

[0031] 200G - Gate;

[0032] 200S - Source;

[0033] 200D - Drain;

[0034] 210B - First cushion layer;

[0035] 220B - Second cushion layer;

[0036] 300A - Field dielectric layer;

[0037] 300B - Film layer to be detected;

[0038] 410A - Through hole;

[0039] 420A - Lead hole;

[0040] 400B - Groove;

[0041] 510A - Hole field plate;

[0042] 520A - Contact plug;

[0043] 600 - Etching adjustment layer. Detailed implementation manners

[0044] The following further elaborates on the layout structure on the substrate and its manufacturing method proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention. It should be recognized that relative terms such as "above", "below", "top", "bottom", "upper" and "lower" shown in the accompanying drawings can be used to describe the relationships between various elements with respect to each other. These relative terms are intended to cover different orientations of the elements other than the orientations depicted in the accompanying drawings. For example, if the device is inverted relative to the view in the accompanying drawings, an element described as "above" another element will now be below that element.

[0045] Figure 3 It is a schematic diagram of a semiconductor structure in an embodiment of the present invention when the hole field plate is not shown. Figure 4 It is a schematic diagram of a semiconductor structure in an embodiment of the present invention when the hole field plate is shown.

[0046] Specifically refer to Figure 3 and Figure 4 As shown, the semiconductor structure provided in this embodiment includes a transistor device and a monitoring structure. By monitoring the film layer 300B to be detected in the monitoring structure, the specific condition of the field dielectric layer 300A in the transistor device can be reflected to a certain extent, realizing effective monitoring of the field dielectric layer 300A. Among them, the monitoring structure can be specifically formed in the scribe line of the substrate.

[0047] Specifically, the semiconductor structure includes a substrate 100. The substrate 100 has a device region AA and a monitoring region BB. The transistor device is disposed in the device region AA, and the monitoring structure is disposed in the monitoring region BB. The monitoring region BB can be defined within the scribe line region.

[0048] Furthermore, a gate material layer is formed on the substrate 100. The gate material layer is formed in the device region AA to form the gate 200G of the transistor device, and the gate material layer is also formed in the monitoring region BB to form the first cushion layer 210B. By providing the first cushion layer 210B, the mesa at the corresponding position in the monitoring region BB is lifted, and then the height of the film layer 300B to be detected formed on the first cushion layer 210 can be increased. Among them, the thickness of the gate dielectric layer is, for example, The thickness of the formed first cushion layer 210B is correspondingly

[0049] In addition, a first dielectric material layer is further formed on the substrate 100. The first dielectric material layer is formed in the device region AA to form the field dielectric layer 300A of the transistor device, and the first dielectric material layer is also formed in the monitoring region BB and covers the first cushion layer 210B to form the film layer 300B to be detected. That is to say, the film layer 300B to be detected and the field dielectric layer 300A in the device region AA are formed by using the same dielectric material layer. Therefore, by monitoring and detecting the film layer 300B to be detected, the film layer condition of the field dielectric layer 300A can be reflected. For example, the thickness of the field dielectric layer 300A can be obtained by detecting the thickness of the film layer 300B to be detected.

[0050] Continue to refer to Figure 3 and Figure 4 As shown, a second dielectric material layer 400 is further formed on the substrate 100. The second dielectric material layer 400 covers the device region AA and the monitoring region BB. A through hole 410A is further formed in the part of the second dielectric material layer 400 located in the device region AA. The through hole 410A is used to fill the hole field plate 510A, and a groove 400B is formed in the part of the second dielectric material layer 400 located in the monitoring region BB. The bottom of the groove 400B exposes the film layer 300B to be detected on the first cushion layer 210B, so that the film layer 300B to be detected can be detected through the groove 400B.

[0051] For example, an optical detection device can be used to detect the thickness of the film layer 300B exposed in the groove 400B. In a specific example, in order to meet the detection requirements of the film layer 300B to be detected, the size of the formed groove 400B can be greater than or equal to 30μm * 30μm, that is, the width and length of the groove 400B are both greater than or equal to 30μm.

[0052] In a specific example, a plurality of lead holes 420A are further formed in the part of the second dielectric material layer 400 located in the device region AA. The plurality of lead holes 420A respectively expose the gate 200G, source 200S, and drain 200D of the transistor device, so that contact plugs can be formed in the lead holes 420A to realize the electrical lead-out of the transistor device. Specifically, the source 200S and the drain 200D are respectively located on both sides of the gate 200G, and the field dielectric layer 300A is disposed on the side of the gate 200G facing the drain 200D. In this embodiment, the field dielectric layer 300A covers the top surface of the gate 200G close to the drain 200D, extends to cover the side wall of the gate 200G and the top surface of the substrate, and extends laterally to the end of the drain 200D.

[0053] In this embodiment, the field dielectric layer 300A can also be used as a silicide area block (SAB) to shield the areas in the device region AA where silicide is not required to be formed and expose the areas in the device region AA where silicide needs to be formed. For example, the silicide area block (i.e., the field dielectric layer 300A) exposes at least a part of the top surfaces of the gate 200G, the source 200S, and the drain 200D. Then, a silicide layer can be formed self-alignedly on the exposed top surfaces of the gate 200G, the source 200S, and the drain 200D, reducing the contact resistance between the gate 200G, the source 200S, and the drain 200D and the corresponding contact plugs.

[0054] It should be noted that the second dielectric material layer 400 covers the device region AA and the monitoring region BB for capping and protecting the transistor device and the monitoring structure. Also, a through hole 410A for accommodating the hole field plate 510A and a via hole 420A for accommodating the contact plug 520A need to be formed in the second dielectric material layer 400. Therefore, the second dielectric material layer 400 needs to have a relatively large thickness to meet the requirements. For example, the thickness of the second dielectric material layer 400 is (i.e., the thickness of the second dielectric material layer 400 formed on the substrate surface can reach, for example, ).

[0055] At this time, if the film layer to be detected is directly disposed on the top surface of the substrate 100, then in order to expose the film layer to be detected, a groove with a relatively large depth needs to be formed. Specifically, as shown in Figure 1 the groove 40B shown, Figure 1 the depth of the groove 40B in will reach, for example,

[0056] and thus it is easy to have the problem of pollutant residue. In contrast, in this embodiment, the film layer to be detected 300B is at least partially formed on the first cushion layer 210B in the monitoring region BB, so that the height of the film layer to be detected 300B is increased. In this way, the depth of the formed groove 400B can be reduced. For example, the depth of the groove 400B can be reduced to be less than or equal to

[0057] In a further solution, a second cushion layer may also be provided above and / or below the first cushion layer 210B according to the thickness of the first cushion layer 210B and the height of the film layer 300B to be detected, that is, a second cushion layer is provided below the first cushion layer 210B and / or between the first cushion layer 210 and the film layer 300B to be detected, so as to further increase the height of the film layer 300B to be detected and correspondingly reduce the depth of the groove 400B to be formed.

[0058] In this embodiment, a second cushion layer 220B is provided below the first cushion layer 210B. It should be understood that the second cushion layer 220B can be any film layer as long as it can raise the height of the film layer 300B to be detected above it. In a specific example, the second cushion layer 220B can specifically be an oxide layer, and the oxide layer is, for example, a local oxide layer formed by a local oxidation process. Also, the oxide layer can be combined with the manufacturing process in the device area. For example, in some device areas, a local oxidation process is used to form an oxide layer for component isolation, or in some device areas, an oxide layer is used as a field oxide layer. At this time, an oxide layer can be formed in the monitoring area BB at the same time to form the second cushion layer 220B.

[0059] In Figure 3 and Figure 4 the structure shown, the height of the top surface of the second cushion layer 220B relative to the top surface of the substrate is, for example, and with the laying of the first cushion layer 210B and the second cushion layer 220B, the height of the film layer 300B to be detected above them can be increased by at least (that is, the height of the top surface of the first cushion layer 210B relative to the top surface of the substrate 100 is greater than or equal to ), further reducing the depth of the groove above the film layer 300B to be detected. For example, it can be reduced to less than or equal to

[0060] Next, referring to Figure 4 shown, a conductive material layer is also formed on the substrate 100. The conductive material layer fills the through hole 410A in the device area AA to form a hole field plate 510A, and the lead hole 420A is also filled with a conductive material layer to form a contact plug 520A. Also, the groove 400B in the monitoring area BB can be filled with a conductive material at the same time. In this embodiment, since the depth of the groove 400B is small, it is easy to fill the groove 400B with the conductive material layer, avoiding the formation of a concave notch in the groove 400B again, and minimizing the risk of pollutant residue.

[0061] In addition, an etching adjustment layer 600 is further formed above the film layer 300B to be detected within the monitoring region BB. When etching to form the groove 400B to expose the film layer 300B to be detected, there is a large etching selectivity between the etching adjustment layer 600 and the film layer 300B to be detected, so that the etching amount of the etching adjustment layer 600 can be precisely controlled, and the film layer 300B to be detected is prevented from being over-etched. Therefore, although the height of the film layer 300B to be detected is increased, the thickness of the film layer 300B to be detected can still be effectively ensured to be close to the thickness of the field dielectric layer 300A within the device region AA.

[0062] For the semiconductor structure described above, its manufacturing method will be described in detail below. Specifically, reference can be made to Figure 5 As shown, the manufacturing method of the semiconductor structure includes the following steps.

[0063] Step S100: Provide a substrate having a device region and a monitoring region.

[0064] Step S200: Form a gate material layer. The part of the gate material layer located within the device region is used to form the gate of the transistor device, and the part of the gate material layer located within the monitoring region is used to form the first cushion layer.

[0065] Step S300: Form a first dielectric material layer. The part of the first dielectric material layer located within the device region is used to form the field dielectric layer of the transistor device, and the part of the first dielectric material layer located within the monitoring region covers the first cushion layer to form the film layer to be detected of the monitoring structure.

[0066] Step S400: Form a second dielectric material layer to cover the device region and the monitoring region, and form a through hole in the part of the second dielectric material layer located in the device region, the bottom of the through hole exposes the field dielectric layer, and form a groove in the part of the second dielectric material layer located in the monitoring region, the bottom of the groove exposes the film layer to be detected located on the first cushion layer.

[0067] In this embodiment, the manufacturing method of the semiconductor structure further includes step 500: Deposit a conductive material layer, the conductive material layer fills the through hole to form a hole field plate, and the conductive material layer also fills the groove.

[0068] Next, in conjunction with Figures 6 - 10 Each step in the manufacturing process of the layout structure in this embodiment will be described in detail.

[0069] In step S100, specifically refer to Figure 6As shown, a substrate 100 is provided, and the substrate 100 has a device region AA and a monitoring region BB. Among them, the device region AA is used to fabricate transistor devices, and the monitoring region BB is used to fabricate a monitoring structure. In this embodiment, the field dielectric layer of the transistor devices in the device region AA can be monitored by using the monitoring structure in the monitoring region BB.

[0070] In step S200, continue to refer to Figure 6 As shown, a gate material layer is formed. The part of the gate material layer located in the device region AA is used to form the gate 200G of the transistor device, and the part of the gate material layer located in the monitoring region BB is used to form the first cushion layer 210B.

[0071] In this embodiment, before forming the gate material layer, a gate dielectric layer is further formed on the substrate in the device region AA, and the gate dielectric layer is covered when forming the gate material layer to form the gate structure of the transistor device. Also, a source 200S and a drain 200D of the transistor device are further formed in the substrate of the device region AA.

[0072] Continue to refer to Figure 6 As shown, when preparing the gate material layer, the gate material layer is also formed in the monitoring region BB to form the first cushion layer 210B, which raises the mesa of the monitoring region. In a specific example, the thickness of the gate material layer is, for example, At this time, the first cushion layer 210B correspondingly has a thickness of.

[0073] In this embodiment, before forming the gate material layer, a second cushion layer 220B can also be formed on the substrate of the monitoring region BB. The second cushion layer 220B can be formed, for example, by using a local oxidation process. Among them, the height of the top surface of the second cushion layer 220B relative to the top surface of the substrate is, for example, That is, the protruding height of the second cushion layer 220B relative to the substrate surface is, for example, Also, the first cushion layer 210B covers the second cushion layer 220B. At this time, the mesa height of the region where the second cushion layer 220B and the first cushion layer 210B are stacked is, for example, greater than or equal to

[0074] In step S300, specifically refer to Figure 7 As shown, a first dielectric material layer is formed. The part of the first dielectric material layer located in the device region AA is used to form the field dielectric layer 300A of the transistor device, and the part of the first dielectric material layer located in the monitoring region BB covers the first cushion layer 210B and is used to form the film layer 300B to be detected of the monitoring structure.

[0075] Among them, the material of the first dielectric material layer includes, for example, silicon oxide. Also, the thickness of the first dielectric material layer is, for example, At this time, the field dielectric layer 300A located in the device region AA and the film layer 300B to be detected located in the monitoring region BB also correspondingly have a thickness of.

[0076] In this embodiment, the field dielectric layer 300A located in the device region AA can also be used as a metal silicide blocking layer SAB for defining the region where metal silicide needs to be formed. As Figure 7 shown, the metal silicide blocking layer SAB (i.e., the field dielectric layer 300A) covers the top surface of the gate 200G near the drain 200D and extends to cover the sidewalls of the gate 200G to the top surface of the substrate 100, and the metal silicide blocking layer SAB also laterally extends to cover the substrate surface between the gate 200G and the drain 200D, so that the surface of the gate 200G near the source, the surface of the source 200S, and the surface of the drain 200D are exposed. Then, a metal layer can be formed, and the metal layer contacts the exposed surfaces of the gate 200G, the source 200S, and the drain 200D to perform a metal silicidation reaction to form a metal silicide layer 700. After that, the unreacted metal layer can be removed. It should be recognized that by forming the metal silicide layer 700, it is beneficial to reduce the contact resistance between the gate 200G and the contact plug, the source 200S and the contact plug, and the drain 200D and the contact plug.

[0077] In a further solution, specifically refer to Figure 8 shown, an etch adjustment layer 600 is also formed on the film layer 300B to be detected in the monitoring region BB. When etching to form a groove in the subsequent process, the etch adjustment layer 600 and the film layer 300B to be detected have a large etch selectivity (for example, the etch selectivity is greater than or equal to 10:1, and even can be greater than or equal to 20:1), improving the etching accuracy. In a specific example, the material of the film layer 300B to be detected includes silicon oxide, and the material of the etch adjustment layer 600 can include silicon nitride. Also, the thickness of the etch adjustment layer 600 is, for example,

[0078] In step S400, specifically refer to Figure 9 shown, a second dielectric material layer 400 is formed to cover the device region AA and the monitoring region BB, and a through hole 410A is formed in the part of the second dielectric material layer 400 located in the device region AA, and the bottom of the through hole 410A exposes the field dielectric layer 300A, and a groove 400B is formed in the part of the second dielectric material layer 400 located in the monitoring region BB, and the bottom of the groove 400B exposes the film layer 300B to be detected located on the first cushion layer 210B.

[0079] Wherein, the second dielectric material layer 400 may be a planarized dielectric material layer, and the maximum thickness of the second dielectric material layer 400 (corresponding to the height between the top surface of the substrate and the top surface of the second dielectric material layer) is, for example, In this way, the height requirements of components such as the hole field plate and contact plug formed in the second dielectric material layer 400 subsequently can be met.

[0080] Continue to refer to Figure 9 As shown, in this embodiment, the field dielectric layer 300A covers the top surface of the gate 200D and extends to cover the top surface of the substrate 100. The through hole 410A specifically exposes the field dielectric layer 300A on the top surface of the substrate. Therefore, the depth of the field dielectric layer 300A exposed in the through hole 410A is lower than the depth of the film layer 300B to be detected exposed in the groove 400B.

[0081] For the field dielectric layer 300A and the film layer 300B to be detected at different height positions, when etching to expose them, the film layer 300B at a higher position is often exposed in advance, resulting in a certain degree of consumption, so that the thickness of the film layer 300B to be detected is less than the thickness of the field dielectric layer 300A, thereby affecting the monitoring result. In this regard, in this embodiment, an etching adjustment layer 600 is provided in the monitoring area BB to effectively alleviate the problem that the film layer 300B to be detected in the monitoring area BB is excessively consumed.

[0082] Specifically, the process of etching to form the through hole 410A and the groove 400B may include: a first etching step and a second etching step. Among them, the first etching step is used to etch the second dielectric material layer 400 in the device area AA to form the through hole 410A, and at the same time etch the second dielectric material layer 400 in the monitoring area BB above the film layer 300B to be detected. At this time, since the thickness of the dielectric material above the film layer 300B to be detected is much smaller than the thickness of the dielectric material above the field dielectric layer 300A, the etching adjustment layer 600 will be preferentially exposed in the monitoring area BB, and the etching adjustment layer 600 will continue to be etched. Among them, in the first etching step, the etching selectivity ratio of the second dielectric material layer 400 to the etching adjustment layer 600 is, for example, greater than or equal to 5:1. In this process, the thicker second dielectric material layer 400 in the device area AA can be quickly consumed to form the through hole 410A, and at the same time, part of the etching adjustment layer 600 in the monitoring area BB is consumed. And, after the through hole 410A that meets the depth requirement is formed through the first etching step, part of the etching adjustment layer 600 can still be retained in the monitoring area BB.

[0083] Next, a second etching step is performed to remove the remaining etching adjustment layer 600 in the monitoring area BB. Since the etching adjustment layer 600 has been partially consumed in the first etching step, and the etching selectivity ratio of the etching adjustment layer 600 and the field dielectric layer 300A / the film layer to be detected 300B in the second etching step is greater than or equal to 20:1, the remaining etching adjustment layer 600 can be quickly removed, and the field dielectric layer 300A and the film layer to be detected 300B are prevented from being consumed or only a small amount is consumed.

[0084] At this point, the exposed film layer 300B to be inspected can be inspected. For example, an optical inspection device can be used to inspect the thickness of the film layer 300B to be inspected, thereby realizing thickness monitoring of the field dielectric layer 300A.

[0085] In addition, in the present embodiment, a plurality of lead holes 420A are formed in the portion of the second dielectric material layer 400 located in the device area AA, and the plurality of lead holes 420A expose the gate 200G, the source 200S and the drain 200D of the transistor device one by one, so that contact plugs can be formed in the lead holes 420A to realize electrical lead-out of the transistor device.

[0086] In step S500, please refer to Figure 10 As shown, a conductive material layer is deposited, the conductive material layer fills the through hole 410A to form a hole field plate 510A, and the conductive material layer also fills the groove. In this embodiment, the conductive material layer also fills the lead hole 420A to form a contact plug 520A.

[0087] Specifically, the method for forming the conductive material layer includes: firstly depositing a conductive material, the conductive material filling the through hole 410A, the lead hole 420A and the groove 400B. As mentioned above, since the depth of the groove 400B is small, the conductive material can easily fill the groove 400B; then, performing a chemical mechanical polishing process to remove the conductive material on the top surface of the second dielectric material layer, and retain the conductive material in the through hole 410A, the lead hole 420A and the groove 400B. It should be noted that since the conductive material can fill the groove 400B, an inner notch will not be formed in the groove 400B, and thus the polishing liquid can be prevented from remaining in the inner notch during the chemical mechanical polishing process.

[0088] In summary, in the layout structure provided by this embodiment, the gate material for the transistor device is simultaneously formed in the monitoring area to be used as the first cushion layer, raising the mesa height of the monitoring area, so that the film layer to be detected in the monitoring area can be formed at a higher position, thereby reducing the groove depth above the film layer to be detected. In this way, when forming the conductive material layer subsequently, the conductive material layer can easily fill the groove, avoiding the formation of a concave notch in the groove and resulting in pollutant residues.

[0089] In a further solution, for a film layer to be detected with a relatively high height, an etching adjustment layer can also be formed above it. There is a large etching selectivity between the etching adjustment layer and the film layer to be detected. Thus, when etching to form the groove, the etching accuracy can be effectively improved, avoiding excessive consumption of the film layer to be detected at a higher position, and making the thickness of the finally exposed film layer to be detected similar to the thickness of the field dielectric layer in the device area. In this way, when detecting the thickness of the film layer to be detected, the thickness condition of the field dielectric layer in the device area can be more accurately reflected.

[0090] Although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible variations and modifications can be made to the technical solution of the present invention by using the disclosed technical content above, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

[0091] It should also be understood that unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between the various components, elements, steps, etc. In addition, it should be recognized that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly dictates otherwise. For example, the reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. Also, the word "or" should be understood to have the definition of logical "or", rather than the definition of logical "exclusive or", unless the context clearly dictates otherwise. In addition, the implementation of the methods and / or devices in the embodiments of the present invention may include performing the selected tasks manually, automatically, or in combination.

Claims

1. A layout structure on a substrate, characterized in that, Comprising: A substrate having a device region and a monitoring region; A gate material layer formed in the device region for forming a gate in a transistor device and also formed on the substrate in the monitoring region for forming a first cushion layer; A first dielectric material layer formed in the device region for forming a field dielectric layer of a transistor device and also formed in the monitoring region and covering the first cushion layer for forming a film layer to be detected of a monitoring structure; And A second dielectric material layer covering the device region and the monitoring region, and through holes are further formed in the portion of the second dielectric material layer located in the device region, the through holes are used to fill hole field plates, and a groove is formed in the portion of the second dielectric material layer located in the monitoring region, and the bottom of the groove exposes the film layer to be detected located on the first cushion layer.

2. The layout structure on a substrate according to claim 1, characterized in that, A second cushion layer is further provided in the monitoring region, and the second cushion layer is provided below the first cushion layer and / or between the first cushion layer and the film layer to be detected.

3. The layout structure on a substrate according to claim 2, characterized in that, The first cushion layer is formed above the second cushion layer, and the height of the top surface of the first cushion layer relative to the top surface of the substrate is greater than or equal to 4. The layout structure on a substrate according to claim 1, characterized in that, The depth of the through hole is 5. The layout structure on a substrate according to claim 1, characterized in that, The depth of the groove is less than or equal to 6. The layout structure on a substrate according to claim 1, characterized in that, The width and length of the groove are both greater than or equal to 30 μm.

7. The layout structure on a substrate according to claim 1, characterized in that, A conductive material layer is further included, the conductive material layer fills the through holes to form hole field plates, and the conductive material layer also fills the groove.

8. A method for preparing a layout structure on a substrate, characterized in that, Comprising: Providing a substrate having a device region and a monitoring region; Forming a gate material layer, the portion of the gate material layer located in the device region is used to form a gate of a transistor device, and the portion of the gate material layer located in the monitoring region is used to form a first cushion layer; Forming a first dielectric material layer, the portion of the first dielectric material layer located in the device region is used to form a field dielectric layer of a transistor device, and the portion of the first dielectric material layer located in the monitoring region covers the first cushion layer for forming a film layer to be detected of a monitoring structure; Forming a second dielectric material layer covering the device region and the monitoring region, and forming through holes in the portion of the second dielectric material layer located in the device region, the bottom of the through holes exposes the field dielectric layer, and forming a groove in the portion of the second dielectric material layer located in the monitoring region, the bottom of the groove exposes the film layer to be detected located on the first cushion layer.

9. The method for preparing a layout structure on a substrate according to claim 8, characterized in that, Before forming the second dielectric material layer, it further includes: forming an etching adjustment layer on the film layer to be detected; And the method for forming the groove includes: performing a first etching step to etch the second dielectric material layer and etching to the etching adjustment layer; performing a second etching step to etch the etching adjustment layer and stopping the etching on the film layer to be detected.

10. The method for preparing a layout structure on a substrate according to claim 8, characterized in that, After forming the through holes and the groove, it further includes: Depositing a conductive material layer, the conductive material layer fills the through holes to form hole field plates, and the conductive material layer also fills the groove.

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