Electrostatic protection structure and its manufacturing method

Abstract

The present application relates to an electrostatic protection structure and a preparation method thereof, comprising a substrate, a buried layer, a first deep well, a second deep well, and a third deep well. The first deep well is provided with a well region of opposite conductivity type and a heavily doped region of the same conductivity type. The second deep well and the third deep well are provided with a well region and a heavily doped region of the same conductivity type, respectively. The first deep well, the first well region, and the second well region are floating, the first heavily doped region is connected to an electrostatic voltage, and the sixth heavily doped region is grounded. When a positive voltage is input to the electrostatic port, the first heavily doped region, the first well region, the second heavily doped region, the third heavily doped region, the second well region, and the fourth heavily doped region together constitute a transistor connected in series to achieve forward voltage withstand; when a negative voltage is input to the electrostatic port, the buried layer, the second deep well, the third well region, the fourth well region, the third deep well, the substrate, and the first deep well form a parasitic transistor, and the first deep well and the first well region form a diode. Reverse voltage withstand can be achieved through the parasitic transistor and the diode.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an electrostatic protection structure and a preparation method thereof. Background Art

[0002] As high-voltage devices are increasingly used in integrated circuits, the requirements for their anti-static (ESD) capabilities are becoming increasingly stringent. Typically, a high-voltage ESD protection structure consists of multiple low-voltage devices connected in series to meet the high-voltage requirements.

[0003] However, traditional high-voltage electrostatic protection structures usually have no problem withstanding the forward voltage, but cannot withstand high voltage in the reverse direction, resulting in inconsistency between the forward ESD protection capability and the negative ESD protection capability. Summary of the Invention

[0004] Based on this, it is necessary to provide an electrostatic protection structure and a preparation method thereof to address the problem that the positive ESD protection capability and negative ESD protection capability of the traditional high-voltage electrostatic protection structure are inconsistent.

[0005] In order to achieve the above objectives, on the one hand, the present application provides an electrostatic protection structure and a preparation method thereof.

[0006] An electrostatic protection structure, comprising:

[0007] a substrate having a first conductivity type;

[0008] a buried layer, located in the substrate, having a second conductivity type, the second conductivity type being opposite to the first conductivity type;

[0009] a first deep well, located on the upper surface of the buried layer and arranged in a floating manner, and having a first conductivity type;

[0010] a second deep well, located on the upper surface of the buried layer and partially in contact with the substrate, having a second conductivity type, the second deep well being adjacent to the first deep well and located outside the first deep well;

[0011] a third deep well, located on the buried layer and completely in contact with the substrate, having the first conductivity type, the third deep well being adjacent to the second deep well and located outside the second deep well;

[0012] wherein, the upper surface layer of the first deep well is provided with a first well region and a second well region isolated from each other and floatingly arranged, the first well region and the second well region both having the second conductivity type, the upper surface layer of the first well region is provided with a first heavily doped region and a second heavily doped region isolated from each other, the upper surface layer of the second well region is provided with a third heavily doped region and a fourth heavily doped region isolated from each other, the first heavily doped region, the second heavily doped region, the third heavily doped region and the fourth heavily doped region having the first conductivity type, the first heavily doped region is led out as a first electrode and connected to an electrostatic port, the second heavily doped region is led out as a second electrode, the third heavily doped region is led out as a third electrode and electrically connected to the second electrode, and the fourth heavily doped region is led out as a fourth electrode;

[0013] A third well region is provided on the upper surface layer of the second deep well, the third well region has the second conductivity type, and a floating fifth heavily doped region is provided on the upper surface layer of the third well region, the fifth heavily doped region has the second conductivity type;

[0014] A fourth well region is provided on the upper surface layer of the third deep well, and the fourth well region has the first conductivity type. A sixth heavily doped region is provided on the upper surface layer of the fourth well region, and the sixth heavily doped region has the first conductivity type. The sixth heavily doped region is led out and connected to the ground together with the fourth electrode.

[0015] In one embodiment, the first conductivity type is P-type, and the second conductivity type is N-type; when the electrostatic port inputs an electrostatic voltage:

[0016] The first heavily doped region, the first well region and the second heavily doped region together constitute a first PNP transistor, the third heavily doped region, the second well region and the fourth heavily doped region together constitute a second PNP transistor, and the first PNP transistor and the second PNP transistor are connected in series.

[0017] In one embodiment, when the electrostatic voltage is a positive voltage:

[0018] The first electrode serves as an emitter of the first PNP transistor, the second electrode serves as a collector of the first PNP transistor, and the first well region serves as a base of the first PNP transistor;

[0019] The third electrode serves as an emitter of the second PNP transistor, the fourth electrode serves as a collector of the second PNP transistor, and the second well region serves as a base of the second PNP transistor.

[0020] In one embodiment, when the electrostatic voltage is a negative voltage:

[0021] The first electrode serves as a collector of the first PNP transistor, the second electrode serves as an emitter of the first PNP transistor, and the first well region serves as a base of the first PNP transistor;

[0022] The third electrode is the collector of the second PNP transistor, the fourth electrode is the emitter of the second PNP transistor, and the second well region serves as the base of the second PNP transistor.

[0023] In one embodiment, the number of the first heavily doped region, the second heavily doped region, the third heavily doped region, and the fourth heavily doped region is at least two;

[0024] Among them, the multiple first heavily doped regions are isolated from each other, the multiple second heavily doped regions are isolated from each other, the multiple third heavily doped regions are isolated from each other, and the multiple fourth heavily doped regions are isolated from each other.

[0025] In one embodiment, multiple first heavily doped regions are electrically connected to serve as the first electrode, multiple second heavily doped regions are electrically connected to serve as the second electrode, multiple third heavily doped regions are electrically connected to serve as the third electrode, and multiple fourth heavily doped regions are electrically connected to serve as the fourth electrode.

[0026] In one embodiment, the upper surface layer of the first deep well is located between the first well region and the second well region and further comprises at least one fifth well region, the fifth well region being isolated from the first well region and the second well region, and the fifth well region having the second conductivity type;

[0027] Among them, the upper surface layer of each of the fifth well regions is provided with a seventh heavily doped region and an eighth heavily doped region of the first conductivity type, the seventh heavily doped region of each of the fifth well regions is electrically connected to the eighth heavily doped region in the adjacent fifth well region, the seventh heavily doped region adjacent to the first well region is electrically connected to the second heavily doped region, and the eighth heavily doped region adjacent to the second well region is electrically connected to the third heavily doped region.

[0028] In one embodiment, a plurality of sixth well regions are further provided on the upper surface layer of the first deep well, and the plurality of sixth well regions are arranged crosswise with the first well region and the second well region, and the sixth well region has the first conductivity type.

[0029] In one embodiment, the second deep well is an annular structure and surrounds the first deep well, and the third deep well is an annular structure and surrounds the second deep well.

[0030] A method for preparing an electrostatic protection structure, comprising:

[0031] providing a substrate having a first conductivity type;

[0032] forming a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type;

[0033] forming a first deep well on the upper surface of the buried layer, wherein the first deep well is disposed in a floating manner and has a first conductivity type;

[0034] forming a second deep well on the upper surface of the buried layer, wherein a portion of the second deep well contacts the substrate and has a second conductivity type, and the second deep well is adjacent to the first deep well and is located outside the first deep well;

[0035] forming a third deep well on the buried layer, wherein the third deep well is completely in contact with the substrate and has the first conductivity type, and the third deep well is adjacent to the second deep well and is located outside the second deep well;

[0036] A first well region and a second well region are formed on the upper surface layer of the first deep well, each of the first well region and the second well region being of the second conductivity type; a first heavily doped region and a second heavily doped region are formed on the upper surface layer of the first well region, each of which is isolated from the other; a third heavily doped region and a fourth heavily doped region are formed on the upper surface layer of the second well region, each of which is isolated from the other; the first heavily doped region, the second heavily doped region, the third heavily doped region, and the fourth heavily doped region are of the first conductivity type; the first heavily doped region is led out as a first electrode and connected to an electrostatic port; the second heavily doped region is led out as a second electrode; the third heavily doped region is led out as a third electrode and electrically connected to the second electrode; and the fourth heavily doped region is led out as a fourth electrode;

[0037] forming a third well region on the upper surface of the second deep well, the third well region having the second conductivity type, and forming a floating fifth heavily doped region on the upper surface of the third well region, the fifth heavily doped region having the second conductivity type;

[0038] A fourth well region is formed on the upper surface layer of the third deep well, and the fourth well region has the first conductivity type. A sixth heavily doped region is formed on the upper surface layer of the fourth well region, and the sixth heavily doped region has the first conductivity type. The sixth heavily doped region is led out and connected to the ground together with the fourth electrode.

[0039] The electrostatic protection structure and its fabrication method include a substrate of a first conductivity type, a buried layer of a second conductivity type, a first deep well of the first conductivity type, a second deep well of the second conductivity type, and a third deep well of the first conductivity type. The first deep well includes a well region of the opposite conductivity type and a heavily doped region of the same conductivity type. The second and third deep wells include a well region and a heavily doped region of the same conductivity type, respectively. The first deep well, the first well region, and the second well region are floating, the first heavily doped region is connected to an electrostatic voltage, and the sixth heavily doped region is grounded. When a positive voltage is input to the electrostatic port, the electrostatic protection structure is in a forward voltage-withstand mode, the first heavily doped region, the first well region and the second heavily doped region together constitute a first PNP transistor, the third heavily doped region, the second well region and the fourth heavily doped region together constitute a second PNP transistor, and forward voltage-withstand is performed through the first PNP transistor and the second PNP transistor, with a higher electrostatic holding voltage and less prone to latch-up effect; when a negative voltage is input to the electrostatic port, the electrostatic protection structure is in a reverse voltage-withstand mode, the buried layer, the second deep well, the third well region, the fourth well region, the third deep well, the substrate and the first deep well form a parasitic PNP transistor, the first deep well and the first well region form a diode, and reverse voltage-withstand can be performed through the parasitic PNP transistor and the diode, while the electrostatic protection structure has a higher electrostatic holding voltage and is less prone to latch-up effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 is a schematic cross-sectional view of an electrostatic protection structure in one embodiment;

[0042] Figure 2 is a schematic cross-sectional view of an electrostatic protection structure in one embodiment;

[0043] Figure 3 is a schematic cross-sectional view of an electrostatic protection structure in one embodiment;

[0044] Figure 4 is a schematic cross-sectional view of an electrostatic protection structure in one embodiment;

[0045] Figure 5 is an equivalent schematic diagram of an electrostatic protection structure in one embodiment;

[0046] Figure 6 is a schematic cross-sectional view of an electrostatic protection structure in one embodiment;

[0047] Figure 7 is a flow chart of a method for preparing an electrostatic protection structure in one embodiment;

[0048] Figure 8 FIG. 4 is a flow chart of a method for preparing an electrostatic protection structure in one embodiment. DETAILED DESCRIPTION

[0049] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0051] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, conductivity types, and / or portions, these elements, components, regions, layers, conductivity types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, conductivity type, or portion from another element, component, region, layer, conductivity type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first conductivity type may be referred to as the second conductivity type, and similarly, the second conductivity type may be referred to as the first conductivity type; the first conductivity type and the second conductivity type are different conductivity types, for example, the first conductivity type may be P-type and the second conductivity type may be N-type, or the first conductivity type may be N-type and the second conductivity type may be P-type.

[0052] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0053] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0054] Figure 1 FIG. 1 is a schematic structural diagram of an electrostatic protection structure according to an embodiment of the present invention. The electrostatic protection structure 10 includes a substrate 100 , a buried layer 200 , a first deep well 300 , a second deep well 400 , and a third deep well 500 .

[0055] In this embodiment, the substrate 100 has a first conductivity type, and an implanted buried layer 200 is formed in the substrate 100. The buried layer 200 has a second conductivity type, which is opposite to the first conductivity type. For example, in this embodiment, the first conductivity type is P-type and the second conductivity type is N-type.

[0056] In this embodiment, the first deep well 300 is located on the buried layer 200 and is disposed in a floating manner, and has a first conductivity type.

[0057] Among them, the first deep well 300 and the buried layer 200 have opposite conductivity types, and the first deep well 300 and the buried layer 200 have different doping concentration gradients, so a PN junction can be formed between the first deep well 300 and the buried layer 200. Therefore, when the electrostatic protection structure is connected to the electrostatic voltage, the first deep well 300 and the buried layer 200 can serve as one of the potential paths for electrostatic discharge.

[0058] Among them, the upper surface layer of the first deep well 300 is provided with a first well region 310 and a second well region 320 that are isolated from each other and floating. The first well region 310 and the second well region 320 both have the second conductivity type. The upper surface layer of the first well region 310 is provided with a first heavily doped region 311 and a second heavily doped region 312 that are isolated from each other. The upper surface layer of the second well region 320 is provided with a third heavily doped region 321 and a fourth heavily doped region 322 that are isolated from each other. The first heavily doped region 311, the second heavily doped region 312, the third heavily doped region 321 and the fourth heavily doped region 322 have the first conductivity type. The first heavily doped region 311 is led out as the first electrode J1 and connected to the electrostatic port H, the second heavily doped region 312 is led out as the second electrode J2, the third heavily doped region 321 is led out as the third electrode J3 and electrically connected to the second electrode J2, and the fourth heavily doped region 322 is led out as the fourth electrode J4.

[0059] The electrostatic port H is a port that requires unidirectional or bidirectional withstand voltage and is used to input an electrostatic voltage, which can be, for example, high-voltage static electricity. When unidirectional withstand voltage is required, the electrostatic protection structure of this embodiment can withstand voltage in either the forward or reverse direction. When bidirectional withstand voltage is required, the electrostatic protection structure of this embodiment can withstand voltage in both the forward and reverse directions to discharge the incoming static electricity. The fourth electrode J4 serves as the electrostatic port L of the electrostatic protection structure.

[0060] Among them, since the first deep well 300 and the first well region 310 and the second well region 320 have opposite conductivity types, and the first deep well 300 and the first well region 310 and the second well region 320 have different doping concentration gradients, a PN junction can be formed between the first deep well 300 and the first well region 310, and between the first deep well 300 and the second well region 320. Therefore, when an electrostatic voltage is input to the electrostatic port H, between the first well region 310 and the first heavily doped region 311, and between the first well region 310 and the second heavily doped region 312 can serve as one of the potential paths for electrostatic discharge.

[0061] Among them, since the first well region 310 and the first heavily doped region 311 and the second heavily doped region 312 have opposite conductivity types, and the first well region 310 and the first heavily doped region 311 and the second heavily doped region 312 have different doping concentration gradients, a PN junction can be formed between the first well region 310 and the first heavily doped region 311, and a PN junction can be formed between the first well region 310 and the second heavily doped region 312, and the voltage bias of the PN junction between the first well region 310 and the first heavily doped region 311 and the PN junction formed between the first well region 310 and the second heavily doped region 312 are opposite, so when the electrostatic voltage is input to the electrostatic port H, the first well region 310 and the first heavily doped region 311, and the first well region 310 and the second heavily doped region 312 can serve as one of the potential paths for electrostatic discharge.

[0062] Among them, since the second well region 320 and the third heavily doped region 321 and the fourth heavily doped region 322 have opposite conductivity types, and the second well region 320 and the third heavily doped region 321 and the fourth heavily doped region 322 have different doping concentration gradients, a PN junction can be formed between the second well region 320 and the third heavily doped region 321, and a PN junction can be formed between the second well region 320 and the fourth heavily doped region 322, and the voltage bias of the PN junction between the second well region 320 and the third heavily doped region 321 and the PN junction formed between the second well region 320 and the fourth heavily doped region 322 are opposite, so when the electrostatic voltage is input to the electrostatic port H, the second well region 320 and the third heavily doped region 321, and the second well region 320 and the fourth heavily doped region 322 can serve as one of the potential paths for electrostatic discharge.

[0063] Among them, since the first heavily doped region 311 is led out as the first electrode J1 and connected to the electrostatic port H, the second heavily doped region 312 is led out as the second electrode J2, the third heavily doped region 321 is led out as the third electrode J3 and electrically connected to the second electrode J2, and the fourth heavily doped region 322 is led out as the fourth electrode J4, therefore, when the electrostatic port H inputs an electrostatic voltage and the PN junction between the first well region 310 and the second heavily doped region 312 is broken down, current is conducted between the third electrode J3 and the second electrode J2, and the first heavily doped region 311, the first well region 310, the second heavily doped region 312, the third heavily doped region 321, the second well region 320 and the fourth heavily doped region 322 form potential electrostatic discharge paths with different voltage biases.

[0064] In some embodiments, as Figure 2 As shown, the number of the first heavily doped region 311, the second heavily doped region 312, the third heavily doped region 321 and the fourth heavily doped region 322 are all at least two ( Figure 2 (For example, the number of each is two), the multiple first heavily doped regions 311 are isolated from each other, the multiple second heavily doped regions 312 are isolated from each other, the multiple third heavily doped regions 321 are isolated from each other, and the multiple fourth heavily doped regions 322 are isolated from each other. Among them, the multiple first heavily doped regions 311 are electrically connected to serve as the first electrode J1, the multiple second heavily doped regions 312 are electrically connected to serve as the second electrode J2, the multiple third heavily doped regions 321 are electrically connected to serve as the third electrode J3, and the multiple fourth heavily doped regions 322 are electrically connected to serve as the fourth electrode J4. Thus, each electrode corresponds to multiple heavily doped regions, which is beneficial to improving the electrostatic discharge capability of each electrode during the electrostatic protection process.

[0065] Among them, the number of the first heavily doped region 311, the second heavily doped region 312, the third heavily doped region 321 and the fourth heavily doped region 322 can be set according to actual needs, for example, according to the actual size of the electrostatic voltage. When the electrostatic voltage is high, a larger number can be set within the range that the product size can bear. When the electrostatic voltage is small, a smaller number can be set.

[0066] In some embodiments, when the first conductivity type is P-type and the second conductivity type is N-type, and an electrostatic voltage is input to the electrostatic port H, the first heavily doped region 311, the first well region 310, and the second heavily doped region 312 together form a first PNP transistor, and the third heavily doped region 321, the second well region 320, and the fourth heavily doped region 322 together form a second PNP transistor. The first and second PNP transistors are arranged in series. Using PNP transistors for ESD protection can achieve a higher sustain voltage.

[0067] Furthermore, when a positive voltage is input to the electrostatic port H, the first electrode J1 is the emitter of the first PNP transistor, the second electrode J2 is the collector of the first PNP transistor, the first well region 310 is the floating base of the first PNP transistor, the third electrode J3 is the emitter of the second PNP transistor, the fourth electrode J4 is the collector of the second PNP transistor, and the second well region 320 is the floating base of the second PNP transistor. When a positive voltage is input to the electrostatic port H, the electrostatic protection structure is in a forward withstand voltage mode. The emitter and the floating base of the first PNP transistor are forward biased, causing the floating base and emitter of the first PNP transistor to breakdown. The avalanche current caused by the breakdown passes through the emitter of the second PNP transistor, thereby connecting the first PNP transistor in series to the second PNP transistor, forming a main electrostatic discharge path for forward electrostatic protection, thereby meeting the high-voltage withstand requirement.

[0068] Furthermore, when a negative voltage is input to the electrostatic port H, the first electrode J1 is the collector of the first PNP transistor, the second electrode J2 is the emitter of the first PNP transistor, the third electrode J3 is the collector of the second PNP transistor, and the fourth electrode J4 is the emitter of the second PNP transistor.

[0069] Therefore, when different electrostatic voltages are input, the collector and emitter of the first PNP transistor and the second PNP transistor can be interchanged, making it easier to achieve consistency in bidirectional withstand voltage.

[0070] It should be noted that in other embodiments, the present invention is not limited to forming a PNP transistor, and other layer structures may be provided to form electrostatic protection structures of other device types, such as forming a PMOS device, specifically, a GDPMOS device.

[0071] In some embodiments, as Figure 3 As shown, the upper surface layer of the first deep well 300 is located between the first well region 310 and the second well region 320 and is further provided with at least one fifth well region 330 ( Figure 3 exist Figure 2 On the basis of the shown embodiment, a fifth well region 330 is added), the fifth well region 330 is isolated from the first well region 310 and the second well region 320, and the fifth well region 330 has the second conductivity type; the upper surface layer of each fifth well region 330 is provided with a seventh heavily doped region 331 and an eighth heavily doped region of the first conductivity type, the seventh heavily doped region 331 of each fifth well region 330 is electrically connected to the eighth heavily doped region 332 in the adjacent fifth well region 330, the seventh heavily doped region 331 adjacent to the first well region 310 is electrically connected to the second heavily doped region 312, and the eighth heavily doped region 332 adjacent to the second well region 320 is electrically connected to the third heavily doped region 321. Thus, potential electrostatic discharge paths with different voltage biases are formed between the first heavily doped region 311, the first well region 310, the second heavily doped region 312, the seventh heavily doped region 331, the fifth well region 330, the eighth heavily doped region 332, the third heavily doped region 321, the second well region 320 and the fourth heavily doped region 322.

[0072] When the first conductivity type is P type, the second conductivity type is N type, and the electrostatic port H inputs an electrostatic voltage, the first heavily doped region 311, the first well region 310 and the second heavily doped region 312 together constitute a first PNP transistor, the third heavily doped region 321, the second well region 320 and the fourth heavily doped region 322 together constitute a second PNP transistor, the seventh heavily doped region 331, the fifth well region 330 and the eighth heavily doped region 332 together constitute a third PNP transistor, and the first PNP transistor, multiple third PNP transistors and the second PNP transistor are arranged in series with each other. Among them, when the electrostatic port H inputs a positive voltage, the electrostatic protection structure is in a forward voltage withstand mode, and the emitter of the first PNP transistor and the floating base are forward biased, causing the floating base and emitter of the first PNP transistor to break down, and the avalanche current caused by the breakdown passes through the emitter of the third PNP transistor, and the emitter of the third PNP transistor and the floating base are forward biased, causing the floating base and emitter of the second PNP transistor to break down, and the avalanche current caused by the breakdown passes through the emitter of the second PNP transistor, thereby realizing the first PNP transistor being connected in series to the third PNP transistor, and the third PNP transistor being connected in series to the second PNP transistor, forming the main electrostatic discharge path of the forward electrostatic protection, further improving the electrostatic voltage withstand capability, and at the same time having a higher electrostatic holding voltage, and not prone to latch-up effect.

[0073] The number of the third PNP transistors can be set according to different levels of the electrostatic voltage. The higher the level of the electrostatic voltage, the more third PNP transistors can be set to solve the electrostatic protection of a higher level.

[0074] In some embodiments, as Figure 4 As shown, the upper surface layer of the first deep well 300 is further provided with a plurality of sixth well regions 340 , which are arranged crosswise with the first well region 310 and the second well region 320 , and the sixth well region 340 has the first conductivity type.

[0075] The sixth well region 340 is arranged crosswise with the first well region 310 and the second well region 320, and has an opposite conductivity type and the same doping concentration gradient as the first well region 310 and the second well region 320. Thus, the sixth well region 340 can be used to separate the first well region 310 and the second well region 320, thereby preventing the first well region 310 and the second well region 320 from affecting each other during the electrostatic withstand voltage test. Furthermore, the sixth well region 340, which is close to the second deep well 400, is located between the first well region 310 and the third well region. Since the sixth well region 340 has an opposite conductivity type and the same doping concentration gradient as the first well region 310 and the second well region 320, the sixth well region 340 can be used to separate the first well region 310 from the third well region, thereby preventing the first well region 310 and the third well region from affecting each other during the electrostatic withstand voltage test.

[0076] In this embodiment, the second deep well 400 is located on the upper surface of the buried layer 200 and partially contacts the substrate 100 . It has the second conductivity type and is adjacent to the first deep well 300 and located outside the first deep well 300 .

[0077] Among them, the second deep well 400 is located on the upper surface of the buried layer 200 and a part of the area is in contact with the substrate 100, and is adjacent to the first deep well 300. Since the second deep well 400 and the buried layer 200 have opposite conductivity types and different doping concentration gradients from the first deep well 300 and the substrate 100, a PN junction can be formed between the second deep well 400 and the buried layer 200 and the substrate 100, and a PN junction can be formed between the second deep well 400 and the buried layer 200 and the first deep well 300. With the input of the voltage at the electrical port H, the second deep well 400 and the buried layer 200 and the substrate 100, and the second deep well 400 and the buried layer 200 and the first deep well 300 can become one of the potential paths for electrostatic discharge; wherein, the second deep well 400 is located between the first deep well 300 and the third deep well 500, and has an opposite conductivity type to the first deep well 300 and the third deep well 500, so the second deep well 400 can be used to isolate the first deep well 300 and the third deep well 500.

[0078] The upper surface of the second deep well 400 is provided with a third well region 410, which has the second conductivity type. A floating fifth heavily doped region 411 is also provided on the upper surface of the third well region 410, which has the second conductivity type. The fifth heavily doped region 411 is floating and leads to an isolation port that serves as an electrostatic protection structure. Exemplarily, the sidewall width of the third well region 410 is smaller than the sidewall width of the second deep well 400, thereby isolating the third well region 410 from the adjacent first deep well 300 and third deep well 500.

[0079] In some embodiments, the second deep well 400 is a ring structure and surrounds the periphery of the first deep well 300, and the third deep well 500 is a ring structure and surrounds the periphery of the second deep well 400, so that the second deep well 400 and the third deep well 500 form a double ring structure. While forming a discharge path for electrostatic discharge with the internal first deep well 300, it can also effectively isolate the mutual influence between wells of the same conductive type, effectively improving the electrostatic protection performance.

[0080] In this embodiment, the third deep well 500 is located on the buried layer 200 and in contact with the substrate 100 . It has the first conductivity type. The third deep well 500 is adjacent to the second deep well 400 and is located outside the second deep well 400 .

[0081] Among them, the third deep well 500 is located on the buried layer 200 and is completely in contact with the substrate 100, and is adjacent to the second deep well 400. Since the third deep well 500 and the substrate 100 have opposite conductivity types to the second deep well 400 and the buried layer 200, a PN junction can be formed between the third deep well 500 and the substrate 100 and the second deep well 400 and the buried layer 200. Through the input of the electrostatic port H voltage, the third deep well 500 and the substrate 100 and the second deep well 400 and the buried layer 200 can become one of the potential paths for electrostatic discharge.

[0082] A fourth well region 510 is provided on the upper surface of the third deep well 500. The fourth well region 510 has the first conductivity type. A sixth heavily doped region 511 is provided on the upper surface of the fourth well region 510. The sixth heavily doped region 511 also has the first conductivity type. The sixth heavily doped region 511 is connected to the ground with the fourth electrode J4, that is, the sixth heavily doped region 511 is connected to the substrate with the fourth electrode J4. Exemplarily, the sidewall width of the fourth well region 510 is smaller than the sidewall width of the third deep well 500, thereby separating the third deep well 500 from the adjacent second deep well 400.

[0083] Among them, since the fourth well region 510, the third deep well 500 and the substrate 100 have opposite conductivity types and different doping concentration gradients on the one hand and the buried layer 200, the second deep well 400 and the third well region 410, a PN junction can be formed between the fourth well region 510, the third deep well 500 and the substrate 100 and the buried layer 200, the second deep well 400 and the third well region 410. Since the buried layer 200, the second deep well 400, the third well region 410 and the first deep well 300 have opposite conductivity types and different doping concentration gradients on the other hand, a PN junction is formed between the buried layer 200, the second deep well 400, the third well region 410 and the first deep well 300.

[0084] Please see for assistance Figure 5 The following takes the electrostatic protection structure including two PNP transistors as an example to explain the process of bidirectional electrostatic protection of the electrostatic protection structure:

[0085] When a positive voltage is input to the electrostatic port H, the electrostatic protection structure is in a forward withstand voltage mode: a PN junction is formed between the first heavily doped region 311 and the floating first well region 310 (see auxiliary reference). Figure 5 PN1 in the figure is in a forward biased state, and a PN junction is formed between the first well region 310 and the second heavily doped region (see auxiliary reference). Figure 5 PN2 in the reverse bias state, the PN junction formed between the third heavily doped region 321 and the floating second well region 320 (see auxiliary reference Figure 5 PN3 in the figure is in a forward biased state, and a PN junction is formed between the second well region 320 and the fourth heavily doped region (see auxiliary reference). Figure 5 PN4 in the transistor is in a reverse biased state. When the PN junction formed between the first well region 310 and the second heavily doped region is broken down, the first heavily doped region 311, the first well region 310 and the second heavily doped region 312 together constitute a first PNP transistor Q1, and the third heavily doped region 321, the second well region 320 and the fourth heavily doped region 322 together constitute a second PNP transistor Q2. The forward withstand voltage is provided by the first PNP transistor Q1 and the second PNP transistor Q2, thereby having a higher electrostatic holding voltage and being less susceptible to latch-up effect.

[0086] When the electrostatic port H is connected to a negative voltage, the electrostatic protection structure is in a negative withstand voltage mode: the sixth heavily doped region 511 connected to the ground is equivalent to being connected to a positive voltage, so that the PN junction formed between the fourth well region 510, the third deep well 500 and the substrate 100 and the buried layer 200, the second deep well 400 and the third well region 410 (please refer to the auxiliary Figure 5 PN5 in the forward bias state, so that the PN junction between the buried layer 200, the second deep well 400, the third well region 410 and the first deep well 300 (see auxiliary reference Figure 5 PN6 in the first well) is in a reverse bias state, so that the PN junction between the first deep well 300 and the first well region 310 (see auxiliary reference) Figure 5 PN7 in the second deep well 400 is in a forward biased state, and the PN junction withstand voltage between the second deep well 400, the buried layer 200 and the first deep well 300 is very high, so it will not be lower than the breakdown voltage of the floating base and emitter of the second PNP transistor Q2. Therefore, the buried layer 200, the second deep well 400, and the third well region 410 are equivalent to the floating base, the fourth well region 510, the third deep well 500 and the substrate 100 are equivalent to the emitter, the first deep well 300 is equivalent to the collector, and the buried layer 200, the second deep well 400, the third well region 410 are equivalent to the collector. The triple well region 410, the fourth well region 510, the third deep well 500, the substrate 100 and the first deep well 300 form a parasitic PNP transistor Q3; the first deep well 300 is equivalent to the anode of the diode, and the first well region 310 is equivalent to the cathode of the diode D. The first deep well 300 and the first well region 310 form a diode D, thereby enabling reverse voltage resistance through the parasitic PNP transistor Q3 and the diode D, while enabling the electrostatic protection structure to have a higher electrostatic holding voltage and making it less prone to latch-up effects.

[0087] Therefore, when the ESD protection structure is in the forward withstand voltage mode, it utilizes the capability of the first PNP transistor Q1 and the second PNP transistor Q2 in series for forward withstand voltage, resulting in a higher ESD holding voltage and less prone to latch-up. When the ESD protection structure is in the negative withstand voltage mode, it also utilizes the capability of the first PNP transistor Q1 and the second PNP transistor Q2 in series, as well as the parallel high-voltage withstand PNP transistor Q3 and diode D, resulting in a higher ESD holding voltage and less prone to latch-up. This allows the ESD protection structure to achieve bidirectional withstand voltage consistency.

[0088] The electrostatic protection structure provided in this embodiment includes a first conductivity type substrate 100, a second conductivity type buried layer 200, a first conductivity type first deep well 300, a second conductivity type second deep well 400, and a first conductivity type third deep well 500. The first deep well 300 is provided with a well region of opposite conductivity type and a heavily doped region of the same conductivity type. The second deep well 400 and the third deep well 500 are provided with a well region and a heavily doped region of the same conductivity type, respectively. The first deep well 300, the first well region 310, and the second well region 320 are floating, the first heavily doped region 311 is connected to an electrostatic voltage, and the sixth heavily doped region 511 is grounded. When a positive voltage is input to the electrostatic port H, the electrostatic protection structure is in a forward withstand voltage mode. The first heavily doped region 311, the first well region 310, and the second heavily doped region 312 together constitute a first PNP transistor Q1. The third heavily doped region 321, the second well region 320, and the fourth heavily doped region 322 together constitute a second PNP transistor Q2. The forward withstand voltage is achieved through the first PNP transistor Q1 and the second PNP transistor Q2, which has a higher electrostatic holding voltage and is less likely to cause latch-up effects. When a negative voltage is input to the electrostatic port H, the electrostatic protection structure is in a reverse withstand voltage mode. The buried layer 200, the second deep well 400, the third well region 410, the fourth well region 510, the third deep well 500, the substrate 100, and the first deep well 300 form a parasitic PNP transistor. The first deep well 300 and the first well region 310 form a diode. The parasitic PNP transistor and the diode can perform reverse withstand voltage, while making the electrostatic protection structure have a higher electrostatic holding voltage and less likely to cause latch-up effects. As a result, the electrostatic protection structure can achieve bidirectional withstand voltage consistency.

[0089] Figure 6 FIG1 is a schematic diagram of an electrostatic protection structure according to an embodiment of the present invention. Based on the electrostatic protection structure according to the above embodiment, the electrostatic protection structure according to the present embodiment further includes a first isolation structure, a second isolation structure, a third isolation structure and a fourth isolation structure.

[0090] In this embodiment, the first isolation structure 600 is located on the upper surface of the first deep well 300 and extends from the upper surface of the first deep well 300 to the first well region 310. The first isolation structure 600 is cross-arranged with the first heavily doped region 311 and the second heavily doped region 312, thereby isolating the first heavily doped region 311 and the second heavily doped region 312 to avoid mutual influence between the first heavily doped region 311 and the second heavily doped region 312 during the electrostatic discharge process.

[0091] In this embodiment, the second isolation structure 700 is located on the upper surface of the first deep well 300 and extends from the upper surface of the first deep well 300 to the second well region 320. The second isolation structure 700 is cross-arranged with the third heavily doped region 321 and the fourth heavily doped region 322, thereby isolating the third heavily doped region 321 and the fourth heavily doped region 322 to avoid mutual influence between the third heavily doped region 321 and the fourth heavily doped region 322 during the electrostatic discharge process.

[0092] In this embodiment, the third isolation structure 800 is located on the upper surface layer of the second deep well 400 and the third deep well 500, and is located between the fifth heavily doped region 411 and the sixth heavily doped region 511, thereby isolating the fifth heavily doped region 411 and the sixth heavily doped region 511, and avoiding the fifth heavily doped region 411 and the sixth heavily doped region 511 from affecting each other during the electrostatic discharge process.

[0093] In this embodiment, the fourth isolation structure 910 is located on the upper surface layer of the fourth well region 510, and is located between the first heavily doped region 311 and the fifth heavily doped region 411, and between the fourth heavily doped region 322 and the fifth heavily doped region 411, thereby isolating the first heavily doped region 311 from the fifth heavily doped region 411, avoiding isolation of the fourth heavily doped region 322 from the fifth heavily doped region 411, and further improving the isolation performance of the electrostatic protection structure.

[0094] In this embodiment, the fifth isolation structure 920 is located on the upper surface of the third deep well 500 and is used to isolate the electrostatic protection structure from other devices, thereby further improving the isolation performance of the electrostatic protection structure.

[0095] In one embodiment, the first isolation structure 600 , the second isolation structure 700 , the third isolation structure 800 , the fourth isolation structure 910 , and the fifth isolation structure 920 may be shallow trench isolation structures.

[0096] The electrostatic protection structure in this embodiment can effectively improve the isolation performance of the device through the first isolation structure 600 , the second isolation structure 700 , the third isolation structure 800 , the fourth isolation structure 910 and the fifth isolation structure 920 .

[0097] This embodiment also provides a method for preparing an electrostatic protection structure, which is used to prepare the electrostatic protection structure described in the above embodiment. Figure 7 As shown, the preparation method includes:

[0098] Step 110: Provide a substrate, wherein the substrate has a first conductivity type.

[0099] Step 120: Form a buried layer in the substrate, wherein the buried layer has a second conductivity type opposite to the first conductivity type.

[0100] Step 130: forming a first deep well on the upper surface of the buried layer, wherein the first deep well is floating and has a first conductivity type.

[0101] Step 140: forming a second deep well on the upper surface of the buried layer, wherein a portion of the second deep well contacts the substrate and has the second conductivity type, and the second deep well is adjacent to the first deep well and is located outside the first deep well.

[0102] Step 150 : forming a third deep well on the buried layer, wherein the third deep well is completely in contact with the substrate and has the first conductivity type. The third deep well is adjacent to the second deep well and is located outside the second deep well.

[0103] Step 160: A first well region and a second well region that are isolated from each other and floating are formed on the upper surface layer of the first deep well, the first well region and the second well region both having the second conductivity type, a first heavily doped region and a second heavily doped region that are isolated from each other are formed on the upper surface layer of the first well region, and a third heavily doped region and a fourth heavily doped region that are isolated from each other are formed on the upper surface layer of the second well region.

[0104] Among them, the first heavily doped region, the second heavily doped region, the third heavily doped region and the fourth heavily doped region have the first conductivity type, the first heavily doped region is led out as a first electrode and connected to the electrostatic port, the second heavily doped region is led out as a second electrode, the third heavily doped region is led out as a third electrode and electrically connected to the second electrode, and the fourth heavily doped region is led out as a fourth electrode.

[0105] Step 170: forming a third well region on the upper surface of the second deep well, the third well region having the second conductivity type, and forming a floating fifth heavily doped region on the upper surface of the third well region, the fifth heavily doped region having the second conductivity type.

[0106] Step 180: Form a fourth well region on the upper surface layer of the third deep well, the fourth well region has the first conductivity type, form a sixth heavily doped region on the upper surface layer of the fourth well region, the sixth heavily doped region has the first conductivity type, and the sixth heavily doped region is led out and connected to the ground together with the fourth electrode.

[0107] Among them, steps 110 to 180 are used to prepare Figure 1-Figure 2 For the electrostatic protection structure described in the embodiment, please refer to Figure 1-Figure 2 The relevant description in the embodiments. The method of "forming" can adopt the existing preparation method, which is not limited here.

[0108] Among them, steps 130 to 150 can be performed simultaneously or sequentially, and steps 160 to 180 can be performed simultaneously or sequentially.

[0109] The preparation method provided in this embodiment can prepare an electrostatic protection structure capable of bidirectional voltage resistance, while also enabling the electrostatic protection structure to have a higher electrostatic holding voltage and be less prone to latch-up effects.

[0110] In some embodiments, the preparation method further comprises:

[0111] Step 190: At least one fifth well region is formed on the upper surface layer of the first deep well and between the first well region and the second well region, the fifth well region is isolated from the first well region and the second well region respectively, the fifth well region has the second conductivity type, and a seventh heavily doped region and an eighth heavily doped region of the first conductivity type are formed on the upper surface layer of each fifth well region, the seventh heavily doped region of each fifth well region is electrically connected to the eighth heavily doped region in the adjacent fifth well region, the seventh heavily doped region adjacent to the first well region is electrically connected to the second heavily doped region, and the eighth heavily doped region adjacent to the second well region is electrically connected to the third heavily doped region.

[0112] Wherein, step 190 is used to prepare Figure 3 For the electrostatic protection structure described in the embodiment, please refer to Figure 3 The relevant description in the embodiments. The method of "forming" can adopt the existing preparation method, which is not limited here.

[0113] In some embodiments, the preparation method further comprises:

[0114] Step 200 : forming a plurality of sixth well regions on the upper surface layer of the first deep well, wherein the plurality of sixth well regions are arranged crosswise with the first well region and the second well region, and the sixth well regions have the first conductivity type.

[0115] Wherein, step 200 is used to prepare Figure 4 For the electrostatic protection structure described in the embodiment, please refer to Figure 4 Related descriptions in the embodiments. Step 200 can be performed simultaneously with or sequentially with steps 130 to 150 in the above embodiments. The "forming" method can adopt existing preparation methods and is not limited here.

[0116] In one embodiment, if Figure 8 As shown, the preparation method also includes:

[0117] Step 210: forming a first isolation structure on the upper surface of the first deep well, wherein the first isolation structure extends from the upper surface of the first deep well to the first well region, and the first isolation structure is cross-arranged with the first heavily doped region and the second heavily doped region.

[0118] Step 220: forming a second isolation structure on the upper surface of the second deep well, wherein the second isolation structure extends from the upper surface of the first deep well to the second well region, and the second isolation structure is cross-arranged with the third heavily doped region and the fourth heavily doped region.

[0119] Step 230 : forming a third isolation structure on the upper surface layer of the second deep well and the third deep well, wherein the third isolation structure is located between the fifth heavily doped region and the sixth heavily doped region.

[0120] Step 240 : forming a fourth isolation structure on the upper surface of the fourth well region, wherein the fourth isolation structure is located between the first heavily doped region and the fifth heavily doped region, and between the fourth heavily doped region and the fifth heavily doped region.

[0121] Step 250 : Form a fifth isolation structure on the upper surface layer of the third deep well.

[0122] Wherein, step 210 is used to prepare Figure 6 For the electrostatic protection structure described in the embodiment, please refer to Figure 6 Related description in the embodiment. Steps 210 to 250 can be performed simultaneously or sequentially. The method of "forming" can adopt existing preparation methods and is not limited here.

[0123] In the description of this specification, reference to the terms "in some embodiments," "other embodiments," etc., means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0124] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0125] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. An electrostatic protection structure, characterized in that: include: a substrate having a first conductivity type; a buried layer, located in the substrate, having a second conductivity type, the second conductivity type being opposite to the first conductivity type; a first deep well, located on the upper surface of the buried layer and arranged in a floating manner, and having a first conductivity type; a second deep well, located on the upper surface of the buried layer and partially in contact with the substrate, having a second conductivity type, the second deep well being adjacent to the first deep well and located outside the first deep well; a third deep well, located on the buried layer and completely in contact with the substrate, having the first conductivity type, the third deep well being adjacent to the second deep well and located outside the second deep well; wherein, the upper surface layer of the first deep well is provided with a first well region and a second well region isolated from each other and floatingly arranged, the first well region and the second well region both having the second conductivity type, the upper surface layer of the first well region is provided with a first heavily doped region and a second heavily doped region isolated from each other, the upper surface layer of the second well region is provided with a third heavily doped region and a fourth heavily doped region isolated from each other, the first heavily doped region, the second heavily doped region, the third heavily doped region and the fourth heavily doped region having the first conductivity type, the first heavily doped region is led out as a first electrode and connected to an electrostatic port, the second heavily doped region is led out as a second electrode, the third heavily doped region is led out as a third electrode and electrically connected to the second electrode, and the fourth heavily doped region is led out as a fourth electrode; A third well region is provided on the upper surface layer of the second deep well, the third well region has the second conductivity type, and a floating fifth heavily doped region is provided on the upper surface layer of the third well region, the fifth heavily doped region has the second conductivity type; A fourth well region is provided on the upper surface of the third deep well, the fourth well region has the first conductivity type, a sixth heavily doped region is provided on the upper surface of the fourth well region, the sixth heavily doped region has the first conductivity type, the sixth heavily doped region is led out and connected to the ground together with the fourth electrode; The electrostatic protection structure also includes a first isolation structure and a second isolation structure. The first isolation structure is located on the upper surface of the first deep well and penetrates from the upper surface of the first deep well to the first well region. The first isolation structure is cross-arranged with the first heavily doped region and the second heavily doped region; the second isolation structure is located on the upper surface of the first deep well and penetrates from the upper surface of the first deep well to the second well region. The second isolation structure is cross-arranged with the third heavily doped region and the fourth heavily doped region; the first isolation structure and the second isolation structure are shallow trench isolation structures.

2. The electrostatic protection structure according to claim 1, characterized in that: The first conductivity type is P type, and the second conductivity type is N type; when the electrostatic port inputs an electrostatic voltage: The first heavily doped region, the first well region and the second heavily doped region together constitute a first PNP transistor, the third heavily doped region, the second well region and the fourth heavily doped region together constitute a second PNP transistor, and the first PNP transistor and the second PNP transistor are connected in series.

3. The electrostatic protection structure according to claim 2, characterized in that: When the electrostatic voltage is positive: The first electrode serves as an emitter of the first PNP transistor, the second electrode serves as a collector of the first PNP transistor, and the first well region serves as a base of the first PNP transistor; The third electrode serves as an emitter of the second PNP transistor, the fourth electrode serves as a collector of the second PNP transistor, and the second well region serves as a base of the second PNP transistor.

4. The electrostatic protection structure according to claim 2, characterized in that: When the electrostatic voltage is negative: The first electrode serves as a collector of the first PNP transistor, the second electrode serves as an emitter of the first PNP transistor, and the first well region serves as a base of the first PNP transistor; The third electrode is the collector of the second PNP transistor, the fourth electrode is the emitter of the second PNP transistor, and the second well region serves as the base of the second PNP transistor.

5. The electrostatic protection structure according to claim 1, wherein: The number of the first heavily doped region, the second heavily doped region, the third heavily doped region, and the fourth heavily doped region is at least two; Among them, the multiple first heavily doped regions are isolated from each other, the multiple second heavily doped regions are isolated from each other, the multiple third heavily doped regions are isolated from each other, and the multiple fourth heavily doped regions are isolated from each other.

6. The electrostatic protection structure according to claim 5, characterized in that: Multiple first heavily doped regions are electrically connected to serve as the first electrodes, multiple second heavily doped regions are electrically connected to serve as the second electrodes, multiple third heavily doped regions are electrically connected to serve as the third electrodes, and multiple fourth heavily doped regions are electrically connected to serve as the fourth electrodes.

7. The electrostatic protection structure according to claim 1, characterized in that: The upper surface layer of the first deep well is located between the first well region and the second well region and further comprises at least one fifth well region, the fifth well region being isolated from the first well region and the second well region, and the fifth well region having the second conductivity type; Among them, the upper surface layer of each of the fifth well regions is provided with a seventh heavily doped region and an eighth heavily doped region of the first conductivity type, the seventh heavily doped region of each of the fifth well regions is electrically connected to the eighth heavily doped region in the adjacent fifth well region, the seventh heavily doped region adjacent to the first well region is electrically connected to the second heavily doped region, and the eighth heavily doped region adjacent to the second well region is electrically connected to the third heavily doped region.

8. The electrostatic protection structure according to claim 1, wherein: A plurality of sixth well regions are further provided on the upper surface layer of the first deep well. The plurality of sixth well regions are arranged crosswise with the first well region and the second well region. The sixth well regions have the first conductivity type.

9. The electrostatic protection structure according to claim 1, characterized in that: The second deep well is an annular structure and surrounds the periphery of the first deep well. The third deep well is an annular structure and surrounds the periphery of the second deep well.

10. A method for preparing an electrostatic protection structure, characterized in that: include: providing a substrate having a first conductivity type; forming a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type; forming a first deep well on the upper surface of the buried layer, wherein the first deep well is disposed in a floating manner and has a first conductivity type; forming a second deep well on the upper surface of the buried layer, wherein a portion of the second deep well contacts the substrate and has a second conductivity type, and the second deep well is adjacent to the first deep well and is located outside the first deep well; forming a third deep well on the buried layer, wherein the third deep well is completely in contact with the substrate and has the first conductivity type, and the third deep well is adjacent to the second deep well and is located outside the second deep well; A first well region and a second well region are formed on the upper surface layer of the first deep well, each of the first well region and the second well region being of the second conductivity type; a first heavily doped region and a second heavily doped region are formed on the upper surface layer of the first well region, each of which is isolated from the other; a third heavily doped region and a fourth heavily doped region are formed on the upper surface layer of the second well region, each of which is isolated from the other; the first heavily doped region, the second heavily doped region, the third heavily doped region, and the fourth heavily doped region are of the first conductivity type; the first heavily doped region is led out as a first electrode and connected to an electrostatic port; the second heavily doped region is led out as a second electrode; the third heavily doped region is led out as a third electrode and electrically connected to the second electrode; and the fourth heavily doped region is led out as a fourth electrode; forming a third well region on the upper surface of the second deep well, the third well region having the second conductivity type, and forming a floating fifth heavily doped region on the upper surface of the third well region, the fifth heavily doped region having the second conductivity type; forming a fourth well region on an upper surface layer of the third deep well, the fourth well region having the first conductivity type; forming a sixth heavily doped region on an upper surface layer of the fourth well region, the sixth heavily doped region having the first conductivity type, the sixth heavily doped region being led out and connected to the ground together with the fourth electrode; forming a first isolation structure on the upper surface of the first deep well, wherein the first isolation structure extends from the upper surface of the first deep well to the first well region, and the first isolation structure is arranged crosswise with the first heavily doped region and the second heavily doped region; A second isolation structure is formed on the upper surface of the second deep well. The second isolation structure extends from the upper surface of the first deep well to the second well region. The second isolation structure is cross-arranged with the third heavily doped region and the fourth heavily doped region. The first isolation structure and the second isolation structure are shallow trench isolation structures.

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