Structure, manufacturing method and power device of mosfet, electronic device

Abstract

A MOSFET structure, manufacturing method, power device, and electronic device are disclosed, belonging to the field of semiconductor technology. The MOSFET comprises an epitaxial layer, a channel layer, an active layer, a gate structure, a first trench, a first conductive layer, a first dielectric layer, metal pillars, a floating junction, and a first insulating layer. The channel layer is disposed on the upper surface of the epitaxial layer. The active layer is disposed on the upper surface of the channel layer. The gate structure extends longitudinally downwards from the upper surface of the active layer through the active layer and the channel layer. The first trench extends longitudinally downwards from the upper surface of the active layer through the active layer and the channel layer. The first conductive layer covers the inner surface of the sidewalls of the first trench. The first dielectric layer covers the inner surface of the sidewalls of the first conductive layer. The metal pillars fill the interior of the first dielectric layer. The floating junction is located at the bottom of the first trench. The first insulating layer is located at the top of the first trench. This design reduces the internal resistance of the MOSFET and improves its longitudinal and lateral breakdown voltage capabilities.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to the structure, manufacturing method and power device of a MOSFET, and electronic equipment. Background Technology

[0002] The related Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) device includes an epitaxial layer, a channel layer, an active layer, and an insulating layer disposed from bottom to top. The MOSFET also includes a trench, a dielectric layer, and conductive pillars. The trench extends longitudinally downwards from the upper surface of the active layer through both the active layer and the channel layer. The dielectric layer covers the inner surface of the sidewalls of the first trench and the upper surface of the bottom of the first trench. The conductive pillars are located inside the dielectric layer. Due to the relatively thick epitaxial layer and the fact that only the epitaxial layer serves as the drain, the related MOSFET suffers from low lateral and reverse breakdown voltages, as well as high internal resistance. Summary of the Invention

[0003] The purpose of this application is to provide a MOSFET structure, manufacturing method, power device, and electronic device, aiming to solve the problems of low lateral and reverse breakdown voltage and high internal resistance of related MOSFETs.

[0004] This application provides a MOSFET structure, including:

[0005] Epitaxial layer;

[0006] A channel layer disposed on the upper surface of the epitaxial layer;

[0007] An active layer disposed on the upper surface of the channel layer;

[0008] A gate structure extending longitudinally downwards from the upper surface of the active layer through the active layer and the channel layer;

[0009] A first trench extends longitudinally downwards from the upper surface of the active layer, passing through the active layer and the channel layer;

[0010] A first conductive layer covering the inner surface of the sidewall of the first trench;

[0011] A first dielectric layer covering the inner surface of the sidewall of the first conductive layer;

[0012] Metal pillars filling the interior of the first dielectric layer;

[0013] A floating knot located at the bottom of the first trench;

[0014] The first insulating layer is located at the top of the first trench.

[0015] In one embodiment, it further includes:

[0016] A second trench extends longitudinally downward from the upper surface of the first insulating layer through the first insulating layer and the active layer;

[0017] The first metal layer located on the upper surface of the first insulating layer and at the top of the second trench;

[0018] The bottom of the second trench is in contact with the upper surface of the channel layer, and the second trench is filled with metal.

[0019] In one embodiment, the gate structure includes:

[0020] A third trench extends longitudinally downwards from the upper surface of the insulation layer through the first insulation layer, the active layer, and the channel layer;

[0021] A second dielectric layer covering the inner surface of the sidewall of the third trench;

[0022] Conductive pillars filling the interior of the second dielectric layer.

[0023] In one embodiment, the epitaxial layer is an N-type epitaxial layer, the channel layer is a P-type channel layer, the active layer is a P-type active layer, and the floating junction is a P-type floating junction; or

[0024] The epitaxial layer is a P-type epitaxial layer, the channel layer is an N-type channel layer, the active layer is an N-type active layer, and the floating junction is an N-type floating junction.

[0025] In one embodiment, the materials of the first dielectric layer and the second dielectric layer include silicon dioxide and silicon nitride; the materials of the first conductive layer and the conductive pillar include polycrystalline silicon.

[0026] In one embodiment, the MOSFET includes a field-effect transistor; the channel layer is the gate of the field-effect transistor, the epitaxial layer is the drain of the field-effect transistor, and the active layer is the source of the field-effect transistor;

[0027] The floating junction and the epitaxial layer form a superjunction structure.

[0028] This application also provides a method for manufacturing a MOSFET, the method comprising:

[0029] Formation of epitaxial layer;

[0030] Remove a portion of the epitaxial layer to form the first trench and the third trench;

[0031] A second dielectric layer is formed on the upper surface of the third trench;

[0032] A first conductive layer is formed on the side surface of the first trench, and the interior of the second dielectric layer is filled to form a conductive pillar;

[0033] Ion implantation is performed at the bottom of the first trench and on the upper surface of the epitaxial layer to form a floating junction and a channel layer; the floating junction is located at the bottom of the first trench and the channel layer is located on the upper surface of the epitaxial layer;

[0034] The interior of the first conductive layer is filled to form a dielectric pillar, and a second insulating layer is formed on the upper surface of the channel layer;

[0035] The second insulating layer is etched back to expose the channel layer;

[0036] Ion implantation is performed on the upper surface of the channel layer to form an active layer;

[0037] A first insulating layer is formed on the upper surface of the active layer;

[0038] Remove the central region of the dielectric pillar to form a fourth trench, and remove part of the first insulating layer and part of the active layer to form a second trench;

[0039] The fourth trench is filled to form a metal pillar, and the second trench is filled, and a first metal layer is formed on the upper surface of the first insulating layer.

[0040] In one embodiment, removing a portion of the epitaxial layer to form the first trench and the third trench includes:

[0041] A silicon dioxide layer is formed on the upper surface of the epitaxial layer;

[0042] A portion of the silicon dioxide layer is removed to form a mask layer; the mask layer has a fifth trench and a sixth trench;

[0043] Using the mask layer as a mask, a portion of the epitaxial layer is removed to form the first trench and the third trench;

[0044] Remove the mask layer.

[0045] In one embodiment, forming a first conductive layer on the side surface of the first trench and filling the interior of the second dielectric layer to form a conductive pillar includes:

[0046] The interior of the second dielectric layer is filled to form a conductive pillar, and a second conductive layer is formed on the surface of the first trench and the upper surface of the epitaxial layer;

[0047] The upper surface of the second conductive layer is etched back while the second conductive layer on the side surface of the first trench is retained to form the first conductive layer.

[0048] This application also provides a power device comprising a plurality of MOSFETs arranged in sequence as described above.

[0049] This application also provides an electronic device, which includes the MOSFET structure described above.

[0050] The beneficial effects of this invention compared to the prior art are as follows: Since the first trench extends longitudinally downward from the upper surface of the active layer through the active layer and the channel layer, the first conductive layer covers the inner surface of the sidewall of the first trench, the first dielectric layer covers the inner surface of the sidewall of the first conductive layer, and the metal pillar fills the interior of the first dielectric layer, a first dielectric layer is disposed between the metal pillar and the first conductive layer. The metal pillar and the first conductive layer respectively constitute the two poles of a capacitor, which improves the lateral breakdown voltage capability of the MOSFET. Since the floating junction is located at the bottom of the first trench and the metal pillar fills the interior of the first dielectric layer, a floating junction embedded in the epitaxial layer is formed, and the floating junction can form a superjunction structure with the epitaxial layer, which improves the longitudinal breakdown voltage capability of the MOSFET. At the same time, the PN junction formed by the floating junction and the epitaxial layer reduces the internal resistance of the MOSFET when a forward voltage is applied to the MOSFET. Attached Figure Description

[0051] To more clearly illustrate the technical inventions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of the structure of a MOSFET provided in an embodiment of this application;

[0053] Figure 2 This is a schematic diagram of another structure of the MOSFET provided in one embodiment of this application;

[0054] Figure 3 This is a schematic diagram illustrating the formation of an N-type epitaxial layer in a MOSFET manufacturing method provided in this application embodiment;

[0055] Figure 4 A schematic diagram illustrating the formation of a first trench and a third trench in a MOSFET manufacturing method provided in this application embodiment;

[0056] Figure 5 A schematic diagram illustrating the formation of a second dielectric layer in a MOSFET manufacturing method provided in this application embodiment;

[0057] Figure 6A schematic diagram illustrating the formation of a first conductive layer and conductive pillars in a MOSFET manufacturing method provided in this application embodiment;

[0058] Figure 7 A schematic diagram illustrating the formation of a floating junction and a channel layer in a MOSFET manufacturing method provided in this application embodiment;

[0059] Figure 8 A schematic diagram illustrating the formation of a dielectric pillar and a second insulating layer in a MOSFET manufacturing method provided in this application embodiment;

[0060] Figure 9 A schematic diagram showing the exposed channel layer in a MOSFET manufacturing method provided in this application embodiment;

[0061] Figure 10 A schematic diagram illustrating the formation of an active layer in a MOSFET manufacturing method provided in this application embodiment;

[0062] Figure 11 A schematic diagram illustrating the formation of a first insulating layer and a fourth trench and a second trench in a MOSFET manufacturing method provided in this application embodiment;

[0063] Figure 12 This is a schematic diagram of the formation of a metal pillar and a first metal layer in a MOSFET manufacturing method provided in this application embodiment. Detailed Implementation

[0064] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0065] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0066] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0067] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0068] Figure 1 The module structure of a MOSFET provided in an embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below:

[0069] The MOSFET structure includes an epitaxial layer 11, a channel layer 12, an active layer 13, a gate structure 14, a first trench 09, a first conductive layer 15, a first dielectric layer 16, a metal pillar 17, a floating junction 18, and a first insulating layer 19.

[0070] A channel layer 12 is disposed on the upper surface of the epitaxial layer 11; an active layer 13 is disposed on the upper surface of the channel layer 12; a gate structure 14 extends longitudinally downward from the upper surface of the active layer 13 through the active layer 13 and the channel layer 12; a first trench 09 extends longitudinally downward from the upper surface of the active layer 13 through the active layer 13 and the channel layer 12; a first conductive layer 15 covers the inner surface of the sidewall of the first trench 09; a first dielectric layer 16 covers the inner surface of the sidewall of the first conductive layer 15; a metal pillar 17 fills the interior of the first dielectric layer 16; a floating junction 18 is located at the bottom of the first trench 09; and a first insulating layer 19 is located at the top of the first trench 09.

[0071] The gate structure 14 includes a third trench 08, a second dielectric layer 142, and a conductive pillar 143.

[0072] The third trench 08 extends longitudinally downward from the upper surface of the first insulating layer 19, through the first insulating layer 19, the active layer 13, and the channel layer 12; the second dielectric layer 142 covers the inner surface of the sidewall of the third trench 08; the conductive pillar 143 fills the interior of the second dielectric layer 142.

[0073] like Figure 2 As shown, the MOSFET structure also includes a second trench 01 and a first metal layer 02.

[0074] The second trench 01 extends longitudinally downward from the upper surface of the insulation through the first insulating layer 19 and the active layer 13; the first metal layer 02 is located on the upper surface of the first insulating layer 19 and the top of the second trench 01; the bottom of the second trench 01 contacts the upper surface of the channel layer 12, and the second trench 01 is filled with metal.

[0075] The second trench 01 is filled with metal, and a first metal layer 02 is formed on the upper surface of the first insulating layer 19 and the top of the second trench 01 to serve as the source electrode of the MOSFET; a third metal layer is formed on the lower surface of the epitaxial layer 11 to serve as the drain electrode of the MOSFET.

[0076] As an example and not a limitation, epitaxial layer 11 is an N-type epitaxial layer 11, channel layer 12 is a P-type channel layer 12, active layer 13 is a P-type active layer 13, and floating junction 18 is a P-type floating junction 18; thereby forming an N-type MOSFET; or

[0077] The epitaxial layer 11 is a P-type epitaxial layer 11, the channel layer 12 is an N-type channel layer 12, the active layer 13 is an N-type active layer 13, and the floating junction 18 is an N-type floating junction 18; thus forming a P-type MOSFET.

[0078] It should be noted that the materials of the first dielectric layer 16 and the second dielectric layer 142 include silicon dioxide and silicon nitride; the materials of the first conductive layer 15 and the conductive pillar 143 include polycrystalline silicon.

[0079] It is worth emphasizing that the MOSFET includes a field-effect transistor; the channel layer 12 is the gate of the field-effect transistor, the epitaxial layer 11 is the drain of the field-effect transistor, and the active layer 13 is the source of the field-effect transistor; and the floating junction 18 and the epitaxial layer 11 form a superjunction structure.

[0080] When the epitaxial layer 11 is an N-type epitaxial layer 11, the floating junction 18 is a P-type floating junction 18; when the epitaxial layer 11 is a P-type epitaxial layer 11, the floating junction 18 is an N-type floating junction 18; thus forming a superjunction structure, the superjunction structure forms a longitudinal electric field, which improves the voltage withstand capability of the MOSFET.

[0081] Corresponding to one embodiment of a MOSFET, the present invention also provides an embodiment of a method for manufacturing a MOSFET.

[0082] A method for manufacturing a MOSFET, the method comprising steps 401 to 406.

[0083] In step 401, as Figure 3 As shown, an epitaxial layer 11 is formed.

[0084] Epitaxial layers can be formed through processes such as vapor deposition or sputtering.

[0085] In step 402, as Figure 4 As shown, a portion of the epitaxial layer 11 is removed to form the first trench 09 and the third trench 08.

[0086] In a specific implementation, step 402 may include steps A1 to D1.

[0087] In step A1, a silicon dioxide layer is formed on the upper surface of the epitaxial layer 11.

[0088] A silicon dioxide layer can be formed on the upper surface of the epitaxial layer 11 by processes such as vapor deposition or sputtering.

[0089] In step B1, a portion of the silicon dioxide layer is removed to form a mask layer; the mask layer has a fifth trench and a sixth trench.

[0090] A mask layer is formed by etching away part of the silicon dioxide layer.

[0091] In step C1, a portion of the epitaxial layer 1111 is removed using a mask layer as a mask to form the first trench 09 and the third trench 08.

[0092] Part of the epitaxial layer 11 is removed by etching using a mask layer as a mask to form the first trench 09 and the third trench 08.

[0093] In step D1, the mask layer is removed.

[0094] Maskless etching is used to remove the mask layer.

[0095] In step 403, as Figure 5 As shown, a second dielectric layer 142 is formed on the upper surface of the third trench 08.

[0096] In step 404, as Figure 6 As shown, a first conductive layer 15 is formed on the side surface of the first trench 09, and the interior of the second dielectric layer 142 is filled to form a conductive pillar 143.

[0097] In a specific implementation, step 402 may include steps A2 to B2.

[0098] In step A2, the interior of the second dielectric layer 142 is filled to form a conductive pillar 143, and a second conductive layer is formed on the surface of the first trench 09 and the upper surface of the epitaxial layer 11.

[0099] The interior of the second dielectric layer 142 can be filled by processes such as vapor deposition or sputtering to form conductive pillars 143, and a second conductive layer can be formed on the surface of the first trench 09 and the upper surface of the epitaxial layer 11.

[0100] In step B2, the upper surface of the second conductive layer is etched back and the second conductive layer on the side surface of the first trench 09 is retained to form the first conductive layer 15.

[0101] The upper surface of the second conductive layer is etched back without a mask, and the second conductive layer on the side surface of the first trench 09 is retained to form the first conductive layer 15.

[0102] In step 405, as Figure 7As shown, ion implantation is performed at the bottom of the first trench 09 and on the upper surface of the epitaxial layer 11 to form a floating junction 18 and a channel layer 12; the floating junction 18 is located at the bottom of the first trench 09 and the channel layer 12 is located on the upper surface of the epitaxial layer 11.

[0103] In step 406, as Figure 8 As shown, the interior of the first conductive layer 15 is filled to form a dielectric pillar 20, and a second insulating layer 30 is formed on the upper surface of the channel layer 12;

[0104] In step 407, as Figure 9 As shown, the second insulating layer 30 is etched back to expose the channel layer 12;

[0105] In step 408, as Figure 10 As shown, ion implantation is performed on the upper surface of the channel layer 12 to form the active layer 13;

[0106] Among them, the channel layer 12 has the opposite semiconductor type to the epitaxial layer 11 and the active layer 13; the epitaxial layer 11 and the active layer 13 have the same semiconductor type.

[0107] In step 409, as Figure 11 As shown, a first insulating layer 19 is formed on the upper surface of the active layer 13;

[0108] The first insulating layer 19 can be formed on the upper surface of the active layer 13 by processes such as vapor deposition or sputtering.

[0109] In step 410, as Figure 11 As shown, the central region of the dielectric pillar 20 is removed to form the fourth trench 05, and a portion of the first insulating layer 19 and a portion of the active layer 13 are removed to form the second trench 01.

[0110] The fourth trench 05 is formed by removing the central region of the dielectric pillar 20 through imaging, and a portion of the first insulating layer 19 and a portion of the active layer 13 are removed to form the second trench 01; the imaging includes an etching process.

[0111] In step 411, as Figure 12 As shown, the fourth trench 05 is filled to form a metal pillar 17, and the second trench 01 is filled, and a first metal layer 02 is formed on the upper surface of the first insulating layer 19.

[0112] The fourth trench 05 can be filled by processes such as vapor deposition or sputtering to form a conductive pillar 143, and the second trench 01 can be filled, and a first metal layer 02 can be formed on the upper surface of the first insulating layer 19.

[0113] The floating junction 18 and the epitaxial layer 11 have opposite semiconductor types.

[0114] It is worth noting that the metal layer can be gold or palladium.

[0115] This invention includes an epitaxial layer, a channel layer, an active layer, a gate structure, a first trench, a first conductive layer, a first dielectric layer, metal pillars, a floating junction, and a first insulating layer. The channel layer is disposed on the upper surface of the epitaxial layer. The active layer is disposed on the upper surface of the channel layer. The gate structure extends longitudinally downwards from the upper surface of the active layer through the active layer and the channel layer. The first trench extends longitudinally downwards from the upper surface of the active layer through the active layer and the channel layer. The first conductive layer covers the inner surface of the sidewalls of the first trench. The first dielectric layer covers the inner surface of the sidewalls of the first conductive layer. The metal pillars fill the interior of the first dielectric layer. The floating junction is located at the bottom of the first trench. The first insulating layer is located at the top of the first trench. Because the first trench extends longitudinally downwards from the upper surface of the active layer... The MOSFET has a source layer and a channel layer. A first conductive layer covers the inner surface of the sidewall of the first trench, and a first dielectric layer covers the inner surface of the sidewall of the first conductive layer. A metal pillar is filled inside the first dielectric layer, so a first dielectric layer is disposed between the metal pillar and the first conductive layer. The metal pillar and the first conductive layer respectively form the two poles of a capacitor, which improves the lateral breakdown voltage capability of the MOSFET. Since the floating junction is located at the bottom of the first trench and the metal pillar is filled inside the first dielectric layer, a floating junction is formed embedded in the epitaxial layer. This floating junction can form a superjunction structure with the epitaxial layer, which improves the longitudinal breakdown voltage capability of the MOSFET. At the same time, the PN junction formed by the floating junction and the epitaxial layer reduces the internal resistance of the MOSFET when a forward voltage is applied to the MOSFET.

[0116] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0117] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A MOSFET structure, characterized in that, include: Epitaxial layer; A channel layer disposed on the upper surface of the epitaxial layer; An active layer disposed on the upper surface of the channel layer; A gate structure extending longitudinally downwards from the upper surface of the active layer through the active layer and the channel layer; A first trench extends longitudinally downwards from the upper surface of the active layer, passing through the active layer and the channel layer; A first conductive layer covering the inner surface of the sidewall of the first trench; A first dielectric layer covering the inner surface of the sidewall of the first conductive layer; Metal pillars filling the interior of the first dielectric layer; A floating knot located at the bottom of the first trench; The first insulating layer located at the top of the first trench; The epitaxial layer is an N-type epitaxial layer, the channel layer is a P-type channel layer, the active layer is a P-type active layer, and the floating junction is a P-type floating junction; or The epitaxial layer is a P-type epitaxial layer, the channel layer is an N-type channel layer, the active layer is an N-type active layer, and the floating junction is an N-type floating junction.

2. The MOSFET structure as described in claim 1, characterized in that, Also includes: A second trench extends longitudinally downward from the upper surface of the first insulating layer through the first insulating layer and the active layer; The first metal layer located on the upper surface of the first insulating layer and at the top of the second trench; The bottom of the second trench is in contact with the upper surface of the channel layer, and the second trench is filled with metal.

3. The MOSFET structure as described in claim 2, characterized in that, The gate structure includes: A third trench extends longitudinally downwards from the upper surface of the insulation layer through the first insulation layer, the active layer, and the channel layer; A second dielectric layer covering the inner surface of the sidewall of the third trench; Conductive pillars filling the interior of the second dielectric layer.

4. The MOSFET structure as described in claim 3, characterized in that, The materials of the first dielectric layer and the second dielectric layer include silicon dioxide and silicon nitride; the materials of the first conductive layer and the conductive pillar include polycrystalline silicon.

5. The structure of the MOSFET as described in claim 1, characterized in that, The MOSFET includes a field-effect transistor; the channel layer is the gate of the field-effect transistor, the epitaxial layer is the drain of the field-effect transistor, and the active layer is the source of the field-effect transistor; The floating junction and the epitaxial layer form a superjunction structure.

6. A method for manufacturing a MOSFET, characterized in that, The manufacturing method includes: Formation of epitaxial layer; Remove a portion of the epitaxial layer to form the first trench and the third trench; A second dielectric layer is formed on the upper surface of the third trench; A first conductive layer is formed on the side surface of the first trench, and the interior of the second dielectric layer is filled to form a conductive pillar; Ion implantation is performed at the bottom of the first trench and on the upper surface of the epitaxial layer to form a floating junction and a channel layer; the floating junction is located at the bottom of the first trench and the channel layer is located on the upper surface of the epitaxial layer; The interior of the first conductive layer is filled to form a dielectric pillar, and a second insulating layer is formed on the upper surface of the channel layer; The second insulating layer is etched back to expose the channel layer; Ion implantation is performed on the upper surface of the channel layer to form an active layer; A first insulating layer is formed on the upper surface of the active layer; Remove the central region of the dielectric pillar to form a fourth trench, and remove part of the first insulating layer and part of the active layer to form a second trench; The fourth trench is filled to form a metal pillar, and the second trench is filled, and a first metal layer is formed on the upper surface of the first insulating layer; The epitaxial layer is an N-type epitaxial layer, the channel layer is a P-type channel layer, the active layer is a P-type active layer, and the floating junction is a P-type floating junction; or The epitaxial layer is a P-type epitaxial layer, the channel layer is an N-type channel layer, the active layer is an N-type active layer, and the floating junction is an N-type floating junction.

7. The method for manufacturing a MOSFET according to claim 6, characterized in that, The removal of a portion of the epitaxial layer to form the first trench and the third trench includes: A silicon dioxide layer is formed on the upper surface of the epitaxial layer; A portion of the silicon dioxide layer is removed to form a mask layer; the mask layer has a fifth trench and a sixth trench; Using the mask layer as a mask, a portion of the epitaxial layer is removed to form the first trench and the third trench; Remove the mask layer.

8. The method for manufacturing a MOSFET according to claim 6, characterized in that, The step of forming a first conductive layer on the side surface of the first trench and filling the interior of the second dielectric layer to form a conductive pillar includes: The interior of the second dielectric layer is filled to form a conductive pillar, and a second conductive layer is formed on the surface of the first trench and the upper surface of the epitaxial layer; The upper surface of the second conductive layer is etched back while the second conductive layer on the side surface of the first trench is retained to form the first conductive layer.

9. A power device, characterized in that, The power device includes a plurality of MOSFETs arranged in sequence as described in any one of claims 1 to 5.

10. An electronic device, characterized in that, The electronic device includes the structure of a MOSFET as described in any one of claims 1 to 5.

Images