Analog circuit and comparator for analog circuit

Abstract

The present disclosure relates to an analog circuit and a shared method for a comparator of the analog circuit. An analog circuit includes a voltage regulator, an analog-to-digital converter, a comparator, and a multiplexer. The voltage regulator is configured to generate an output voltage. The analog-to-digital converter is configured to generate a digital signal. The multiplexer is coupled to the voltage regulator, the analog-to-digital converter, and the comparator, and configured to switch the comparator to one of the voltage regulator and the analog-to-digital converter. When the voltage regulator is triggered, the multiplexer switches the comparator to the voltage regulator, and the voltage regulator generates the output voltage according to an output of the comparator. When the analog-to-digital converter is triggered, the multiplexer switches the comparator to the analog-to-digital converter, and the analog-to-digital converter generates the digital signal according to the output of the comparator.

Description

Technical Field

[0001] This disclosure relates to an analog circuit and its operation method, and more particularly to an analog circuit with a shared comparator and its comparator sharing method. Background Technology

[0002] Linear regulators are widely used in processor peripheral circuits. They adaptively adjust their power according to load changes to achieve a stable output voltage. Since temperature variations directly affect processor performance and stability, processor peripheral circuits typically include numerous temperature sensors to calibrate the processor based on temperature; these temperature sensors can be implemented using various analog-to-digital converters. Summary of the Invention

[0003] This disclosure provides an analog circuit comprising a voltage regulator, at least one analog-to-digital converter (A / D converter), at least one comparator, and a multiplexer. The voltage regulator generates an output voltage. The at least one A / D converter generates at least one digital signal. The multiplexer is coupled to the voltage regulator, the at least one A / D converter, and the at least one comparator, for turning on the at least one comparator to one of the voltage regulator and the at least one A / D converter. When the voltage regulator is triggered, the multiplexer turns on the at least one comparator to the voltage regulator, and the voltage regulator generates an output voltage based on the output of the at least one comparator. When the at least one A / D converter is triggered, the multiplexer turns on the at least one comparator to the at least one A / D converter, and the at least one A / D converter generates at least one digital signal based on the output of the at least one comparator.

[0004] This disclosure provides a comparator sharing method for analog circuits, comprising the following steps: when a regulator is triggered, a multiplexer is used to turn on at least one comparator to the regulator, wherein the regulator generates an output voltage based on the output of the at least one comparator; and when at least one analog-to-digital converter is triggered, a multiplexer is used to turn on at least one comparator to at least one analog-to-digital converter, wherein the at least one analog-to-digital converter generates at least one digital signal based on the output of the at least one comparator. The multiplexer is coupled to the regulator, the at least one analog-to-digital converter, and the at least one comparator.

[0005] One of the advantages of the above-mentioned method of sharing analog circuits and comparators is that it can reduce the circuit area. Attached Figure Description

[0006] Figure 1 This is a simplified functional block diagram of an analog circuit according to an embodiment of this disclosure.

[0007] Figure 2This is a simplified functional block diagram of a digital low-dropout linear regulator according to an embodiment of this disclosure.

[0008] Figure 3 This is a simplified functional block diagram of an incremental trigonometric integrator analog-to-digital converter according to an embodiment of this disclosure.

[0009] Figure 4 This is a simplified functional block diagram of an analog circuit according to an embodiment of this disclosure.

[0010] Figure 5 This is a simplified functional block diagram of a control circuit according to an embodiment of this disclosure.

[0011] Figure 6 for Figure 5 A waveform diagram of multiple signals of the control circuit.

[0012] Figure 7 This is a simplified functional block diagram of a trigonometric integral modulator according to an embodiment of this disclosure.

[0013] Figure 8 This is a simplified functional block diagram of a successive approximation analog-to-digital converter according to an embodiment of this disclosure.

[0014] Figure 9 This is a simplified functional block diagram of an analog circuit according to an embodiment of this disclosure. Detailed Implementation

[0015] The embodiments of this disclosure will be described below with reference to the relevant drawings. In the drawings, the same reference numerals denote the same or similar elements or method flows.

[0016] Figure 1This is a simplified functional block diagram of an analog circuit 100 according to one embodiment of this disclosure. In some embodiments, the analog circuit 100 is peripheral circuitry to a processor (not shown) and can be used to provide operating voltage to the processor and to detect ambient temperature so that the processor can self-calibrate for temperature. The analog circuit 100 includes a voltage regulator 110, an analog-to-digital converter (ADC) 120, a multiplexer 130, and a comparator 140. The voltage regulator 110 is coupled to the comparator 140 through the multiplexer 130. The voltage regulator 110 generates an output voltage Vout and receives a control signal Pload and a load voltage Vload. When the voltage regulator 110 is triggered by the control signal Pload, the voltage regulator 110 analyzes the load voltage Vload to obtain the current load magnitude and adaptively adjusts its power to obtain a stable output voltage Vout. In some embodiments, the output voltage Vout is used as the operating voltage of the processor. In other embodiments, regulator 110 is a digital low-dropout linear regulator (DLDO), but this disclosure is not limited thereto.

[0017] Analog-to-digital converter 120 is coupled to comparator 140 via multiplexer 130. Analog-to-digital converter 120 generates a digital signal Dout and receives a control signal Vsta and an input voltage Vin. When triggered by the control signal Vsta, analog-to-digital converter 120 converts the input voltage Vin to generate the digital signal Dout. In some embodiments, the input voltage Vin is positively or negatively correlated with the ambient temperature, so the digital signal Dout can be used to inform the processor of the current ambient temperature so that the processor can perform self-correction for the ambient temperature. Analog-to-digital converter 120 can be implemented as an incremental delta-sigma ADC, a delta-sigma modulator, or a successive approximation register ADC, but this disclosure is not limited thereto.

[0018] Multiplexer 130 is coupled to regulator 110, analog-to-digital converter 120, and comparator 140, and is used to turn comparator 140 to one of regulator 110 and analog-to-digital converter 120. Multiplexer 130 includes switching circuits 132 and 134. Switching circuit 132 is coupled between regulator 110 and comparator 140, while switching circuit 134 is coupled between analog-to-digital converter 120 and comparator 140. Figure 1It can be seen that the switching operation of the switching circuit 132 and the switching circuit 134 is controlled by the multiplexing signals Swb and Sw, respectively, wherein the multiplexing signals Swb and Sw are inverses of each other.

[0019] When regulator 110 is triggered by control signal Pload, multiplexer 130 turns on switching circuit 132 and turns off switching circuit 134 to turn on comparator 140 to regulator 110. At this time, regulator 110 generates an output voltage Vout based on the output of comparator 140. Conversely, when analog-to-digital converter 120 is triggered by control signal Vsta, multiplexer 130 turns off switching circuit 132 and turns on switching circuit 134 to turn on comparator 140 to analog-to-digital converter 120. At this time, analog-to-digital converter 120 generates a digital signal Dout based on the output of comparator 140.

[0020] In some embodiments, the control signal Pload is used to trigger the regulator 110 when the load on the regulator 110 changes. For example, the control signal Pload and the load voltage Vload can be generated by the aforementioned processor. In this case, the regulator 110 uses the comparator 140 to analyze the load voltage Vload to obtain the current load magnitude, and then adjusts the output power of the regulator 110. On the other hand, when the load on the regulator 110 remains stable, the control signal Pload does not trigger the regulator 110, and the regulator 110 can maintain a constant output power. In this case, the regulator 110 does not need to continuously use the comparator 140. When the regulator 110 does not need to use the comparator 140, the analog-to-digital converter 120 can use the comparator 140 to perform analog-to-digital conversion. As can be seen from the above, the analog circuit 100 can reduce the overall circuit area by sharing the comparator 140.

[0021] Figure 2 A simplified functional block diagram of a digital low-dropout linear regulator 200 (hereinafter referred to as regulator 200) according to an embodiment of this disclosure. In some embodiments, regulator 200 can be used to implement... Figure 1 The voltage regulator 110, namely Figure 1 The load voltage Vload includes Figure 2 The load voltages are Vload[0] to Vload[n]. The regulator 200 includes an analog-to-digital converter 210, a control circuit 220, multiple power transistors 230, and a trigger circuit 240.

[0022] The analog-to-digital converter 210 includes multiple comparators 212[0] to 212[n]. The positive inputs of comparators 212[0] to 212[n] are used to receive load voltages Vload[0] to Vload[n], respectively, while the negative inputs of comparators 212[0] to 212[n] are used to receive the output voltage Vout through the feedback path. The outputs of comparators 212[0] to 212[n] are coupled to the control circuit 220, and comparators 212[0] to 212[n] are used to provide the digital codes Dcod[0] to Dcod[n] obtained by parsing the load voltages Vload[0] to Vload[n] to the control circuit 220.

[0023] The control circuit 220 registers digital codes Dcod[0] to Dcod[n] based on the clock signal Clk, and determines the number of power transistors 230 turned on based on the digital codes Dcod[0] to Dcod[n] to adjust the output voltage Vout. In some embodiments, the control circuit 220 includes a multi-stage shift register for storing the digital codes Dcod[0] to Dcod[n]. The trigger circuit 240 is coupled to the feedback path between the power transistor 230 and the analog-to-digital converter 210, and includes multiple transistors. The control signal Pload sets the voltage on the feedback path to ground potential by turning on the transistors in the trigger circuit 240, thereby triggering the regulator 200 to start parsing the load voltages Vload[0] to Vload[n] to adjust the output voltage Vout.

[0024] Depend on Figure 2 As can be seen, when the regulator 200 is triggered, the switching circuit 132 turns on the comparator 140 to the regulator 200, so that the comparator 140 is operated as comparator 212[0] in the analog-to-digital converter 210 (marked with a dashed box in the figure; this part of the line is actually coupled to the comparator 140 through the switching circuit 132). At this time, the positive input terminal of the comparator 140 is used to receive the load voltage Vload[0]; the negative input terminal of the comparator 140 is used to receive the output voltage Vout; the output terminal of the comparator 140 is used to output the digital code Dcod[0] to the control circuit 220, but this disclosure is not limited thereto. In some embodiments, the comparator 140 may be operated as any one of the comparators 212[0] to 212[n] of the analog-to-digital converter 210. That is, the voltage regulator 200 and the analog-to-digital converter 300 share the comparator 140, and when the voltage regulator 200 is triggered, the comparator 140 is operated as part of the voltage regulator 200.

[0025] Figure 3This is a simplified functional block diagram of an incremental trigonometric integrator analog-to-digital converter 300 (hereinafter referred to as analog-to-digital converter 300) according to an embodiment of this disclosure. In some embodiments, the analog-to-digital converter 300 can be used to implement... Figure 1 The analog-to-digital converter 120, namely Figure 1 The input voltage Vin includes Figure 3 The differential input voltages Vinn and Vinp, and Figure 1 The digital signal Dout contains Figure 3 The analog-to-digital converter 300 includes sampling circuit 310, integrator 320, sampling circuit 330, integrator 340, logic circuit 350, and quantizer 360 to generate digital signals Doutn and Doutp from the input voltages Vinn and Vinp through two-stage integration processing, but this disclosure is not limited thereto. In some embodiments, the analog-to-digital converter 300 may include combinations of two or more sampling circuits and integrators.

[0026] Switching signals of analog-to-digital converter 300 and They are inversely related to each other to achieve interleaved integration and interleaved sampling. For example, when sampling circuit 310 performs sampling, integrator 340 performs integration; when sampling circuit 330 performs sampling, integrator 320 performs integration. Quantizer 360 is used to quantize the output of integrator 340 into digital signals Doutn and Doutp.

[0027] Logic circuit 350 based on switch signals and The digital signals Doutn and Doutp generate inverse switching signals A1 and B1, and inverse switching signals A2 and B2. The switches controlled by switching signals A1, B1, A2, and B2 are used to implement negative feedback. Additionally, the switch controlled by switching signal P1 presets the positive output (upper) and negative output (lower) of integrator 320 to the positive reference voltage Vrefp and the negative reference voltage Vrefn, respectively. Therefore, during integration, the voltage at the positive output of integrator 320 gradually decreases under the influence of the current source, while the voltage at the negative output of integrator 320 gradually increases under the influence of the current source. Similarly, the switch controlled by switching signal P2 presets the positive output (upper) and negative output (lower) of integrator 340 to the positive reference voltage Vrefp and the negative reference voltage Vrefn, respectively.

[0028] The control signal Vsta is used to reset the analog-to-digital converter 300 and to trigger the converter to convert the input voltages Vinn and Vinp to generate digital signals Doutn and Doutp. Figure 3 As can be seen, when the analog-to-digital converter 300 is triggered, the switching circuit 134 turns on the comparator 140 to the analog-to-digital converter 300. At this time, the comparator 140 can be operated as the integrator 320 of the analog-to-digital converter 300, but this disclosure is not limited thereto. In some embodiments, the comparator 140 can be used to form any of a plurality of integrators of the analog-to-digital converter 300. That is, the voltage regulator 200 and the analog-to-digital converter 300 share the comparator 140, and when the analog-to-digital converter 300 is triggered, the comparator 140 is operated as part of the analog-to-digital converter 300.

[0029] Figure 4 This is a simplified functional block diagram of an analog circuit 400 according to an embodiment of this disclosure. The analog circuit 400 includes a voltage regulator 410, an analog-to-digital converter 420, a multiplexer 430, and a plurality of comparators 440[0] to 440[n]. The voltage regulator 410 is used to generate an output voltage Vout and to receive a control signal Pload and a load voltage Vload. The analog-to-digital converter 420 is used to generate a digital signal Dout and to receive a control signal Vsta and an input voltage Vin. The multiplexer 430 is used to turn on the comparators 440[0] to 440[n] to one of the voltage regulator 410 and the analog-to-digital converter 420. In some embodiments, the voltage regulator 410 is a digital low-dropout linear regulator, but this disclosure is not limited thereto. The analog-to-digital converter 420 may be implemented by an incremental trigonometric integrator analog-to-digital converter, a trigonometric integrator modulator, or a continuous approximation analog-to-digital converter, but this disclosure is not limited thereto.

[0030] The multiplexer 430 includes multiple switching circuits 432[0] to 432[n] and multiple switching circuits 434[0] to 434[n]. The switching operation of the switching circuits 432[0] to 432[n] and the switching circuits 434[0] to 434[n] is controlled by multiplexing signals Swb and Sw, respectively, wherein the multiplexing signals Swb and Sw are inverses of each other. The first terminal of the switching circuits 432[0] to 432[n] is coupled to the voltage regulator 410, and the second terminal of the switching circuits 432[0] to 432[n] is coupled to the comparators 440[0] to 440[n]. The first terminal of the switching circuits 434[0] to 434[n] is coupled to the comparators 440[0] to 440[n], and the second terminal of the switching circuits 434[0] to 434[n] is coupled to the analog-to-digital converter 420.

[0031] When the voltage regulator 410 is triggered by the control signal Pload, the multiplexer 430 turns on the switching circuits 432[0] to 432[n] and turns off the switching circuits 434[0] to 434[n], so that the comparators 440[0] to 440[n] are all turned on to the voltage regulator 410. At this time, the voltage regulator 410 generates an output voltage Vout based on the outputs of the comparators 440[0] to 440[n]. For example, please refer to [reference needed]. Figure 2 and Figure 4 , Figure 2 The voltage regulator 200 can be used to achieve Figure 4 The voltage regulator 410. When the voltage regulator 410 is triggered by the control signal Pload, Figure 4 The comparators 440[0] to 440[n] are respectively operated as (or understood as replaced) Figure 2 The comparators 212[0] to 212[n] in the analog-to-digital converter 210. That is, the positive input terminal and the negative input terminal of comparator 440[0] receive the load voltage Vload[0] and the output voltage Vout respectively through the switching circuit 432[0], and the output terminal of comparator 440[0] is coupled to the control circuit 220 through the switching circuit 432[0]; the positive input terminal and the negative input terminal of comparator 440[1] receive the load voltage Vload[1] and the output voltage Vout respectively through the switching circuit 432[1], and the output terminal of comparator 440[1] is coupled to the control circuit 220 through the switching circuit 432[1], and so on.

[0032] On the other hand, when the analog-to-digital converter 420 is triggered, the multiplexer 430 turns on the switching circuits 434[0] to 434[n] and turns off the switching circuits 432[0] to 432[n], so that the comparators 440[0] to 440[n] are all turned on to the analog-to-digital converter 420. At this time, the analog-to-digital converter 420 generates a digital signal Dout based on the outputs of the comparators 440[0] to 440[n]. In an embodiment where n equals 1, please also refer to Figure 3 and Figure 4 , Figure 3 The analog-to-digital converter 300 can be used to implement Figure 4The analog-to-digital converter 420. When the analog-to-digital converter 420 is triggered by the control signal Vsta, the comparators 440[0] to 440[1] operate as part of the integrators 320 and 340, respectively. That is, the positive input terminal and the negative input terminal of the comparator 440[0] are coupled to the positive output terminal (upper end) and the negative output terminal (lower end) of the sampling circuit 310 through the switch circuit 434[0], respectively, and the output terminal of the comparator 440[0] is coupled to the current source in the integrator 320 through the switch circuit 434[0]; the positive input terminal and the negative input terminal of the comparator 440[1] are coupled to the positive output terminal (upper end) and the negative output terminal (lower end) of the sampling circuit 330 through the switch circuit 434[1], respectively, and the output terminal of the comparator 440[1] is coupled to the current source in the integrator 340 through the switch circuit 434[1] (that is, Figure 3 The comparator shown in the integrator 340 can be Figure 4 The comparator 440[1] in the middle is replaced), and so on.

[0033] In summary, when the analog-to-digital converter 420 is triggered, comparators 440[0] to 440[n] are respectively operated as part of a plurality of integrators in the analog-to-digital converter 420. The remaining embodiments and advantages of the aforementioned analog circuit 100 are also applicable to the analog circuit 400, and will not be repeated here for the sake of brevity.

[0034] Figure 5 This is a simplified functional block diagram of a control circuit 500 according to an embodiment of this disclosure. Figure 6 This is a waveform diagram of multiple signals from the control circuit 500. In some embodiments, Figure 1 Analog circuit 100 and Figure 4 The analog circuit 400 further includes a control circuit 500, which is used to generate a multiplexed signal Sw. The control circuit 500 includes registers 510 and 520, logic circuits 530 and 540.

[0035] Register 510 receives control signals Pload and Vsta via its clock input CK and reset input RST, respectively. Its positive data output Q outputs the clock signal Clk. Register 520 receives a delayed clock signal Clk' via its clock input CK and is coupled to logic circuit 530 via its reset input RST. Logic circuit 530 outputs a pulse wave in response to the falling edge of the control signal Vcnt. Register 520's positive data output Q outputs the multiplexing signal Sw. Additionally, the data inputs D of both registers 510 and 520 receive the operating voltage Vdd. The multiplexing signal Sw can be used for control... Figure 1 Multiplexer 130 or Figure 4 Multiplexer 430. In some embodiments, the multiplexing signal Swb can be generated by inputting the multiplexing signal Sw into an inverter (not shown), or directly generated by the inverted data output QB of register 520. In addition, logic circuit 540 is used to generate a control signal Vsta based on a delayed clock signal Clk', that is, logic circuit 540 is used to make the control signal Vsta have a pulse wave in response to the rising edge of the delayed clock signal Clk'.

[0036] like Figure 6 As shown, when register 510 is triggered by the control signal Pload, register 510 outputs a clock signal Clk with a first logic value (e.g., logic 1). When register 510 is triggered by the control signal Vsta, register 510 outputs a clock signal Clk with a second logic value (e.g., logic 0). Additionally, when register 520 is triggered by a delayed clock signal Clk', register 520 outputs a multiplexed signal Sw with a first logic value (e.g., logic 1). When register 520 is triggered by the control signal Vcnt (i.e., triggered by the pulse wave output by logic circuit 530), register 520 outputs a multiplexed signal Sw with a second logic value (e.g., logic 0).

[0037] In this embodiment, the control signal Vcnt can be generated by the analog-to-digital converter 120, analog-to-digital converter 300, or analog-to-digital converter 420. The control signal Vcnt is used to indicate that the analog-to-digital converter has completed the analog-to-digital conversion. Figure 3 Taking the analog-to-digital converter 300 as an example, the analog-to-digital converter 300 may include a counting circuit (not shown in the figure). The counting circuit is used to count the switching signals. The number of pulse waves is used to generate the control signal Vcnt. During one analog-to-digital conversion operation of the analog-to-digital converter 300, the switching signal... It will have a predetermined number of pulse waves, such as 100 times (e.g.) Figure 6 (as marked), but not limited to this.

[0038] In some embodiments, such as Figure 6 As shown, when the analog-to-digital converter 300 is triggered by the control signal Vsta, the switching signal... A pulse wave will begin to be generated, and the control signal Vcnt will be set to the first logic level (e.g., logic 1). If the switching signal... If the pulse wave has not yet reached the predetermined number, it indicates that the analog-to-digital conversion is not yet complete, and the counting circuit will maintain the control signal Vcnt at the first logic level. If the switching signal... Once the pulse wave has reached a predetermined number (e.g., 100 times), it indicates that the analog-to-digital conversion has been completed. The counting circuit will switch the control signal Vcnt to the second logic level (e.g., logic 0) to indicate that the analog-to-digital conversion has been completed.

[0039] Figure 7 This is a simplified functional block diagram of a trigonometric integral modulator 700 according to an embodiment of this disclosure. In some embodiments, the trigonometric integral modulator 700 can be used to implement... Figure 1 The analog-to-digital converter 120 is included. The trigonometric modulator 700 can be part of the receiver circuitry (not shown) of a wireless communication system for demodulating received wireless signals (e.g., input voltage Vin). The trigonometric modulator 700 includes integrator 710, integrator 720, quantizer 730 composed of comparators, and digital-to-analog converter 740.

[0040] When the delta-integral modulator 700 is triggered to begin demodulation operation, the switching circuit 134 turns on the comparator 140 to the delta-integral modulator 700. Therefore, the comparator 140 can operate as a quantizer for the delta-integral modulator 700, and the delta-integral modulator 700 generates a digital signal Dout based on the output of the comparator 140.

[0041] Figure 8 This is a simplified functional block diagram of a successive approximation analog-to-digital converter 800 (hereinafter referred to as analog-to-digital converter 800) according to an embodiment of this disclosure. In some embodiments, the analog-to-digital converter 800 can be used to implement... Figure 1 The analog-to-digital converter 120. The analog-to-digital converter 800 includes a sampling capacitor array 810, a comparator 820, and a successive approximation logic circuit 830. The sampling capacitor array 810 is used to receive input voltages Vinp and Vinn, and a reference voltage Vref.

[0042] When the analog-to-digital converter 800 is triggered to convert the input voltages Vinp and Vinn, the switching circuit 134 turns on comparator 140 to the analog-to-digital converter 800. Therefore, comparator 140 operates as comparator 820 of the analog-to-digital converter 800, meaning comparator 140 is coupled between the sampling capacitor array 810 and the successive approximation logic circuit 830. At this time, the successive approximation logic circuit 830 generates a digital signal Dout based on the output of comparator 140.

[0043] Figure 9The present disclosure provides a simplified functional block diagram of an analog circuit 900 according to an embodiment of the present disclosure. The analog circuit 900 includes a voltage regulator 910, multiple analog-to-digital converters 920[0] to 920[n], a multiplexer 930, and multiple comparators 940[0] to 940[n]. The multiplexer 930 is coupled to the voltage regulator 910, the analog-to-digital converters 920[0] to 920[n], and the comparators 940[0] to 940[n]. The analog-to-digital converters 920[0] to 920[n] convert input voltages Vin[0] to Vin[n] to generate multiple digital signals Dout[0] to Dout[n]. The multiplexer 930 turns on the comparators 940[0] to 940[n] to one of the voltage regulator 910 and the analog-to-digital converters 920[0] to 920[n]. In some embodiments, regulator 910 is a digital low-dropout linear regulator, but this disclosure is not limited thereto.

[0044] The multiplexer 930 includes multiple switching circuits 932[0] to 932[n] and multiple switching circuits 934[0] to 934[n]. The switching circuits 932[0] to 932[n] are controlled by multiplexing signals Swb[0] to Swb[n], respectively, while the switching circuits 934[0] to 934[n] are controlled by multiplexing signals Sw[0] to Sw[n], respectively, wherein the multiplexing signals Swb[0] to Swb[n] are inverted by the multiplexing signals Sw[0] to Sw[n]. The first terminal of the switching circuits 932[0] to 932[n] is coupled to the voltage regulator 910, and the second terminal of the switching circuits 932[0] to 932[n] is coupled to the comparators 940[0] to 940[n]. The first terminals of the switching circuits 934[0] to 934[n] are respectively coupled to the comparators 940[0] to 940[n], while the second terminals of the switching circuits 934[0] to 934[n] are respectively coupled to the analog-to-digital converters 920[0] to 920[n].

[0045] When the voltage regulator 910 is triggered by the control signal Pload, the multiplexer 930 will turn on the switching circuits 932[0] to 932[n] to couple the comparators 940[0] to 940[n] to the voltage regulator 910. For example, please refer to the following: Figure 2 and Figure 9 , Figure 2 The voltage regulator 200 can be used to achieve Figure 4 The voltage regulator 910. When the voltage regulator 910 is triggered by the control signal Pload, Figure 9 The comparators 940[0] to 940[n] are respectively operated as (or understood as replaced) Figure 2 The comparators 212[0] to 212[n].

[0046] On the other hand, when one or more of the analog-to-digital converters 920[0] to 920[n] are triggered, the multiplexer 930 turns on one or more of the corresponding switching circuits 934[0] to 934[n]. In this way, one or more comparators corresponding to the comparators 940[0] to 940[n] are turned on to the triggered one or more analog-to-digital converters respectively. For example, if the analog-to-digital converters 920[0] to 920[2] are triggered, the switching circuits 934[0] to 934[2] will be turned on, while the switching circuits 934[3] to 934[n] will remain off, so that the comparators 940[0] to 940[2] are turned on to the analog-to-digital converters 920[0] to 920[2] respectively.

[0047] The analog-to-digital converters 920[0] to 920[n] can each be implemented by an incremental trigonometric integrator analog-to-digital converter, a trigonometric integrator modulator, or a successive approximation analog-to-digital converter, but this disclosure is not limited thereto. For example, if the analog-to-digital converter 920[0] is implemented as an incremental trigonometric integrator analog-to-digital converter, then the comparator 940[0] is used as an integrator of the analog-to-digital converter 920[0]; if the analog-to-digital converter 920[0] is implemented as a trigonometric integrator modulator, then the comparator 940[0] is used as a quantizer of the analog-to-digital converter 920[0]; if the analog-to-digital converter 920[0] is implemented as a successive approximation analog-to-digital converter, then the comparator 940[0] is coupled between the successive approximation logic circuit of the analog-to-digital converter 920[0] and the sampling capacitor array, and so on. The other embodiments and advantages of the aforementioned analog circuit 100 are also applicable to the analog circuit 900, and for the sake of brevity, they will not be repeated here.

[0048] In summary, the logic circuit in this disclosure can switch the comparator to be used by the analog-to-digital converter when the voltage regulator does not need to adjust its power, and can also switch the comparator to be used by the voltage regulator when the analog-to-digital converter does not need to perform analog-to-digital conversion. By allowing different circuit blocks to share the comparator, the logic circuit in this disclosure has the advantages of reducing the overall circuit area and improving the flexibility of circuit layout.

[0049] Certain terms are used in the specification and claims to refer to specific elements. However, those skilled in the art will understand that the same element may be referred to by different names. The specification and claims do not distinguish elements by differences in name, but by differences in function. The term "comprising" in the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to". Furthermore, "coupled" here includes any direct and indirect means of connection. Therefore, if the text describes a first element coupled to a second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection methods such as wireless transmission or optical transmission, or indirectly electrically or signalally connected to the second element through other elements or connection means.

[0050] In addition, unless otherwise specified in the instructions, any singular term also includes the meaning of the plural.

[0051] The above are merely preferred embodiments of this disclosure. Any equivalent changes and modifications made in accordance with the claims of this disclosure shall fall within the scope of this disclosure.

[0052] Symbol Explanation

[0053] 100, 400, 900: Analog circuits

[0054] 110, 410, 910: Voltage regulator

[0055] 120,420,920[0]~920[n]: Analog-to-digital converter

[0056] 130, 430, 930: Multiplexer

[0057] 132,432[0]~432[n],932[0]~932[n]: Switching circuit

[0058] 134,434[0]~434[n],934[0]~934[n]: Switching circuit

[0059] 140,440[0]~440[n],940[0]~940[n]: Comparators

[0060] 200: Digital Low Dropout Linear Regulator

[0061] 210: Analog-to-digital converter

[0062] 220: Control Circuit

[0063] 212[0]~212[n]: Comparator

[0064] 230: Power Transistor

[0065] 240: Trigger circuit

[0066] 300: Incremental Trigonometric Integral Analog-to-Digital Converter

[0067] 310: Sampling circuit

[0068] 320: Integrator

[0069] 330: Sampling Circuit

[0070] 340: Integrator

[0071] 350: Logic Circuits

[0072] 360: Quantizer

[0073] 500: Control Circuit

[0074] 510, 520: Registers

[0075] 530, 540: Logic circuits

[0076] 700: Trigonometric Integral Modulator

[0077] 710, 720: Integrator

[0078] 730: Quantizer

[0079] 800: Continuous Approximation Analog-to-Digital Converter

[0080] 810: Sampling Capacitor Array

[0081] 820: Comparator

[0082] 830: Continuous Approximation Logic Circuit

[0083] Pload, Vsta, Vsta[0]~Vsta[n], Vcnt: Control signal

[0084] Vload,Vload[0]~Vload[n]: Load voltage

[0085] Dcod[0]~Dcod[n]: Numeric code

[0086] Vout: Output voltage

[0087] Vin,Vin[0]~Vin[n],Vinn,Vinp: Input voltage

[0088] Dout, Doutn, Doutp, Dout[0]~Dout[n]: Digital signals

[0089] Sw,Sw[0]~Sw[n]: Multiplexing signals

[0090] Sw,Swb[0]~Swb[n]: Multiplexed signals

[0091] Clk: Clock signal

[0092] Clk': Delayed clock signal

[0093] Vrefn: Negative reference voltage

[0094] Vrefp: Positive reference voltage

[0095] A1, A2, B1, B2, P1, P2: Switch signals

[0096] Vdd: Operating voltage

[0097] D: Data input terminal

[0098] CK: Clock input

[0099] Q: Forward data output terminal

[0100] QB: Reverse data output terminal

Claims

1. An analog circuit comprising: a voltage regulator for generating an output voltage; at least one analog-to-digital converter for generating at least one digital signal; at least one comparator; and a multiplexer coupled to the voltage regulator, the at least one analog-to-digital converter, and the at least one comparator for conducting the at least one comparator to one of the voltage regulator and the at least one analog-to-digital converter; wherein when the voltage regulator is triggered, the multiplexer conducts the at least one comparator to the voltage regulator, and the voltage regulator generates the output voltage in accordance with an output of the at least one comparator; wherein when the at least one analog-to-digital converter is triggered, the multiplexer conducts the at least one comparator to the at least one analog-to-digital converter, and the at least one analog-to-digital converter generates the at least one digital signal in accordance with the output of the at least one comparator.

2. The analog circuit of claim 1, wherein, The at least one comparator operates as part of an integrator of the at least one analog-to-digital converter when the at least one analog-to-digital converter is triggered.

3. The analog circuit of claim 1, wherein, The at least one comparator comprises a plurality of comparators, the multiplexer is coupled to the voltage regulator, the plurality of analog-to-digital converters, and the plurality of comparators, and the multiplexer is for conducting the plurality of comparators to one of the voltage regulator and the plurality of analog-to-digital converters; wherein when the voltage regulator is triggered, the multiplexer conducts the plurality of comparators to the voltage regulator, and the voltage regulator generates the output voltage in accordance with outputs of the plurality of comparators; wherein when the plurality of analog-to-digital converters are triggered, the multiplexer conducts the plurality of comparators to the plurality of analog-to-digital converters, and the plurality of analog-to-digital converters generate the plurality of digital signals in accordance with the outputs of the plurality of comparators.

4. The analog circuit of claim 3, wherein, The plurality of comparators respectively operate as parts of a plurality of integrators of the plurality of analog-to-digital converters when the plurality of analog-to-digital converters are triggered.

5. The analog circuit of claim 1, wherein, The at least one analog-to-digital converter comprises a delta-sigma modulator, and the at least one comparator operates as a quantizer of the delta-sigma modulator when the multiplexer conducts the at least one comparator to the at least one analog-to-digital converter.

6. The analog circuit of claim 1, wherein, The at least one analog-to-digital converter comprises a successive approximation analog-to-digital converter, and the successive approximation analog-to-digital converter comprises a successive approximation logic circuit and a sampling capacitor array; wherein the at least one comparator is coupled between the successive approximation logic circuit and the sampling capacitor array when the multiplexer conducts the at least one comparator to the at least one analog-to-digital converter.

7. The analog circuit of claim 1, wherein, The at least one analog-to-digital converter comprises a plurality of analog-to-digital converters, the at least one comparator comprises a plurality of comparators, the multiplexer is coupled to the voltage regulator, the plurality of analog-to-digital converters, and the plurality of comparators, and the multiplexer is for conducting the plurality of comparators to one of the voltage regulator and the plurality of analog-to-digital converters; wherein when the voltage regulator is triggered, the multiplexer conducts the plurality of comparators to the voltage regulator, and the voltage regulator generates the output voltage in accordance with outputs of the plurality of comparators; wherein when the plurality of analog-to-digital converters are triggered, the multiplexer conducts the plurality of comparators to the plurality of analog-to-digital converters, and the plurality of analog-to-digital converters generate the plurality of digital signals in accordance with the outputs of the plurality of comparators. wherein when one or more of the plurality of analog-to-digital converters is triggered, the multiplexer turns on a corresponding one or more of the plurality of comparators to the one or more analog-to-digital converters, respectively, and the one or more analog-to-digital converters generates one or more of the at least one digital signals in accordance with outputs of the one or more comparators.

8. A comparator sharing method for analog circuits, comprising: when a voltage regulator is triggered, turning on at least one comparator to the voltage regulator using a multiplexer, wherein the voltage regulator generates an output voltage of the voltage regulator in accordance with an output of the at least one comparator; and when at least one analog-to-digital converter is triggered, turning on the at least one comparator to the at least one analog-to-digital converter using the multiplexer, wherein the at least one analog-to-digital converter generates at least one digital signal of the at least one analog-to-digital converter in accordance with an output of the at least one comparator; wherein the multiplexer is coupled to the voltage regulator, the at least one analog-to-digital converter, and the at least one comparator.

9. The method of claim 8, wherein, when the at least one analog-to-digital converter is triggered, the at least one comparator operates as part of an integrator of the at least one analog-to-digital converter.

10. The method of claim 8, wherein, the at least one comparator comprises a plurality of comparators, and the multiplexer is coupled to the voltage regulator, the at least one analog-to-digital converter, and the plurality of comparators; wherein when the voltage regulator is triggered, turning on the at least one comparator to the voltage regulator using the multiplexer comprises: when the voltage regulator is triggered, turning on all of the plurality of comparators to the voltage regulator using the multiplexer, and the voltage regulator generates the output voltage in accordance with outputs of the plurality of comparators; wherein when the at least one analog-to-digital converter is triggered, turning on the at least one comparator to the at least one analog-to-digital converter using the multiplexer comprises: when the at least one analog-to-digital converter is triggered, turning on all of the plurality of comparators to the at least one analog-to-digital converter using the multiplexer, and the at least one analog-to-digital converter generates the at least one digital signal in accordance with outputs of the plurality of comparators.

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