Hardware-assisted dynamic random access memory (DRAM) row merging

Abstract

Hardware-assisted dynamic random access memory (DRAM) row merging includes identifying, by a memory controller, multiple rows in a DRAM module storing the same data; storing, in a mapping table, data mapping one or more of the multiple rows to another row; and excluding the one or more rows from refresh of the DRAM module.

Description

Background Technology

[0001] Dynamic random access memory (DRAM) rows must be flushed to ensure data integrity. DRAM flushing constitutes a significant portion of the power consumed by the memory module. In some environments, multiple rows of DRAM store the same value. Attached Figure Description

[0002] Figure 1 This is a block diagram of an exemplary system for hardware-assisted DRAM row merging according to some implementation schemes.

[0003] Figure 2 This is a flowchart of an exemplary method for hardware-assisted DRAM row merging according to some implementation schemes.

[0004] Figure 3 This is a flowchart of an exemplary method for hardware-assisted DRAM row merging according to some implementation schemes.

[0005] Figure 4 This is a flowchart of an exemplary method for hardware-assisted DRAM row merging according to some implementation schemes.

[0006] Figure 5 This is a flowchart of an exemplary method for hardware-assisted DRAM row merging according to some implementation schemes.

[0007] Figure 6 This is a flowchart of an exemplary method for hardware-assisted DRAM row merging according to some implementation schemes.

[0008] Figure 7 This is a flowchart of an exemplary method for hardware-assisted DRAM row merging according to some implementation schemes.

[0009] Figure 8 This is a flowchart of an exemplary method for hardware-assisted DRAM row merging according to some implementation schemes. Detailed Implementation

[0010] In some implementations, hardware-assisted dynamic random access memory (DRAM) row merging includes, among other things, the memory controller identifying multiple rows storing the same data within the DRAM module. Hardware-assisted DRAM row merging also includes storing data in a mapping table that maps one or more rows of the multiple rows to another row, and excluding the one or more rows from refreshes of the DRAM module.

[0011] In some embodiments, hardware-assisted DRAM row merging further includes updating a bitmap to indicate that the one or more rows are excluded from the refresh. In such embodiments, excluding one or more rows from the refresh includes providing a bitmap to the DRAM module by the memory controller. In some embodiments, another row includes rows among multiple rows. In other embodiments, another row includes reserved rows included in one or more reserved rows of the DRAM module. In some embodiments, hardware-assisted DRAM row merging further includes determining that a single row is mapped to a reserved row. In response to such determination, the memory controller stores the data stored in the reserved row in the single row and updates the mapping table to remove the mapping of the single row to the reserved row. In some embodiments, hardware-assisted DRAM row merging further includes maintaining a counter indicating the number of rows mapped to the reserved row. In such embodiments, determining that a single row is mapped to the reserved row is based on the counter. In some embodiments, hardware-assisted DRAM row merging further includes maintaining a mapping table cache that stores a portion of the mapping table. In some embodiments, hardware-assisted DRAM row merging further includes receiving a read request for a row among the one or more rows. In response to a received read request, the memory controller determines, based on a mapping table, that the row is mapped to another row and provides the data stored in that other row. In some implementations, hardware-assisted DRAM row merging further includes receiving a write request for a specific row within the one or more rows. In response to the write request, the memory controller stores the data stored in the reserved row in the specific row of the one or more rows. The memory controller then executes the write request and updates the mapping table to remove the mapping from the specific row to the reserved row.

[0012] In some implementations, the memory controller for hardware-assisted DRAM row merging performs the step of identifying, among other things, multiple rows storing the same data in the DRAM module. This step further includes storing data in a mapping table that maps one or more of the multiple rows to another row, and excluding the one or more rows from refreshes of the DRAM module.

[0013] In some embodiments, the step further includes updating a bitmap to indicate that the one or more rows are excluded from the refresh. In such embodiments, excluding one or more rows from the refresh includes providing a bitmap to the DRAM module by the memory controller. In some embodiments, the other row includes rows among multiple rows. In other embodiments, the other row includes reserved rows included in one or more reserved rows of the DRAM module. In some embodiments, the step further includes determining that a single row is mapped to a reserved row. In response to such determination, the memory controller stores the data stored in the reserved row in the single row and updates the mapping table to remove the mapping of the single row to the reserved row. In some embodiments, the step further includes maintaining a counter indicating the number of rows mapped to the reserved row. In such embodiments, determining that the single row is mapped to the reserved row is based on the counter. In some embodiments, the step further includes maintaining a mapping table cache that stores a portion of the mapping table. In some embodiments, the step further includes receiving a read request for a row among the one or more rows. In response to receiving a read request, the memory controller determines, based on the mapping table, that the row is mapped to another row and provides the data stored in the other row. In some implementations, this step further includes receiving a write request for a specific row within the one or more rows. In response to the write request, the memory controller stores the data that was stored in the reserved row in the specific row of the one or more rows. The memory controller then executes the write request and updates the mapping table to remove the mapping from the specific row to the reserved row.

[0014] In some embodiments, the means for hardware-assisted DRAM row merging includes a memory controller that performs the steps of identifying, among other things, multiple rows storing the same data in the DRAM module. This step further includes storing data in a mapping table that maps one or more of the multiple rows to another row, and excluding the one or more rows from refreshes of the DRAM module.

[0015] In some implementations, this step further includes updating the bitmap to indicate that the one or more rows are excluded from the refresh. In such implementations, excluding one or more rows from the refresh includes providing a bitmap to the DRAM module from the memory controller.

[0016] Figure 1This is a block diagram of a non-limiting exemplary system 100. Exemplary system 100 can be implemented in various devices, including a central processing unit (CPU), a graphics processing unit (GPU), etc. System 100 includes a memory controller 102 and one or more dynamic random access memory (DRAM) modules 106. Each DRAM module 104 includes multiple rows 106 for storing data. The memory controller 102 processes read and write requests issued to the DRAM modules 104. For example, the memory controller 102 maintains a queue of read and write requests and issues the queued request to the specific DRAM module 104 to which the request is directed.

[0017] Row 106 is volatile memory used to store data. Because row 106 is volatile, it must be refreshed periodically to maintain the integrity of the stored data. These refreshes constitute a significant portion of the power consumed by DRAM module 104. In many environments, multiple rows 106 within the same DRAM module 104 store the same data. That is, each value in one row 106 is the same as each value in one or more other rows 106. For example, in an environment where multiple virtual machines run on the same hardware and execute the same software or operating system, the data stored in the portion of DRAM allocated to each virtual machine will be at least partially identical.

[0018] Existing solutions for addressing identical data across rows in DRAM include software modules managed by a hypervisor or other agent that deduplicate data from the same row. However, to reduce bottlenecks involving DRAM content deduplication, these modules typically only execute when the total available memory in the system falls below a threshold. Furthermore, because these solutions are software-based, computational overhead and resources are required to deduplicate data stored in DRAM.

[0019] Instead of using a software-based solution (which requires considerable computational overhead and is limited to execution when total system memory drops below a threshold), system 100 uses a hardware-based approach to merge rows 106 within DRAM module 104 that store the same data. Memory controller 102 identifies multiple rows storing the same data within DRAM module 104. For example, these multiple rows may each comprise row 106 of DRAM module 104. As another example, these multiple rows may include one or more rows 106 that share the same data with reserved row 108. Reserved row 108 is a row of memory in DRAM module 104 reserved for storing data from row 106, which is identified as storing the same data. In other words, while row 106 is used to serve read and write operations from other processes or agents, reserved row 108 is specifically used to store data from row 106 that is identified as storing the same data.

[0020] In some implementations, the identification of multiple rows storing the same data is performed at predetermined intervals or in response to another event. For example, memory controller 102 identifies two or more rows within row 106 storing the same data in response to the occurrence of an event. As another example, memory controller 102 identifies one or more rows within row 106 storing the same data as reserved row 108 in response to the occurrence of an event. In some implementations, the identification of multiple rows is performed in response to a read or write request issued to row 106. For example, memory controller 102 compares data read from or to be written to row 106 with data in another row 106 or with reserved row 108. In some implementations, this includes performing a checksum 110 or hash of the data read from or written to row 106 and comparing it with one or more stored checksums 110, as will be described in more detail below.

[0021] The memory controller 102 then stores data in a mapping table 112 that maps one or more rows of rows to another. Each entry in the mapping table 112 maps row 106 in the DRAM module 104 to another row, where the other row stores the same data as the last data stored in the row 106 to which it is mapped. Although the mapping table 112 is shown as being stored in the DRAM module 104, it should be understood that in some embodiments, the mapping table 112 is alternatively stored in the memory controller 102.

[0022] In some implementations, storing data that maps one or more rows to another row includes storing data that maps one or more of a plurality of identified rows 106 to another row 106 of a plurality of identified rows 106. For example, suppose memory controller 102 identifies rows 106A, 106B, 106C, and 106D as each storing the same data. In such an example, memory controller 102 stores entries in mapping table 112 that map rows 106A, 106B, and 106C to row 106D. In this example, row 106D is considered the “representative row” because the remaining rows are mapped to row 106D. Furthermore, in this example, row 106D is arbitrarily selected as the representative row, and it should be understood that the other rows 106 are possible representative rows.

[0023] For example, suppose memory controller 102 identifies rows 106A, 106B, 106C, and 106D as storing the same data. Then, memory controller 102 stores the data equivalent to that in rows 106A, 106B, 106C, and 106D in reserved row 108, and stores entries in mapping table 112 that map rows 106A, 106B, 106C, and 106D to reserved row 108. In another example, suppose memory controller 102 identifies rows 106A, 106B, and 106C as storing data equivalent to that already stored in reserved row 108. Then, memory controller 102 stores entries in mapping table 112 that map rows 106A, 106B, and 106C to reserved row 108.

[0024] Then, memory controller 102 excludes one or more rows 106 (e.g., those rows 106 mapped to another row in mapping table 112) from the refresh of DRAM module 104. For example, memory controller 102 provides DRAM module 104 with an indication of which rows 106 should or should not be refreshed during the next refresh operation. In some embodiments, memory controller 102 maintains refresh bitmap 114. Each row 106 corresponds to a bit in refresh bitmap 114. In the case where row 106 is mapped to another row (e.g., to representative row or reserved row 108), the bit corresponding to the mapped row 106 is set (e.g., to "1") to indicate that the mapped row 106 should be skipped during the next refresh. For example, when an entry in mapping table 112 is created to map a particular row 106, the bit in refresh bitmap 114 corresponding to the particular row 106 is set to indicate that the particular row 106 is excluded from the next refresh. Therefore, in some implementations, excluding one or more rows 106 from the refresh includes providing a refresh bitmap 114 to the DRAM module 104. The DRAM module 104 then performs a refresh operation based on the refresh bitmap 114.

[0025] As described above, one or more rows 106 that store the same data as another row (e.g., the representative row or reserved row 108) are excluded from the refresh operation, thereby saving energy compared to refreshing those rows 106. Such rows 106 are referred to below as "merged rows 106". Read operations targeting these merged rows 106 are serviced by accessing the mapping table 112 to determine the location where the merged rows 106 are mapped (e.g., the target of the mapping), and then the corresponding data is loaded from the target of the mapping.

[0026] As explained above, merge row 106 is alternatively mapped to a representative row (included in row 106) or to a reserved row 108. Since the representative row can still be the target of write requests, mapping to the representative row during a write operation carries the risk of significant overhead. For example, when writing to the representative row, the data stored in the representative row should be copied to another row, and any mapping table 112 entries mapped to the representative row should be updated to that other row. Therefore, in a preferred embodiment, when reserved row 108 is only written to store data from merge row 106, the row 106 to be merged is mapped to reserved row 108.

[0027] In some implementations, for each reserved row 108, the memory controller 102 maintains a corresponding counter 116 indicating the number of merged rows 106 mapped to reserved row 108. For example, when a mapping table 112 entry is created to map merged rows 106 to reserved rows 108, the memory controller 102 increments the counter 116 corresponding to reserved row 108. When merged rows 106 stop mapping to reserved rows 108 (e.g., in response to a write to merged row 106), the counter 116 corresponding to reserved row 108 is decremented. In some implementations, the counter 116 is maintained in the same data structure as a checksum 110 for each reserved row 108. For example, each entry in the data structure corresponds to a reserved row 108. For a corresponding reserved row 108, each entry in the data structure indicates a checksum 110 of the data stored in the reserved row 108 (if any) and a counter 116 indicating the number of merged rows 106 mapped to reserved row 108.

[0028] Therefore, in some implementations, the memory controller 102 determines when a single row 106 is mapped to a reserved row 108. For example, the memory controller 102 determines when a counter 116 corresponding to the reserved row 108 is set to "1". As another example, the memory controller 102 accesses the mapping table 112 entries mapped to the reserved row 108 and determines that a single mapping table 112 is mapped to the reserved row 108.

[0029] In response to determining that a single row 106 is mapped to a reserved row 108, the memory controller 102 stores the data already stored in the reserved row 108 in the single row 106. For example, the memory controller 102 sends a command to the DRAM module 104, which causes the data stored in the reserved row 108 to be copied or cloned to the single row 106 mapped to the reserved row 106. This ensures that the single row 106 stores the correct data even if the data previously stored in the single row 106 has been weakened due to lack of refresh. The memory controller 102 then updates the mapping table 112 to remove the mapping of the single row 106 to the reserved row 108. In some embodiments, the memory controller 102 then decrements the counter corresponding to the reserved row 108 to zero. In some embodiments, this indicates that the reserved row 108 is not allocated and can be used to store additional data for mapping other rows 106 for merging. In some embodiments, the memory controller 102 updates the refresh bitmap 114 to indicate that a single row 106 that is no longer mapped to any reserved row 108 should be included in the next refresh.

[0030] As described above, in some embodiments, the memory controller 102 maintains a checksum 110 for the data stored in each reserved row 108. This checksum 110 facilitates the determination of whether data read from or written to row 106 matches reserved row 108. For example, in response to a write request for row 106, the memory controller 102 determines that the data to be written matches reserved row 108. Instead of executing the write request, the memory controller 102 creates a mapping table 112 entry that maps row 106, the target of the write request, to reserved row 108. In some embodiments, the memory controller 102 then updates the refresh bitmap 114 to indicate that row 106 (now merged row 106), the target of the write request, is excluded from the refresh of DRAM module 104. As another example, in response to a read request for row 106, the memory controller 102 determines, based on the checksum 110, that the read data matches data stored in reserved row 108. Then, the memory controller 102 creates a mapping table 112 entry that maps read line 106 to reserved line 108, and updates the refresh bitmap 114 to exclude read line 106 from the refresh of DRAM module 104.

[0031] In some implementations, the memory controller 102 maintains a mapping table cache 118 that stores the most recently or most frequently used mappings in mapping table 112. For example, the memory controller 102 accesses mapping table 112 to determine whether row 106, the target of a read or write request, is mapped to another row (e.g., a representative row or reserved row 108). If the memory controller 102 finds a match in mapping table 112, the memory controller 102 updates mapping table cache 118 to include the matching mapping table 112 entry. Therefore, a read or write request is first compared with an entry in mapping table cache 118 before accessing mapping table 112, thereby reducing the number of accesses to the DRAM module 104 required to determine whether a particular row 106 has been merged and mapped to another row.

[0032] In response to a read request for row 106 of DRAM module 104, memory controller 102 determines whether row 106 has been merged and mapped to another row (e.g., a representative row or reserved row 108). For example, memory controller 102 accesses mapping table cache 118 to determine if an entry for mapping row 106 exists. If no entry is found, or mapping table cache 118 is not implemented, memory controller 102 accesses mapping table 112 to determine if an entry for mapping row 106 exists. If an entry exists in mapping table cache 118 or mapping table 112, the row and stored data that are the target of the mapping indicated in the accessed entry are retrieved. This data is then returned in response to the read request. In some embodiments, the identified entry of mapping table 112 is added to mapping table cache 118.

[0033] In response to a write request to row 106 in DRAM module 104, memory controller 102 determines whether row 106 has been merged and mapped to reserved row 108. For example, memory controller 102 accesses mapping table cache 118 to determine if an entry exists that maps row 106 to reserved row 108. If no entry is found, or mapping table cache 118 is not implemented, memory controller 102 accesses mapping table 112 to determine if an entry exists that maps row 106 to reserved row 108.

[0034] If an entry exists in mapping table cache 118 or mapping table 112, reserved row 108 is accessed, and its contents are copied to row 106, the target of the write request. The write request is then applied to row 106. The mapping table 112 entry that maps row 106 to reserved row 108 (and, if present, the mapping table cache entry 118) is removed. In some implementations, a counter 116 corresponding to reserved row 108 is decremented.

[0035] To further explain, Figure 2A flowchart illustrating an exemplary method for hardware-assisted DRAM row merging is provided. The method includes identifying multiple rows 202 (e.g., by memory controller 102) in DRAM module 104 that store the same data. For example, each of the multiple rows includes row 106 of DRAM module 104. As another example, the multiple rows include one or more rows 106 and a reserved row 108, wherein the one or more rows 106 share the same data with the reserved row 108. For example, in some embodiments, the reserved row 108 stores data by means of previous merging and mapping other rows 106 to the reserved row.

[0036] In some implementations, the identification of multiple rows storing the same data is performed at predetermined intervals or in response to another event. For example, memory controller 102 identifies two or more rows within row 106 storing the same data in response to the occurrence of an event. As another example, memory controller 102 identifies one or more rows 106 storing the same data as reserved row 108 within row 106. In some implementations, the identification of multiple rows is performed in response to a read or write request issued to row 106. For example, memory controller 102 compares data read from or to be written to row 106 with data in another row 106 or with reserved row 108.

[0037] Figure 2 The method also includes storing in mapping table 112 data that maps one or more rows 106 of a plurality of rows to another row. Each entry in mapping table 112 maps row 106 of DRAM module 104 to another row, wherein the other row stores the same data as the last data stored in the row 106 to which it is mapped. In some embodiments, the other row includes row 106 of DRAM module 104 (e.g., row 106 capable of being used for read and write requests). In other embodiments, the other row to which row 106 is mapped includes reserved row 108, which is reserved for storing data and mapped to row 106. Although mapping table 112 is shown as being stored in DRAM module 104, it should be understood that in some embodiments, mapping table 112 is alternatively stored in memory controller 102.

[0038] In some implementations, storing data 204 that maps one or more rows 106 to another row includes storing data that maps one or more of a plurality of identified rows 106 to another of a plurality of identified rows 106. For example, suppose memory controller 102 identifies rows 106A, 106B, 106C, and 106D as each storing the same data. In such an example, memory controller 102 stores entries in mapping table 112 that map rows 106A, 106B, and 106C to row 106D. In this example, row 106D is considered the “representative row” because the remaining rows 106 are mapped to that row 106D. Furthermore, in this example, row 106D is arbitrarily selected as the representative row, and it should be understood that the other rows 106 are possible representative rows and can be selected according to various criteria.

[0039] For example, suppose memory controller 102 identifies rows 106A, 106B, 106C, and 106D as storing the same data. Then, memory controller 102 stores the data equivalent to that in rows 106A, 106B, 106C, and 106D in reserved row 108, and stores entries in mapping table 112 that map rows 106A, 106B, 106C, and 106D to reserved row 108. In another example, suppose memory controller 102 identifies rows 106A, 106B, and 106C as storing data equivalent to that already stored in reserved row 108. Then, memory controller 102 stores entries in mapping table 112 that map rows 106A, 106B, and 106C to reserved row 108.

[0040] Figure 2 The method further includes excluding one or more rows 106 (e.g., those rows 106 mapped to another row in mapping table 112) from the refresh exclusion 206 of DRAM module 104 (e.g., by memory controller 102). Rows 106 having entries in mapping table 112 and being excluded from refresh are considered “merged rows” 106. In some embodiments, excluding one or more rows 106 from refresh 206 includes providing the DRAM module 104 with an indication of which rows 106 should or should not be refreshed during the next refresh operation. The DRAM module 104 then performs a refresh based on the received indication.

[0041] To explain further, Figure 3 A method for hardware-assisted DRAM row merging according to an embodiment of the present disclosure is described. Figure 3 The method is similar to Figure 2 The similarities are Figure 3The method includes identifying multiple rows storing the same data in 202, storing in mapping table 112 the data that maps one or more rows 106 of the multiple rows to another row in 204, and excluding one or more rows 106 from the refresh of DRAM module 104.

[0042] Figure 3 and Figure 2 The difference is Figure 3 This includes updating bitmap 302 (e.g., refreshing bitmap 114) to indicate that one or more rows 106 are excluded from the refresh. For example, in some embodiments, memory controller 102 maintains refresh bitmap 114. Each row 106 corresponds to a bit in refresh bitmap 114. When row 106 is mapped to another row (e.g., to a representative row or reserved row 108), the bit corresponding to the mapped row 106 (e.g., row 106 with an entry in mapping table 112) is set (e.g., to "1") to indicate that the mapped row 106 should be skipped during the next refresh. For example, when mapping table 112 entries are created to map a particular row 106, the bit in refresh bitmap 114 corresponding to the particular row 106 is set to indicate that the particular row 106 is excluded from the next refresh.

[0043] Figure 3 The method further with Figure 3 The difference lies in that excluding one or more rows 106 from refresh 206 includes providing a 304 bitmap (e.g., refresh bitmap 114) to the DRAM module 104. The DRAM module 104 then performs a refresh operation based on the received bitmap.

[0044] To explain further, Figure 4 A method for hardware-assisted DRAM row merging according to an embodiment of the present disclosure is described. Figure 4 The method is similar to Figure 2 The similarities are Figure 4 The method includes identifying multiple rows storing the same data in 202, storing in mapping table 112 the data that maps one or more rows 106 of the multiple rows to another row in 204, and excluding one or more rows 106 from the refresh of DRAM module 104 104.

[0045] Suppose that one or more rows 106 are mapped to another row, which is reserved row 108. Figure 4 and Figure 2 The difference lies in Figure 4The method involves determining that a single row 106 is mapped to reserved row 108. Suppose that after multiple rows 106 have been mapped to reserved row 108, but all of these rows 106 cease to be mapped to reserved row 108. For example, a write operation is performed targeting mapped rows 106 instead of a single row 106. This will cause the row 106 targeted by the write operation to store a value different from the mapped reserved row 108, thus forcing row 106 to no longer be mapped to reserved row 108.

[0046] In some implementations, determining that a single row 106 is mapped to reserved row 108 includes determining when a counter 116 indicating the number of rows 106 mapped to reserved row 108 is set to "1". As another example, determining that a single row 106 is mapped to reserved row 108 includes accessing the mapping table 112 entries mapped to reserved row 108 and determining that a single mapping table 112 is mapped to reserved row 108.

[0047] Figure 4 The method further includes storing the data 404 already stored in reserved row 108 in a single row 106. For example, memory controller 102 sends a command to DRAM module 104, which causes the data stored in reserved row 108 to be copied or cloned to the single row 106 mapped to reserved row 106. This ensures that the single row 106 stores the correct data even if the data previously stored in the single row 106 has been degraded due to lack of refresh.

[0048] Figure 4 The method further includes updating mapping table 112 (406) to remove the mapping of a single row 106 to reserved row 108. In some embodiments, memory controller 102 then decrements counter 116 corresponding to reserved row 108 to zero. In some embodiments, this indicates that reserved row 108 is not allocated and can be used to store additional data for mapping other rows 106 for merging. In some embodiments, memory controller 102 updates refresh bitmap 114 to indicate that a single row 106 that is no longer mapped to any reserved row 108 should be included in the next refresh.

[0049] To explain further, Figure 5 A method for hardware-assisted DRAM row merging according to an embodiment of the present disclosure is described. Figure 5 The method is similar to Figure 4 The similarities are as follows Figure 5The method includes identifying 202 multiple rows storing the same data, storing in mapping table 112 data that maps one or more rows 106 of the multiple rows to another row, excluding 206 one or more rows 106 from the refresh of DRAM module 104, determining 402 a single row 106 is mapped to a reserved row 108, storing in the single row 106 data that has been stored in the reserved row 108, and updating 406 mapping table 112 to remove the mapping of the single row 106 to the reserved row 108.

[0050] Figure 5 Methods and Figure 4 The difference lies in Figure 5 The method includes maintaining a counter 116 that indicates the number of rows 106 mapped to reserved rows 108. For example, for each reserved row 108, the memory controller 102 maintains a corresponding counter 116 that indicates the number of merged rows 106 mapped to reserved rows 108. For example, when a mapping table 112 entry is created to map merged rows 106 to reserved rows 108, the memory controller 102 increments the counter 116 corresponding to the reserved row 108. When merged rows 106 stop mapping to reserved rows 108 (e.g., in response to a write to merged rows 106), the counter 116 corresponding to the reserved row 108 is decremented. In some embodiments, the counter 116 is maintained in the same data structure as a checksum 110 for each reserved row 108. For example, each entry in the data structure corresponds to a reserved row 108. For the corresponding reserved row 108, each entry in the data structure indicates a checksum 110 of the data stored in the reserved row 108 (if any) and a counter 116 indicating the number of merged rows 106 mapped to the reserved row 108.

[0051] Figure 5 Methods and Figure 4 A further difference lies in determining that 402 a single row 106 is mapped to reserved row 108, which includes determining 504 a single row 106 is mapped to reserved row 108 based on counter 116. For example, memory controller 102 accesses counter 116 for reserved row 108 and determines that counter 116 is set to "1".

[0052] To explain further, Figure 6 A method for hardware-assisted DRAM row merging according to an embodiment of the present disclosure is described. Figure 6 The method is similar to Figure 2 The similarities are Figure 6The method includes identifying multiple rows storing the same data in 202, storing in mapping table 112 the data that maps one or more rows 106 of the multiple rows to another row in 204, and excluding one or more rows 106 from the refresh of DRAM module 104.

[0053] Figure 6 and Figure 2 The difference lies in Figure 6 This includes (e.g., by memory controller 102) a mapping table cache 118 that maintains a portion of the 602 storage mapping table 112. The mapping table cache 118 stores the most recently or most frequently used mappings in the mapping table 112. For example, memory controller 102 accesses mapping table 112 to determine if row 106, the target of a read or write request, is mapped to another row (e.g., a representative row or reserved row 108). If memory controller 102 finds a match in mapping table 112, memory controller 102 updates mapping table cache 118 to include that matching mapping table 112 entry. Therefore, before accessing mapping table 112, a read or write request is first compared with entries in mapping table cache 118, thereby reducing the number of accesses to the DRAM module 104 required to determine whether a particular row 106 has been merged and mapped to another row.

[0054] To explain further, Figure 7 A method for hardware-assisted DRAM row merging according to an embodiment of the present disclosure is described. Figure 7 The method is similar to Figure 2 The similarities are Figure 7 The method includes identifying multiple rows storing the same data in 202, storing in mapping table 112 the data that maps one or more rows 106 of the multiple rows to another row in 204, and excluding one or more rows 106 from the refresh of DRAM module 104.

[0055] Figure 7 and Figure 2 The difference lies in Figure 7 This includes (e.g., by memory controller 102) receiving 702 read requests for one or more rows 106 (e.g., merged rows 106 previously mapped to another row and excluded from refresh). For example, assume rows 106A, 106B, and 106C are identified as storing the same data and mapped to reserved row 108. Further assume the read request is for data stored in row 106A. Since the data stored in row 106A has been excluded from refresh, the data stored in row 106A is susceptible to loss of integrity.

[0056] Figure 7The method further includes determining, based on mapping table 112, that row 106 is mapped to another row. Continuing the example above, memory controller 102 determines, based on mapping table 112, that row 106A is mapped to its corresponding reserved row 108. For example, in some embodiments, memory controller 102 accesses mapping table 112 from DRAM module 104 and identifies an entry for row 106A in mapping table 112. This entry then indicates the corresponding reserved row 108. In other embodiments, memory controller 102 first accesses mapping table cache 118 to determine if an entry for row 106A is stored. If an entry is stored, the memory controller identifies the corresponding reserved row 108 based on the entry in mapping table cache 118. If no entry for row 108A is found, memory controller 102 then accesses mapping table 112 from DRAM module 104 as described above.

[0057] Figure 7 The method also includes providing data 706 stored in another row (e.g., the row identified in mapping table 112 to which merge row 106 is mapped) in response to a read request. For example, memory controller 102 reads from the row identified in mapping table 112 and provides the requested data as a response to the read request. Thus, in response, a read request for merge row 106 receives data stored in the row identified in mapping table 112 as the target of the mapping of merge row 106.

[0058] To explain further, Figure 8 A method for hardware-assisted DRAM row merging according to an embodiment of the present disclosure is described. Figure 8 The method is similar to Figure 2 The similarities are Figure 8 The method includes identifying multiple rows storing the same data in 202, storing in mapping table 112 the data that maps one or more rows 106 of the multiple rows to another row in 204, and excluding one or more rows 106 from the refresh of DRAM module 104.

[0059] Suppose that one or more rows 106 are mapped to reserved row 108. Figure 8 Unlike Figure 2 The difference is Figure 8 The method includes receiving a write request at 802 for one or more rows 106 (e.g., merged rows 106 mapped to reserved rows 108 and excluded from refresh). For example, assume rows 106A, 106B, and 106C are identified as storing the same data and mapped to reserved rows 108. Further assume a read request is for data stored in row 106A. Since the data stored in row 106A has been excluded from refresh, the data stored in row 106A is susceptible to loss of integrity.

[0060] Figure 8 The method also includes storing 804 data already stored in reserved row 108 in row 106 of one or more rows 106. Continuing the example above, memory controller 102 determines, based on mapping table 112, that row 106A is mapped to its corresponding reserved row 108. For example, in some embodiments, memory controller 102 accesses mapping table 112 from DRAM module 104 and identifies an entry for row 106A in mapping table 112. This entry then indicates the corresponding reserved row 108. In other embodiments, memory controller 102 first accesses mapping table cache 118 to determine if an entry for row 106A is stored. If an entry is stored, the memory controller identifies the corresponding reserved row 108 based on the entry in mapping table cache 118. If no entry for row 108A is found, memory controller 102 then accesses mapping table 112 from DRAM module 104 as described above. Then, memory controller 102 loads the data stored in the identified reserved row 108 and stores that data in row A.

[0061] Figure 8 The method also includes executing the write request at 806. For example, memory controller 102 issues a write request to DRAM module 104 for use by an application. Thus, any operation of the write request is applied to line 106 indicated in the write request, which now stores data in its corresponding reserved line 108.

[0062] Figure 8 The method also includes updating mapping table 112 to remove the mapping from row 106 to reserved row 108. When row 106 has been written, it no longer stores the same data as reserved row 108. Therefore, the mapping from row 106 to reserved row 108 is removed from mapping table 112. If mapping table cache 118 is implemented, any mapping from row 106 to reserved row 108 is also removed from mapping table cache 118.

[0063] Based on the explanations above, the reader will recognize that the beneficial effects of hardware-assisted DRAM row merging include:

[0064] • Improve computing system performance by reducing the energy required to perform DRAM refreshes by suppressing the refresh of selected rows with the same data.

[0065] • Improves computing system performance by requiring less computational overhead compared to software-based solutions for data deduplication in DRAM.

[0066] The advantages and features of this disclosure can be further described by the following statements:

[0067] 1. A method for hardware-assisted row merging of a dynamic random access memory (DRAM), the method comprising: identifying, by a memory controller, multiple rows storing identical data in a DRAM module; storing in a mapping table data mapping one or more of the multiple rows to another row; and excluding the one or more rows from a refresh of the DRAM module.

[0068] 2. The method according to statement 1, comprising: updating a bitmap to indicate the exclusion of the one or more rows from the refresh, wherein excluding the one or more rows from the refresh includes providing the bitmap to the dynamic random access memory (DRAM) module by the memory controller.

[0069] 3. The method according to any one of statements 1 to 2, wherein the other row comprises a row among the plurality of rows.

[0070] 4. The method according to any one of statements 1 to 3, wherein the other row includes a reserved row contained in one or more reserved rows of the dynamic random access memory (DRAM) module.

[0071] 5. The method according to any one of statements 1 to 4, further comprising: determining that a single row is mapped to the reserved row; storing data already stored in the reserved row in the single row; and updating the mapping table to remove the mapping of the single row to the reserved row.

[0072] 6. The method according to any one of statements 1 to 5, further comprising: maintaining a counter indicating the number of rows mapped to the reserved rows, wherein determining that a single row is mapped to the reserved rows is based on the counter.

[0073] 7. The method according to any one of statements 1 to 6 further includes maintaining a mapping table cache that stores a portion of the mapping table.

[0074] 8. The method according to any one of statements 1 to 7, further comprising: receiving a read request for a row of the one or more rows; determining, based on the mapping table, that the row is mapped to the other row; and providing data stored in the other row in response to the read request.

[0075] 9. The method according to any one of statements 1 to 8, further comprising: receiving a write request for a specific row among the one or more rows; storing data already stored in the reserved row in the specific row among the one or more rows; executing the write request; and updating the mapping table to remove the mapping of the specific row to the reserved row.

[0076] 10. A memory controller for hardware-assisted dynamic random access memory (DRAM) row merging, the memory controller being configured to perform the steps of: identifying multiple rows storing the same data in a DRAM module; storing data in a mapping table that maps one or more of the multiple rows to another row; and excluding the one or more rows from a refresh of the DRAM module.

[0077] 11. The memory controller of statement 10, wherein the step further comprises: updating a bitmap to indicate that the one or more rows have been excluded from the refresh, wherein excluding the one or more rows from the refresh comprises providing the bitmap to the DRAM module by the memory controller.

[0078] 12. The memory controller according to any one of statements 10 to 11, wherein the other row comprises a row of the plurality of rows.

[0079] 13. The memory controller according to any one of statements 10 to 12, wherein the other row includes a reserved row contained in one or more reserved rows of the dynamic random access memory (DRAM) module.

[0080] 14. The memory controller according to any one of statements 10 to 13, wherein the steps include: determining that a single row is mapped to the reserved row; storing data stored in the reserved row in the single row; and updating the mapping table to remove the mapping of the single row to the reserved row.

[0081] 15. The memory controller according to any one of statements 10 to 14, wherein the step further comprises: maintaining a counter indicating the number of rows mapped to the reserved rows, wherein determining that a single row is mapped to the reserved row is based on the counter.

[0082] 16. The memory controller according to any one of statements 10 to 15, wherein the step further includes maintaining a mapping table cache that stores a portion of the mapping table.

[0083] 17. The memory controller according to any one of statements 10 to 16, wherein the step further comprises: receiving a read request for a row of the one or more rows; determining, based on the mapping table, that the row is mapped to the other row; and providing data stored in the other row in response to the read request.

[0084] 18. The memory controller according to any one of statements 10 to 17, wherein the step further comprises: receiving a write request for a specific row of the one or more rows; storing data stored in the reserved row in the specific row of the one or more rows; executing the write request; and updating the mapping table to remove the mapping of the row to the reserved row.

[0085] 19. An apparatus for hardware-assisted dynamic random access memory (DRAM) row merging, the apparatus comprising: a memory controller configured to perform the steps of: identifying a plurality of rows storing identical data in a DRAM module; storing data in a mapping table that maps one or more of the plurality of rows to another row; and excluding the one or more rows from a refresh of the DRAM module.

[0086] 20. The apparatus of statement 19, wherein the step further comprises: updating a bitmap to indicate that the one or more rows have been excluded from the refresh; and wherein excluding the one or more rows from the refresh comprises providing the bitmap to the DRAM module by the memory controller.

[0087] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible specific implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions indicated in the blocks may not occur in the order shown in the figures. For example, depending on the functions involved, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0088] As will be understood from the foregoing description, modifications and changes can be made to various embodiments of this disclosure. The description in this specification is for illustrative purposes only and should not be construed as limiting. The scope of this disclosure is defined only by the language of the appended claims.

Claims

1. A method for hardware-assisted row merging of dynamic random access memory (DRAM), the method comprising: The memory controller maps one or more rows from a plurality of rows storing the same data in the DRAM module to a representative row in a mapping table, wherein the representative row is selected from the plurality of rows storing the same data; Instructions to exclude stored mapping rows from refresh; as well as Based on the instruction, exclude the mapping row from the refresh.

2. The method according to claim 1, further comprising: Update the bitmap to indicate that the mapping row has been excluded from the refresh, wherein excluding the mapping row from the refresh includes the memory controller providing the bitmap to the DRAM module.

3. The method of claim 1, wherein the representative row includes a reserved row contained in one or more reserved rows of the DRAM module.

4. The method according to claim 3, further comprising: Determine which individual rows are mapped to the reserved rows; The data already stored in the reserved row is stored in the single row; as well as Update the mapping table to remove the mapping from the single row to the retained row.

5. The method according to claim 4, further comprising: Maintain a counter indicating the number of rows mapped to the reserved row, wherein determining that a single row is mapped to the reserved row is based on the counter.

6. The method of claim 1, further comprising maintaining a mapping table cache that stores a portion of the mapping table.

7. The method according to claim 1, further comprising: Receive read requests for rows in the mapped rows; Based on the mapping table, it is determined that the row is mapped to the representative row; as well as In response to the read request, the data stored in the representative row is provided.

8. The method according to claim 3, further comprising: Receive a write request for a specific row in the mapped row; The data stored in the reserved row is stored in the specific row of the mapped row; Execute the write request; as well as Update the mapping table to remove the mapping from the specific row to the retained row.

9. An apparatus for hardware-assisted row merging of dynamic random access memory (DRAM), the apparatus comprising: processor; Memory; A memory controller, which couples the processor to the memory, is configured to: In the mapping table, one or more rows of multiple rows storing the same data in the DRAM module are mapped to a representative row, which is selected from the multiple rows storing the same data; Instructions to exclude stored mapping rows from refresh; as well as Based on the instruction, exclude one or more rows from the refresh.

10. The apparatus of claim 9, wherein the memory controller is further configured to: Update the bitmap to indicate that the mapping row has been excluded from the refresh, wherein excluding the mapping row from the refresh includes the memory controller providing the bitmap to the DRAM module.

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