Pixel circuit for light emitting element

Abstract

A pixel circuit (300) comprises a pixel driver (302) configured to receive a data signal and to drive a light emitting element (D) based on the data signal (DATA[M]), a first power supply signal (V1) coupled through the pixel driver (302) to an anode of the light emitting element (D), and a second power supply signal (V2) coupled to a cathode of the light emitting element (D). The second power supply signal (V2) is configured to vary based on the data signal (DATA[M]). In a first period (T1) of the data signal (DATA[M]), a value of the second power supply signal (V2) is configured to be lower than a value of the first power supply signal (V1), and in a second period (T2) of the data signal (DATA[M]), the value of the second power supply signal (V2) is configured to be higher than the value of the first power supply signal (V1).

Description

Technical Field

[0001] The present disclosure relates generally to display technology and, more particularly, to pixel circuits. Background Art

[0002] In displays formed by organic light-emitting diodes (OLEDs), when a voltage is applied to the anode and cathode of the OLED, holes injected from the anode and electrons injected from the cathode combine in the OLED's light-emitting layer, thereby emitting light. When the OLED is under continuous forward bias, impurity ions can migrate and electric dipoles can move from their original positions. These changes in the OLED can form an electric field in the opposite direction to the electric field formed by the voltage. The driving current and brightness of the OLED will decrease, causing OLED degradation. Summary of the Invention

[0003] Embodiments of pixel circuits for light emitting elements are disclosed herein.

[0004] In one example, a pixel circuit includes a pixel driver configured to receive a data signal and drive a light-emitting element based on the data signal. A first power signal is coupled to an anode of the light-emitting element via the pixel driver, and a second power signal is coupled to a cathode of the light-emitting element. In some embodiments, the second power signal is configured to vary based on the data signal. In some embodiments, during a first cycle of the data signal, the value of the second power signal is configured to be lower than the value of the first power signal, and during a second cycle of the data signal, the value of the second power signal is configured to be higher than the value of the first power signal.

[0005] In another example, a circuit for driving multiple light-emitting elements includes multiple pixel circuits, each of the multiple pixel circuits being configured to drive one of a plurality of light-emitting elements arranged in multiple rows and columns. Each pixel circuit includes a pixel driver configured to receive a data signal and drive the light-emitting element based on the data signal. A first power signal is coupled to an anode of the light-emitting element via the pixel driver, and a second power signal is coupled to a cathode of the light-emitting element. In some embodiments, the second power signal is configured to vary based on the data signal. In some embodiments, during a first cycle of the data signal, the value of the second power signal is lower than the value of the first power signal, and during a second cycle of the data signal, the value of the second power signal is higher than the value of the first power signal.

[0006] In yet another example, a circuit for driving a light-emitting element includes an AC power supply circuit having a first power supply circuit configured to output a first power supply signal and a second power supply circuit configured to output a second power supply signal. In some embodiments, the first power supply signal ranges between a first high power supply value and a first low power supply value, wherein the first high power supply value is greater than the first low power supply value; the second power supply signal ranges between a second high power supply value and a second low power supply value, wherein the second high power supply value is greater than the second low power supply value; and a power supply swing value of the AC power supply circuit is equal to the difference between the first high power supply value and the second low power supply value. This difference is equal to or greater than the driving voltage across the light-emitting element. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the presented disclosure and, together with the description, further serve to explain the principles of the disclosure and enable one skilled in the relevant art to make and use the disclosure.

[0008] Figure 1 is a block diagram illustrating a device including a display and control logic according to an embodiment.

[0009] Figure 2 FIG. 1 is a diagram showing a drive circuit according to an embodiment of the present invention. Figure 1 Block diagram of the display shown in .

[0010] Figures 3A-3C 2 and 3 are circuit diagrams of exemplary pixel circuits for driving a light emitting element according to embodiments.

[0011] Figures 4A-4C Each is a circuit diagram of an exemplary circuit for driving a plurality of light emitting elements according to an embodiment.

[0012] Figure 5A is a circuit diagram of an exemplary circuit for generating a first AC power signal according to an embodiment.

[0013] Figure 5B is a circuit diagram of an exemplary circuit for generating a second AC power signal according to an embodiment.

[0014] Figure 6A is a circuit diagram of a first switching circuit according to an embodiment.

[0015] Figure 6B According to the embodiment Figure 6A Timing diagram of the circuit shown in .

[0016] Figure 7A is a circuit diagram of a second switching circuit according to an embodiment.

[0017] Figure 7B According to the embodiment Figure 7ATiming diagram of the circuit shown in .

[0018] The present disclosure is described with reference to the accompanying drawings. In the drawings, generally, like reference numerals indicate identical or functionally similar elements. Also, generally, the leftmost digit of a reference number identifies the drawing in which the reference number first appears. DETAILED DESCRIPTION

[0019] Although specific configurations and arrangements are discussed, it should be understood that this is for illustrative purposes only. It is contemplated that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It is also contemplated that the present disclosure may be used in a variety of other applications.

[0020] It should be noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," etc., indicate that the described embodiments may include a particular feature, structure, or characteristic, but not every embodiment may necessarily include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is contemplated that such feature, structure, or characteristic may also be used in conjunction with other embodiments, whether or not explicitly described.

[0021] In general, terms can be understood based, at least in part, on their use in context. For example, the term "one or more," as used herein, can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" can be understood to convey either singular usage or plural usage, depending, at least in part, on the context. Furthermore, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but rather can allow for the presence of additional factors that are not necessarily explicitly described, again depending, at least in part, on the context.

[0022] As will be disclosed in detail below, among other novel features, the pixel circuit of the light-emitting element of the present invention can increase the voltage at the cathode of the light-emitting element, causing the light-emitting element to reverse bias when it is turned off, thereby changing the electric field in the light-emitting element. This operation can reduce or mitigate degradation of the light-emitting element and improve the contrast of the display. In some embodiments, when the light-emitting element is turned off, the voltage at the anode of the light-emitting diode is reduced, allowing for more flexible determination of the reverse bias applied to the light-emitting diode.

[0023] In the present disclosure, the first and second power supply signals applied to the anode and cathode of the light-emitting diode can be applied to at least one row of light-emitting diodes. In some embodiments, each row of light-emitting elements is applied with a corresponding first / second power supply signal. In some embodiments, the light-emitting elements in the entire display are applied with the same first / second power supply signal. The first / second power supply signals can be generated by respective power supply circuits, each of which has a voltage swing range, allowing the light-emitting elements to be reverse biased with greater flexibility. At the same time, the power supply circuit couples the capacitor to filter out noise only when the light-emitting element is forward biased to emit light, thereby reducing energy consumption. Compared with traditional pixel circuits, in which only a power supply signal is applied to control the "on" and "off" states of the light-emitting element (for example, not reverse biased), the disclosed pixel circuit can use a power supply signal or an external signal to reverse bias the light-emitting element, preventing / reducing the light emission caused by the anode floating and leakage current of the light-emitting element. The degradation of the light-emitting element can be reduced or prevented.

[0024] Figure 1 An apparatus 100 is shown that includes a display 102 and control logic 104. Apparatus 100 can be any suitable device, such as a virtual reality (VR), augmented reality (AR), or mixed reality (MR) device (e.g., a VR headset, etc.), a handheld device (e.g., a smartphone, tablet, etc.), a wearable device (e.g., glasses, a watch, etc.), a car console, a game console, a television, a laptop, a desktop computer, a netbook computer, a media center, a set-top box, a global positioning system (GPS), an electronic billboard, an electronic sign, a printer, or any other suitable device. In this embodiment, display 102 is operably coupled to control logic 104 and is part of apparatus 100, such as, but not limited to, an HMD, a handheld device screen, a computer monitor, a television screen, a dashboard, an electronic billboard, or an electronic sign. Display 102 can be an OLED display, a micro-LED display, a liquid crystal display (LCD), an electronic ink display, an electroluminescent display (ELD), a billboard display with LED or incandescent lamps, or any other suitable type of display.

[0025] The control logic 104 can be any suitable hardware, software, firmware, or combination thereof that is configured to receive display data 106 (e.g., pixel data) and generate control signals 108 for driving sub-pixels on the display 102. The control signals 108 are used to control the writing of the display data 106 to the sub-pixels and direct the operation of the display 102. For example, a sub-pixel rendering (SPR) algorithm for various sub-pixel arrangements can be part of the control logic 104 or implemented by the control logic 104. The control logic 104 can be implemented as a stand-alone integrated circuit (IC) chip, such as an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The device 100 can also include any other suitable components, such as, but not limited to, a tracking device 110 (e.g., an inertial sensor, a camera, an eye tracker, a GPS receiver, or any other suitable device for tracking eye movements, facial expressions, head movements, body movements, and gestures), an input device 112 (e.g., a mouse, a keyboard, a remote control, a handwriting device, a microphone, a scanner, etc.), and a speaker (not shown).

[0026] In this embodiment, the apparatus 100 may be a handheld or VR / AR / MR device, such as a smartphone, a tablet, or a VR headset. The apparatus 100 may also include a processor 114 and a memory 116. The processor 114 may be, for example, a graphics processor (e.g., a graphics processing unit (GPU)), an application processor (AP), a general-purpose processor (e.g., an APU, accelerated processing unit; a GPGPU, general-purpose computing on a GPU), or any other suitable processor. The memory 116 may be, for example, a discrete frame buffer or a unified memory. The processor 114 is configured to generate display data 106 in a display frame and may temporarily store the display data 106 in the memory 116 before sending it to the control logic 104. The processor 114 may also generate other data, such as, but not limited to, control instructions 118 or test signals, and provide them to the control logic 104 directly or through the memory 116. The control logic 104 then receives the display data 106 from the memory 116 or directly from the processor 114.

[0027] Figure 2 FIG. 1 is a diagram showing a drive circuit according to an embodiment of the present invention. Figure 1 . The display 102 in this embodiment includes a display panel having an active area 200, which includes a plurality of sub-pixels. The display panel may also include on-board driver circuits, such as a gate driver circuit 202 and a source driver circuit 204. It should be understood that in some embodiments, the gate driver circuit 202 and the source driver circuit 204 may not be on-panel driver circuits, i.e., not part of the display panel, but may be operatively coupled to the display panel.

[0028] Each subpixel can be any unit that constitutes a pixel, i.e., a subdivision of a pixel. For example, a subpixel can be a monochrome display element that can be addressed individually. In some embodiments where display 102 is a light-emitting element display (e.g., an OLED display or a micro-LED display), each subpixel can include a light-emitting element (e.g., an OLED or micro-LED) and pixel circuitry for driving the light-emitting element. The multiple subpixels (and their light-emitting elements) can be arranged in an array having multiple rows and columns according to any suitable subpixel arrangement. Each light-emitting element can emit light of a predetermined brightness and color, such as, but not limited to, red, green, blue, yellow, cyan, magenta, or white. Each pixel circuit includes a thin-film transistor (TFT) and a capacitor and is configured to drive the corresponding subpixel by controlling the light emitted from each light-emitting element according to a control signal 108 from control logic 104. The pixel circuit can be a 2T1C configuration (i.e., including a switching transistor, a drive transistor, and a storage capacitor) or can include compensation circuitry with more transistors and / or capacitors to achieve brightness uniformity, such as in a 7T1C, 5T1C, 5T2C, or 6T1C configuration.

[0029] The gate drive circuit 202 in this embodiment is operably coupled to the active area 200 through a plurality of gate lines G1-Gm (also known as scan lines) and is configured to scan a plurality of sub-pixels. For example, the gate drive circuit 202 applies a plurality of scan signals generated based on the control signal 108 from the control logic 104 to the plurality of gate lines G1-Gm for scanning a plurality of sub-pixels in a gate scan sequence. The scan signal is applied to the gate of the switching transistor of each pixel circuit during the scan period, turning on the switching transistor so that the source drive circuit 204 can write the data signal of the corresponding sub-pixel. It should be understood that although Figure 2 One gate driving circuit 202 is shown in FIG. 4 , but in some embodiments, multiple gate driving circuits may work in conjunction with each other to scan sub-pixels.

[0030] The source driver circuit 204 in this embodiment is operably coupled to the active area 200 through a plurality of source lines S1-Sn (also known as data lines), and is configured to write the display data 106 to a plurality of sub-pixels in frames. For example, the source driver circuit 204 can apply a plurality of data signals to the plurality of source lines S1-Sn of the sub-pixels at the same time. That is, the source driver circuit 204 may include one or more shift registers, digital-to-analog converters (DACs), multiplexers (MUXs), and operational circuits for controlling the timing (i.e., during the scanning period of each frame) of applying a voltage to the source of the switching transistor of each pixel circuit and the magnitude of the applied voltage according to the grayscale of the display data 106. It should be understood that although Figure 2One source driver circuit 204 is shown in FIG. 2 , but in some embodiments, multiple source driver circuits may work in conjunction with each other to apply data signals to the source lines of the sub-pixels.

[0031] In addition, a light emitting driver circuit 206 may be included on the display panel. The light emitting driver circuit 206 is operatively coupled to the active region 200 and configured to cause each sub-pixel to emit light for a certain period in each frame by applying a plurality of light emitting signals to a plurality of emission lines E1-Ek. It should be understood that although Figure 2 One light emitting driving circuit 206 is shown in FIG. 2 , but in some embodiments, multiple light emitting driving circuits may work in conjunction with each other.

[0032] Figure 3A FIG3 is a circuit diagram of a pixel circuit 300 for driving a light-emitting element D in an OLED array on display 102 according to an embodiment. For ease of illustration, light-emitting element D is located in row N and column M of the array. Data signal DATA[M] and scan signal SCAN[N] may be used to control the light emission of light-emitting element D during a frame. For example, in each frame, when pixel circuit 300 receives scan signal SCAN[N], it may select the OLED in row N, and pixel circuit 300 may receive data signal DATA[M] to control the light emission of light-emitting element D. Light-emitting element D may be an OLED or micro-OLED driven by pixel circuit 300. Pixel circuit 300 may include a pixel driver 302 configured to receive data signal DATA[M] and drive light-emitting element D based on data signal DATA[M]. In some embodiments, the "ON" and "OFF" states of light-emitting element D are determined based on data signal DATA[M]. For ease of illustration, during the first cycle of data signal DATA[M], light-emitting element D is turned on; during the second cycle of data signal DATA[M], light-emitting element D is turned off. In the first cycle, the light-emitting element D can be turned on (e.g., forward biased) to emit light, and the brightness range can be from a bright state to a dark state, depending on the data signal DATA[M]. In the second cycle, the light-emitting element D can be turned off and / or reverse biased, emitting little or no light. In the present disclosure, the data signal DATA[M] of the first and second cycles is used to distinguish the "ON" (e.g., forward biased) and "OFF" (e.g., closed and / or reverse biased) states of the light-emitting element. The specific value of the data signal DATA[M] should not be limited. In the present disclosure, "first cycle" can be interchanged with "first cycle of the data signal", and "second cycle" can be interchanged with "second cycle of the data signal".

[0033] like Figure 3AAs shown, the pixel driver 302 may include a driver transistor N1 coupled to a first power signal V1 and a light-emitting element D. In some embodiments, the driver transistor N1 is an n-type transistor, with its drain coupled to the first power signal V1 and its source coupled to the light-emitting element D. The pixel driver 302 may also include a capacitor C (e.g., a storage capacitor) having one end coupled to the gate of the driver transistor N1 and the other end coupled to GND. The pixel driver 302 may also include a switching transistor T coupled to the data signal DATA[M], the scan signal SCAN[N], the capacitor C, and the driver transistor N1. When the scan signal SCAN[N] selects a row of light-emitting elements D, the switching transistor T may allow the data signal DATA[M] to be transmitted to the driver transistor N1, so that the driver transistor N1 may be coupled to the anode of the light-emitting element D. In some embodiments, the switching transistor T is an n-type transistor, with its drain coupled to the data signal DATA[M], its source coupled to the capacitor C and the gate of the driver transistor N1, and its gate coupled to the scan signal SCAN[N].

[0034] The anode of light-emitting element D may be coupled to the source terminal of driver transistor N1, which is coupled to a first power supply signal V1. V1 may then be coupled to the anode of light-emitting element D via driver transistor N1. The cathode of light-emitting element D may be coupled to a second power supply signal V2. In some embodiments, when light-emitting element D is turned on (e.g., emits light) based on data signal DATA[M] during a first cycle, the value of first power supply signal V1 is higher than the value of second power supply signal V2. In some embodiments, the value of first power supply signal V1 is equal to Vdd (e.g., a positive power supply voltage) and the value of second power supply signal V2 is equal to Vss (e.g., a negative power supply voltage). That is, when light-emitting element D is turned on, the voltage VDN1 at the anode of light-emitting element D (e.g., at node ND1) may be higher than the voltage VDN2 at the cathode of light-emitting element D (e.g., at node ND2). Light-emitting element D may be forward biased, and a drive current may flow into light-emitting element D via driver transistor N1. In some embodiments, the value of first power supply signal V1 is a constant DC value, such as Vdd, during the first cycle. In some embodiments, first power supply signal V1 is an AC signal.

[0035] Pixel circuit 300 can include a third power signal V3 applied to the anode of light-emitting element D during the second period, i.e., when light-emitting element D is off. That is, during the second period, voltage VDN1 (e.g., at the anode of light-emitting element D) can be determined by the third power signal V3 rather than the first power signal V1. Simultaneously, during the second period, second power signal V2 can vary, e.g., increase, such that cathode voltage VDN2 of light-emitting element D can be higher than voltage VDN1. Thus, light-emitting element D can be reverse biased during the second period. In some embodiments, third power signal V3 is coupled to the source terminal of drive transistor N1 and the anode of light-emitting element D. The value of third power signal V3 can be lower than the value of first power signal V1 (e.g., Vdd).

[0036] In some embodiments, the range of the second power supply signal V2 is between a minimum second power supply value and a maximum second power supply value. The minimum second power supply value may be equal to Vss. Depending on the value of the third power supply signal V3, the maximum second power supply value may be positive, negative, or zero. In some embodiments, the third power supply signal V3 is a constant value, which may be positive, negative, or zero. In some embodiments, the reverse voltage applied across the light-emitting element D (i.e., (VDN2-VDN1)) is equal to (V3-V2). In some embodiments, the maximum second power supply value is greater than the value of the third power supply signal V3. In some embodiments, the value of the second power supply signal V2 is positive and the value of the third power supply signal V3 is negative (e.g., Vss).

[0037] In some embodiments, the connection / coupling between the third power supply signal V3 and the pixel driver 302 (or node ND1) is controlled by a switch element N2. When the light-emitting element D is off (e.g., during the second cycle), the switch element N2 controls the transmission of the third power supply signal V3 to the light-emitting element D. In some embodiments, the switch element N2 is an n-type transistor, with its drain coupled to the third power supply signal V3 and its source coupled to the pixel driver 302 (or node ND1). A control signal REV may be applied to the gate of the switch element N2. This control signal turns on the switch element N2 when the light-emitting element D is off (e.g., during the second cycle). During the first cycle, the control signal REV may be applied to turn off the switch element N2, so that the third power supply signal V3 does not bias (or decouple) the pixel driver 302. The anode voltage VND1 of the light-emitting element D may be (or be determined by) the value of the first power supply signal V1 (e.g., Vdd), and the cathode voltage VND2 of the light-emitting element D may be the value of the second power supply signal V2 (e.g., Vss). During the second cycle, a control signal REV may be applied to turn on the switch element N2, so that the third power signal V3 is coupled to the pixel driver 302. The anode voltage VND1 of the light-emitting element D may be (or be determined by) the value of the third power signal V3 (e.g., lower than Vdd), and the cathode voltage VND2 of the light-emitting element D may be the value of the second power signal V2 (e.g., higher than the value of the third power signal V3). The control signal REV may be generated using a separate circuit different from the pixel circuit 300. In some embodiments, the control signal REV is generated based on the data signal DATA[M] and / or the scan signal SCAN[N].

[0038] In some embodiments, the third power signal V3 may further vary between a maximum third power value and a minimum third power value. In some embodiments, the maximum third power value is lower than the maximum second power value. In various embodiments, the values ​​of the second and third power signals V2 and V3 may be flexibly determined based on components of the circuit, such as the light-emitting element D and the power supply circuit that generates the power signal, and should not be limited by the embodiments of the present invention.

[0039] Figure 3B FIG. 3 is a circuit diagram of another pixel circuit 310 for driving a light emitting element D in an OLED array on a display 102 according to an embodiment. Different from the pixel circuit 300, in the pixel circuit 310, the switch element N2 is controlled by the second power signal V2 instead of the control signal REV. Figure 3BAs shown, the gate terminal of switching element N2 is coupled to the cathode of light-emitting element D (or node ND2). During a first cycle, a first power signal V1 can be applied to the anode of light-emitting element D via driver transistor N1, and a second power signal V2 can be applied to the cathode of light-emitting element D. The value of the first power signal V1 can be higher than the value of the second power signal V2. As previously described, during the first cycle, VND1 can be higher than VND2, and light-emitting element D can be driven to emit light. During the first cycle, the value of the second power signal V2 can be sufficiently low (e.g., a negative value such as Vss), and switching element N2 can be turned off to prevent the third power signal V3 from applying a bias to pixel driver 302. During a second cycle, the value of the second power signal V2 can increase to a value high enough to turn on switching element N2. Therefore, the third power signal V3 can be applied to the anode of light-emitting element D (or node ND1) via switching element N2, and the first power signal V1 can no longer apply a bias to light-emitting element D. Therefore, as previously described, light-emitting element D can be reverse biased during the second cycle. The ranges / values ​​of the second and third power signals V2 and V3, as well as the reverse voltage drop across the light-emitting element D in pixel circuit 310, can be the same as those in pixel circuit 300 and are not further described herein. In some embodiments, by controlling the switch element N2 using the second power signal V2, no additional control signal is required to control the switch element N2. For ease of description, the control signal REV can be referred to as an external control signal.

[0040] In some embodiments, in pixel circuits 300 and 310, the value of the first power signal V1 may be reduced in the second cycle, for example, when the third power signal V3 is applied to the anode (or node ND1) of the light-emitting element D, to reduce or prevent electrical coupling, such as current, between the first and third power signals V1 and V3. In some embodiments, in the second cycle of the data signal DATA[M], the first power signal V1 may be reduced to have the same value as the third power signal V3.

[0041] Figure 3CFIG3 is a circuit diagram of another pixel circuit 320 for driving a light-emitting element D in an OLED array on display 102 according to an embodiment. Unlike pixel circuits 300 and 310, in pixel circuit 320, the value of the first power signal V1 can vary, for example, decrease, based on whether the data signal DATA[M] is reverse biased. During the second cycle, the light-emitting element D is reverse biased by the first and second power signals V1 and V2. In this embodiment, the light-emitting element D is reverse biased by varying the values ​​(and / or polarities) of the first and second power signals V1 and V2. Similar to pixel circuits 300 and 310, during the first cycle, the value of the first power signal V1 (e.g., Vdd) can be higher than the value of the second power signal V2 (e.g., Vss), and the light-emitting element D can be driven to emit light. During the second cycle, based on the data signal DATA[M], the value of the second power signal V2 can increase, and the value of the first power signal V1 can decrease. During the second cycle, the value of the second power signal V2 can be higher than the value of the first power signal V1. Consequently, VND2 can be higher than VND1, and the light-emitting element D can be reverse biased. In some embodiments, the range of the first power signal V1 is between the minimum first power value and Vdd, wherein the minimum first power value is lower than Vdd. The minimum first power value can be a positive value, a negative value (e.g., Vss) or zero. In some embodiments, the range of the second power signal V2 is between Vss and the maximum second power value, similar to pixel circuits 300 and 310. The maximum second power value can be a positive value (e.g., Vdd), a negative value or zero. In various embodiments, the reverse voltage drop across the light-emitting element D in the second cycle is nominally equal to (V1-V2) in the second cycle.

[0042] The display 102 may include a plurality of light emitting elements D arranged in an array of multiple rows and columns. The first and second power supply signals V1 and V2 may be applied to the light emitting elements D in different manners. Figures 4A-4C Different circuits 400, 410, and 420 are illustrated, wherein first and second power supply signals V1 and V2 are applied to light-emitting elements D in display 102. Each of circuits 400-420 can include a plurality of light-emitting elements D arranged in an array of multiple rows and columns. Each light-emitting element can be part of a pixel circuit 402. Multiple pixel circuits 402 can be arranged in multiple rows and columns. In some embodiments, pixel circuit 402 can be similar to any of pixel circuits 300-320, and therefore a detailed description of pixel circuit 402 will not be repeated here. In some embodiments, circuits 400-420 can be used to apply first and second power supply signals V1 and V2 to pixel circuits 300-320.

[0043] like Figures 4A-4CAs shown. Each scan line (e.g., SCAN[N-1], SCAN[N], SCAN[N+1], ...) can be coupled to a plurality of pixel circuits 402 along the row direction. And each data line (e.g., DATA[M-1], DATA[M], DATA[M+1], DATA[M+2], ...) can be coupled to a plurality of pixel circuits 402 along the column direction. A first power supply signal V1 and a second power supply signal V2 can be applied to the pixel circuits 402 in at least one row, respectively. In some embodiments, as shown in circuit 400, the first power supply signal V1 and the second power supply signal V2 can each be applied to each pixel circuit 402 in the display 102 (i.e., "V1 voltage source" and "V2 voltage source") through a corresponding voltage source (i.e., arranged in multiple rows). That is, the same first power supply signal V1 is applied to each pixel circuit 402 in the display 102, and the same second power supply signal V2 is applied to each pixel circuit 402 in the display 102. In other words, the control and / or operation of the first power supply signal V1 may be the same for all pixel circuits 402, and the control and / or operation of the second power supply signal V2 may be the same for all pixel circuits 402. In some embodiments, in the circuit 400, the pixel circuits 402 may include pixel circuits 300 and 310.

[0044] In some embodiments, as shown in circuit 410, the same first power signal V1 is applied to each pixel circuit 402, and a corresponding second power signal V2 (e.g., via a V2[N-1] voltage source, a V2[N] voltage source, a V2[N+1] voltage source, ...) is applied to the pixel circuit 402 of each row. That is, the number of V2 voltage sources (i.e., the number of second power signals V2) can be the same as the number of scan lines. Unlike circuit 400, in circuit 410, the second power signal V2 applied to each row can be operated and / or controlled separately, so that the light-emitting elements D in different rows can be reverse biased separately, for example, at different times. The control of pixel circuit 402 can be more flexible. In some embodiments, in circuit 410, pixel circuit 402 can include pixel circuits 300 and 310.

[0045] In some embodiments, as shown in circuit 420, unlike circuit 410, a respective first power supply signal V1 is applied to the pixel circuit 402 coupled to each row (e.g., via a V2[N-1] voltage source, a V2[N] voltage source, a V2[N+1] voltage source, etc.). That is, the number of V1 voltage sources (i.e., the number of first power supply signals V1) can be the same as the number of scan lines. Unlike circuits 400 and 410, in circuit 420, the first power supply signal V1 applied to each row can be operated and / or controlled separately, such that the light-emitting elements D in different rows can be reverse biased separately, e.g., at different times. This allows for more flexible control of pixel circuit 402. In some embodiments, in circuit 420, pixel circuit 402 can include pixel circuit 320.

[0046] The first and second power supply signals V1 and V2 may each be generated by a suitable AC power supply circuit and applied to corresponding pixel circuits. Figure 5A An exemplary first power supply circuit 500 is shown for generating a first power supply signal V1 (e.g., a first AC power supply signal) ranging from a minimum first power supply value V1_L to a maximum first power supply value V1_H (e.g., Vdd). The power supply circuit 500 can be used to generate the first power supply signal V1 for the pixel circuit 320. Figure 5B An exemplary power supply circuit 510 is illustrated for generating a second power signal V2 (e.g., a second AC power signal) ranging from a minimum second power value V2_L (e.g., Vss) to a maximum first power value. The power supply circuit 510 can be used to generate the second power signal V2 for the pixel circuits 300-320. Each of the power supply circuits 500 and 510 may include a power supply circuit (i.e., 502 and 512) and a switching circuit (i.e., 504 and 514) coupled to the corresponding power supply circuit. Each power supply circuit 502 and 512 can have a voltage swing between a respective maximum power value and a respective minimum power value. The structure and working mechanism of the power supply circuits 502 and 512 can be found in Chinese Patent CN101101736A and will not be described in detail here.

[0047] like Figure 5AAs shown, the first power supply circuit 500 may include a first power supply circuit 502 in contact with a first switching circuit 504. The first power supply circuit 502 can provide AC power ranging between a maximum first power supply value V1_H (e.g., Vdd) and a minimum first power supply value V1_L (e.g., GND). The maximum and minimum first power supply values ​​V1_H and V1_L can be provided by respective power supplies. Each power supply can be coupled to multiple components such as transistors and / or capacitors (e.g., PH and NG, and NL and PG) and further coupled to GND. The output ("OUTPUT") of the first power supply circuit 500 can be coupled to V1_H and V1_L via any component (e.g., PH and NL) to output a first power supply signal V1 having a voltage swing between V1_H and V1_L. In some embodiments, V1_H is equal to Vdd (e.g., a positive voltage), and V1_L is equal to GND (e.g., 0V). In some embodiments, Vdd ≥ V1_H > GND, where Vdd is a positive voltage.

[0048] The first switching circuit 504 can be coupled (e.g., electrically coupled to or electrically coupled to) the first power circuit 502 or decoupled (e.g., having little or no electrical coupling) from the first power circuit 502, depending on the operation. During a first period, the first switching circuit 504 can be coupled to the first power circuit 502 and filter out noise signals when the first power circuit 500 outputs an AC power signal (e.g., first power signal V1) for driving each light-emitting element. During a second period, when the first power circuit 500 is used to reverse bias the corresponding light-emitting element, the first switching circuit 504 can be decoupled from the first power circuit 502. No noise filtering is performed during the second period. That is, in some embodiments, the first power circuit 500 only filters noise signals when the light-emitting element is turned on. This can save energy compared to conventional AC power circuits that filter noise signals when the light-emitting element is turned on and off. For example, when the first power supply circuit 500 outputs V1_H, the corresponding light-emitting element is forward biased and / or turned on, and the first switch circuit 504 is coupled to the first power supply circuit 502 to filter out noise signals; when the first power supply circuit 500 outputs V1_L, the corresponding light-emitting element is reverse biased and / or turned off, and the first switch circuit 504 is decoupled from the first power supply circuit 502.

[0049] like Figure 5AAs shown, the first switch circuit 504 may include a transistor PCAP1 coupled to the first power supply circuit 502, a switch SW1 coupled to the transistor PCAP1, a capacitor CAP1 coupled to the switch SW1 and GND, and a transistor NG_CAP coupled to the capacitor PCAP1, the switch SW1, and GND. In some embodiments, the transistor PCAP1 is a p-type transistor, whose source terminal is coupled to the first power supply circuit 502, the drain terminal is coupled to the switch SW1, and the gate terminal is coupled to the control signal (i.e., Figure 6A VPCAP1_CTRL in FIG1 controls the “ON” and “OFF” states of transistor PCAP1. Switch SW1 can be coupled to transistor PCAP1 and one end of capacitor CAP1. The other end of capacitor CAP1 can be coupled to GND. In some embodiments, transistor NG_CAP is an n-type transistor with a drain terminal coupled to the drain terminal of transistor PCAP1, a source terminal coupled to GND, and a gate terminal coupled to a control signal (i.e., VPCAP1_CTRL in FIG1 ) that controls the “ON” and “OFF” states of transistor NG_CAP. Figure 6A ) in VNGCAP_CTRL.

[0050] Figure 6A A detailed circuit diagram of the first switching circuit 504 according to an embodiment is illustrated. Figure 6B FIG shows a timing diagram of various voltages in the first switch circuit 504. Figure 5A 、 6A 6B show the operation of the first power supply circuit 500. Figure 6A As shown, switch SW1 may include a p-type transistor PSW and an n-type transistor NSW coupled together. In various embodiments, switch SW1 may include any suitable configuration and / or device, not limited by the embodiments of the present disclosure. In some embodiments, the drain terminal of transistor NSW is coupled to the source terminal of transistor PSW and the drain terminal of transistor PCAP1, and the source terminal of transistor NSW is coupled to the drain terminal of transistor PSW and capacitor CAP1. A control signal VNSW_CTRL may be applied to the gate terminal of transistor NSW, and a control signal VPSW_CTRL may be applied to the gate terminal of transistor PSW. In some embodiments, a control signal VPCAP1_CTRL may be applied to the gate terminal of transistor PCAP1, and a control signal VNG_CAP_CTRL may be applied to the gate terminal of transistor NG_CAP. The voltage on one side of switch SW1 (i.e., coupled to transistor PCAP1) is denoted by VCAP_SW, while the voltage on the other side of switch SW1 (i.e., coupled to capacitor CAP1) is denoted by VCAP.

[0051] like Figure 6A and 6BAs shown, in the first period T1, the control signal VNG_CAP_CTRL can be configured to turn off the transistor NG_CAP, the control signal VPCAP1_CTRL can be configured to turn on the transistor PCAP1, and the control signals VNSW_CTRL and VPSW_CTRL can be configured to turn on the transistors NSW and PSW, respectively. Therefore, the switch SW1 is turned on, and the voltages VCAP_SW and VCAP can both be equal to the output V1 of the first power supply circuit 500 (e.g., the maximum first power supply value V1_H). Return to reference Figure 5A During a first cycle T1, when switch SW1 and transistor PCAP1 are on and transistor NG_CAP is off, capacitor CAP1 is coupled to first power circuit 502. In some embodiments, capacitor CAP1 is used for noise filtering, e.g., only during the first cycle T1. In some embodiments, current in first power circuit 500 flows through path 1, which includes a power supply providing a maximum first power supply value V1_H and capacitor CAP1. Output V1 of first power circuit 500 can be equal to V1_H.

[0052] like Figure 6A and 6B As shown, in the second period T2, the control signal VNG_CAP_CTRL can be configured to turn on the transistor NG_CAP, the control signal VPCAP1_CTRL can be configured to turn off the transistor PCAP1, and the control signals VNSW_CTRL and VPSW_CTRL can be configured to turn off the transistors NSW and PSW, respectively. Therefore, the switch SW1 is closed, the voltage VCAP_SW can be equal to GND, and the voltage VCAP can be equal to the maximum first power supply value V1_H of the first power supply circuit 500. Return to reference Figure 5B In the second period T2, when the switch SW1 and the transistor PCAP1 are turned off and the transistor NG_CAP is turned on, the capacitor CAP1 is decoupled from the first power supply circuit 502. In some embodiments, the current in the first power supply circuit 500 flows through path 2, which includes a power supply that provides the minimum first power supply value V1_L. The output V1 of the first power supply circuit 500 can be equal to V1_L.

[0053] Figure 5BA second power supply circuit 510 is shown. Similar to the first power supply circuit 500, the second power supply circuit 510 may include a second power supply circuit 512 coupled to a second switching circuit 514. The second power supply circuit 512 may provide AC power ranging between a maximum second power supply value V2_H (e.g., GND) and a minimum first power supply value V2_L (e.g., Vss). The maximum and minimum first power supply values ​​V1_H and V1_L may be provided by respective power supplies. Each power supply is coupled to a plurality of components such as transistors and / or capacitors (e.g., PH and NG, and NL and PG) and further coupled to GND. The output ("OUTPUT") of the second power supply circuit 510 may be coupled to V2_H and V2_L via any of the components (e.g., PH and NL) to output a second power supply signal V2 having a voltage swing between V2_H and V2_L. In some embodiments, V2_H is equal to GND (e.g., 0V), and V1_L is equal to Vss (e.g., a negative voltage). In some embodiments, GND>V2_L≥Vss, where Vss is a negative voltage.

[0054] Depending on the operation, the second switching circuit 514 can be coupled to the second power supply circuit 512 or can be decoupled from the second power supply circuit 512. In a first cycle, the second switching circuit 514 can be coupled to the second power supply circuit 512 and can filter out noise signals when the second power supply circuit 510 outputs an AC power signal (e.g., second power signal V2) for driving each light-emitting element. In a second cycle, when the second power supply circuit 510 is used to reverse bias the corresponding light-emitting element, the second switching circuit 514 can be decoupled from the second power supply circuit 512. No noise filtering is performed in the second cycle. That is, in some embodiments, the second power supply circuit 510 only filters noise signals when the light-emitting element is turned on. Similar to the first power supply circuit 500, energy can be saved by using the second power supply circuit 510. For example, when the second power supply circuit 510 outputs V2_L, the corresponding light-emitting element is forward biased and / or turned on, and the second switch circuit 514 is coupled to the second power supply circuit 512 to filter out noise signals; when the second power supply circuit 510 outputs V2_H, the corresponding light-emitting element is reverse biased and / or turned off, and the second switch circuit 514 is decoupled from the second power supply circuit 512.

[0055] like Figure 5B As shown, the second switch circuit 514 may include a transistor NCAP coupled to the second power supply circuit 512, a switch SW2 coupled to the transistor NCAP, a capacitor CAP2 coupled to the switch SW2 and GND, and a transistor PG_CAP coupled to the capacitor NCAP, the switch SW2, and GND. In some embodiments, the transistor NCAP is an n-type transistor, the drain terminal of which is coupled to the second power supply circuit 512. The source terminal is coupled to the switch SW2, and the gate terminal is coupled to the control signal (i.e., Figure 6B The switch SW2 can be coupled to the transistor NCAP and one end of the capacitor CAP2. The other end of the capacitor CAP2 can be coupled to GND. In some embodiments, the transistor PG_CAP is a p-type transistor with a source terminal coupled to the source terminal of the transistor NCAP, a drain terminal coupled to GND, and a gate terminal coupled to a control signal (i.e., Figure 6B VPGCAP_CTRL in the PG_CAP pin controls the “ON” and “OFF” states of transistor PG_CAP.

[0056] Figure 7A FIG. 5 illustrates a detailed circuit diagram of the second switching circuit 514 according to an embodiment. Figure 7B FIG2 shows a timing diagram of various voltages in the second switching circuit 514. Figure 5B 、 7A 7B show the operation of the second power supply circuit 510. Figure 7A As shown, switch SW2 can include a p-type transistor PSW and an n-type transistor NSW coupled together, similar to first switch circuit 504. In some embodiments, the drain terminal of transistor NSW is coupled to the source terminal of transistor PSW and the source terminal of transistor NCAP, and the source terminal of transistor NSW is coupled to the drain terminal of transistor PSW and capacitor CAP2. In some embodiments, control signal VNCAP_CTRL can be applied to the gate terminal of transistor NCAP, and control signal VPG_CAP_CTRL can be applied to the gate terminal of transistor PG_CAP. The voltage on one side of switch SW2 (i.e., coupled to transistor NCAP) is denoted by VCAP_SW, and the voltage on the other side of switch SW2 (i.e., coupled to capacitor CAP2) is denoted by VCAP.

[0057] like Figure 7A and Figure 7B As shown, in the first period T1, the control signal VPG_CAP_CTRL can be configured to turn off the transistor PG_CAP, the control signal VNCAP_CTRL can be configured to turn on the transistor NCAP, and the control signals VNSW_CTRL and VPSW_CTRL can be configured to turn on the transistors NSW and PSW, respectively. Therefore, the switch SW2 is turned on, and the voltages VCAP_SW and VCAP can both be equal to the output V2 of the second power supply circuit 510 (e.g., the minimum second power supply value V2_L). Return to reference Figure 5BDuring the first cycle T1, when switch SW2 and transistor NCAP are on and transistor PG_CAP is off, capacitor CAP2 is coupled to second power supply circuit 512. In some embodiments, capacitor CAP2 is used for noise filtering, for example, only during the first cycle T1. In some embodiments, current in second power supply circuit 510 flows through path 1, which includes a power supply providing a minimum second power supply value V2_L and capacitor CAP2. Output V2 of second power supply circuit 510 can be equal to V2_L.

[0058] like Figure 7A and 7B As shown, in the second period T2, the control signal VPG_CAP_CTRL can be configured to turn on the transistor PG_CAP, the control signal VNCAP_CTRL can be configured to turn off the transistor NCAP, and the control signals VNSW_CTRL and VPSW_CTRL can be configured to turn off the transistors NSW and PSW, respectively. Therefore, the switch SW2 is closed, the voltage VCAP_SW can be equal to GND, and the voltage VCAP can be equal to the minimum second power value V2_L of the second power circuit 510. Return to reference Figure 7B In the second period T2, when the switch SW2 and the transistor NCAP are turned off and the transistor PG_CAP is turned on, the capacitor CAP2 is decoupled from the second power supply circuit 512. In some embodiments, the current in the second power supply circuit 510 flows through path 2, which includes a power supply that provides the maximum second power supply value V2_H. The output V2 of the second power supply circuit 510 can be equal to V2_H.

[0059] In some embodiments, a first power supply circuit 500 is used to provide a first power supply signal V1 ranging between a maximum first power supply value V1_H (e.g., Vdd) and a minimum first power supply value V1_L (e.g., GND) to circuit 420. In some embodiments, a second power supply circuit 510 is used to provide a second power supply signal V2 ranging between a maximum second power supply value V2_H (e.g., GND) and a minimum second power supply value V2_L (e.g., Vss) to circuits 400, 410, and 420.

[0060] In some embodiments, for circuits 400 and 410, a first power signal V1 is provided during a first cycle (T1) and a third power signal V3 is provided during a second cycle (T2). In some embodiments, both the first and third power signals V1 and V3 are provided by suitable power supply circuits. In some embodiments, the value of the first power signal V1 is Vdd, while the value of the third power signal V3 is lower than Vdd. The second power supply circuit 510 can provide a second power signal V2 during the first and second cycles, wherein in the first cycle, the value of the second power signal V2 is lower than the value of the first power signal V1, and in the second cycle, the value of the second power signal V2 is higher than the value of the third power signal V3. In some embodiments, the second power supply circuit 510 outputs Vss during the first cycle and outputs a positive voltage, such as Vdd, during the second cycle.

[0061] In some embodiments, for circuit 420, first and second power supply signals V1 and V2 are provided in first and second cycles (T1 and T2). In some embodiments, the first power supply signal V1 is provided by the first power supply circuit 500, and the second power supply signal V2 is provided by the second power supply circuit 510. Specifically, in the first cycle, the first power supply circuit 500 outputs a positive voltage as the first power supply signal V1, and the second power supply circuit 510 outputs a negative voltage or zero as the second power supply signal V2. In the second cycle, the first power supply circuit 500 outputs a negative voltage or zero as the first power supply signal V1, and the second power supply circuit 510 outputs a positive voltage as the second power supply signal V2. In some embodiments, the first power supply circuit 500 outputs Vdd in the first cycle and Vss in the second cycle, and the second power supply circuit 510 outputs Vss in the first cycle and Vdd in the second cycle.

[0062] For circuit 420, in the first cycle T1, the first and second power supply circuits 500 and 510 can output a sufficiently high driving voltage at both ends of the light-emitting element together. In some embodiments, the maximum value of the driving voltage can be equal to (V1_H-V2_L). For example, V1_H can be equal to 5V, V2_L can be equal to (-5V), and the maximum driving voltage can be equal to 10V. That is, the first and second power supply circuits 500 and 510 can be combined to drive a light-emitting element that requires a driving voltage higher than the individual driving voltage provided by each of the first and second power supply circuits 500 and 510. In some embodiments, in the second cycle, the first and second power supply circuits 500 and 510 can be combined to determine the reverse voltage drop across the light-emitting element. Because each of the first and second power supply circuits 500 and 510 has its own voltage swing range, the determination of the reverse voltage drop can be easier and more flexible.

[0063] It should be understood that the Detailed Description section, and not the Summary and Abstract sections, is intended to be used to interpret the claims. The Summary and Abstract sections may set forth one or more, but not all, exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure or the appended claims in any way.

[0064] Although the present disclosure has been described herein with reference to exemplary embodiments of exemplary fields and applications, it should be understood that the present disclosure is not limited thereto. Other embodiments and modifications thereof are possible and within the scope and spirit of the present disclosure. For example, but not limiting the generality of this paragraph, the embodiments are not limited to the software, hardware, firmware, and / or entities shown in the figures and / or described herein. Furthermore, the embodiments (whether or not explicitly described herein) have significant utility for fields and applications beyond the examples described herein.

[0065] The embodiments have been described with the aid of functional building blocks that illustrate the implementation of specific functions and relationships thereof. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries may be defined so long as the specified functions and relationships (or their equivalents) are appropriately performed. Furthermore, alternative embodiments may implement functional blocks, steps, operations, methods, etc., in an order different from that described herein.

[0066] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A pixel circuit comprising: a pixel driver configured to receive a data signal and drive a light-emitting element based on the data signal; a first power supply signal coupled to the anode of the light-emitting element through the pixel driver; a second power signal coupled to the cathode of the light emitting element; a third power supply signal coupled to the light-emitting element, wherein the value of the third power supply signal is lower than the positive power supply voltage; wherein: the second power supply signal is configured to change based on the data signal, and in a first cycle of the data signal, the value of the second power supply signal is lower than the value of the first power supply signal, and in a second cycle of the data signal, the value of the first power supply signal is equal to the value of the third power supply signal, and the value of the second power supply signal is higher than the value of the first power supply signal.

2. The pixel circuit according to claim 1, wherein: During a first cycle of the data signal, the light emitting element is configured to emit light; and during a second cycle of the data signal, the light emitting element is configured to be reverse biased.

3. The pixel circuit according to claim 2, wherein: In a second cycle of the data signal, the value of the second power signal is configured to increase to be higher than the value of the first power signal.

4. The pixel circuit according to claim 3, wherein: It also includes a third power supply signal coupled to the anode of the light-emitting element, the value of the third power supply signal being lower than the positive power supply voltage, wherein: in the first cycle of the data signal, the value of the first power supply signal is equal to Vdd, and the value of the second power supply signal is equal to Vss; and in the second cycle of the data signal, the value of the first power supply signal is equal to the value of the third power supply signal.

5. The pixel circuit according to claim 1, wherein: The second power supply signal varies between a negative power supply voltage and a maximum second power supply value; and the maximum second power supply value is greater than a value of the third power supply signal.

6. The pixel circuit according to claim 1 further includes a switching element coupled between the third power supply signal and the anode of the light-emitting element, and a control signal applied to the switching element, wherein in the second cycle of the data signal, the control signal is used to turn on the switching element so that the first power supply signal does not apply a bias to the light-emitting element, and the third power supply signal is coupled to the anode of the light-emitting element.

7. The pixel circuit according to claim 6, wherein: The switching element is a transistor, the drain of the transistor is coupled to the third power signal, the source of the transistor is coupled to the cathode of the light-emitting element, and the control signal is an external control signal applied to the gate of the light-emitting element.

8. The pixel circuit according to claim 6, wherein: The switching element is a transistor, the drain of the transistor is coupled to the third power signal, the source of the transistor is coupled to the cathode of the light-emitting element, and the control signal is the second power signal applied to the gate of the light-emitting element.

9. A pixel circuit according to claim 2, wherein the first power supply signal is configured to vary between a minimum first power supply value and Vdd based on the data signal; in a first cycle of the data signal, the value of the first power supply signal is equal to Vdd, and the value of the second power supply signal is equal to a negative power supply voltage; and in a second cycle of the data signal, the value of the first power supply signal is configured to decrease so that the value of the second power supply signal is higher than the value of the first power supply signal. 10 . The pixel circuit according to claim 9 , wherein in a second cycle of the data signal, the value of the first power signal is configured to decrease to Vss, and the value of the second power signal is configured to increase to the positive power voltage.

11. A circuit for driving a plurality of light-emitting elements, comprising: A plurality of pixel circuits are respectively configured to drive each of a plurality of light-emitting elements arranged in multiple rows and columns, and each pixel circuit includes: a pixel driver configured to receive a data signal and drive the light-emitting element based on the data signal; a first power signal coupled to the anode of the light-emitting element through the pixel driver; a second power signal coupled to the cathode of the light-emitting element; a third power signal coupled to the light-emitting element, the value of the third power signal being lower than a positive power supply voltage; wherein: the second power signal is configured to change based on the data signal, in a first cycle of the data signal, the value of the second power signal is lower than the value of the first power signal, in a second cycle of the data signal, the value of the first power signal is equal to the value of the third power signal, and the value of the second power signal is higher than the value of the first power signal. 12 . The circuit of claim 11 , wherein the second power supply signal is coupled to a cathode of each of the plurality of light emitting elements arranged in a same row.

13. The circuit of claim 11, wherein the first power supply signal is coupled to an anode of each of the plurality of light emitting elements arranged in a same row.

14. The circuit of claim 11 , wherein the second power signal is coupled to a cathode of each of the plurality of light emitting elements arranged in the plurality of rows and columns, and the first power signal is coupled to an anode of each of the plurality of light emitting elements arranged in the plurality of rows and columns.

15. The pixel circuit according to claim 11, wherein: It also includes a switching element that couples the third power supply signal and the cathode of the light-emitting element, and a control signal applied to the switching element, wherein in the second cycle of the data signal, the control signal is configured to turn on the switching element so that the first power supply signal does not apply a bias to the light-emitting element, and the third power supply signal is coupled to the anode of the light-emitting element.

16. The pixel circuit according to claim 11, wherein: The first power signal is configured to change based on the data signal; in a first cycle of the data signal, the value of the first power signal is equal to Vdd, and the value of the second power signal is equal to the negative power voltage; and in a second cycle of the data signal, the value of the first power signal is configured to decrease so that the value of the second power signal is higher than the value of the first power signal.

17. A circuit for driving a light-emitting element, comprising: An alternating current (AC) power supply circuit includes a first power supply circuit configured to output a first power supply signal and a second power supply circuit configured to output a second power supply signal, wherein: the first power supply signal is between a first high power supply value and a first low power supply value, the first high power supply value is greater than the first low power supply value, and the first high power supply value and the low power supply value are equal to or greater than zero; the second power supply signal is between a second high power supply value and a second low power supply value, the second high power supply value is greater than the second low power supply value, and the second high power supply value and the low power supply value are less than or equal to zero; and a power supply swing value of the AC power supply circuit is equal to the difference between the first high power supply value and the second low power supply value, and the difference is equal to or greater than the driving voltage across the light-emitting element.

18. The circuit of claim 17, further comprising a first switching circuit coupled to the first power circuit and a second switching circuit coupled to the second power circuit, wherein: The first switching circuit includes a first capacitor, and the second switching circuit includes a second capacitor; in response to the first power circuit outputting the first high power value, the first capacitor is configured to be coupled to the first power circuit through a switch; And in response to the second power circuit outputting the second low power value, the second capacitor is configured to be coupled to the second power circuit through another switch.

19. The circuit of claim 18 , wherein in response to the first power supply circuit outputting the first low power supply value, the first capacitor is configured to be decoupled from the first power supply circuit via the switch; and in response to the second power supply circuit outputting the second high power supply value, the second capacitor is configured to be decoupled from the second power supply circuit via the other switch.

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