Semiconductor device and method for manufacturing semiconductor device

Abstract

A thickness of solder can be reduced, and damage to a ceramic circuit substrate and solder can be suppressed. A metal base plate (30) has a rectangular shape in plan view, and a joining region is provided on a front surface, and a center line CL1 is provided in the center of the metal base plate (30) in parallel with and sandwiched by a pair of short sides (31a, 31c) opposite each other. A ceramic circuit substrate (21) includes a ceramic substrate having a rectangular shape in plan view, a circuit pattern formed on a front surface of the ceramic substrate and joining a semiconductor chip, and a metal plate (23) formed on a back surface of the ceramic substrate (22) and joined to the joining region by solder (25a, 25b). At this time, the solder (25a, 25b) has a stress relaxation region (25a1, 25b1) in which a density of voids included in the solder (25a, 25b) is higher than in other regions, in an edge portion on a side away from the center line CL1.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] A semiconductor device includes multiple ceramic circuit boards, semiconductor chips disposed on the multiple ceramic circuit boards, and a metal substrate bonded to the front side of the multiple ceramic circuit boards. Each ceramic circuit board includes a ceramic substrate, a metal plate disposed on the back side of the ceramic substrate, and a circuit pattern disposed on the front side of the ceramic substrate. The semiconductor chips are disposed on the circuit pattern of the ceramic circuit boards. The semiconductor chips include power devices. Power devices are, for example, IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The multiple ceramic circuit boards, each disposed on a semiconductor chip, are disposed on the front side of the metal substrate by solder. In the semiconductor device, heat from the heated semiconductor chip is conducted from the ceramic circuit boards to the metal substrate for heat dissipation. To improve the heat dissipation of the semiconductor device, for example, the solder between the ceramic circuit boards and the metal substrate is thinned.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2015-170826 Summary of the Invention

[0006] Technical issues

[0007] However, in semiconductor devices, if the solder is made too thin, excessive stress can easily be applied to the ceramic circuit board and solder due to differences in thermal expansion between the metal substrate and the ceramic circuit board. This can lead to peeling and / or cracking of the ceramic circuit board and solder, damaging the semiconductor device.

[0008] The present invention was made in view of this, and its object is to provide a semiconductor device and a method for manufacturing the semiconductor device that can reduce the thickness of the solder and suppress damage to the ceramic circuit board and the solder.

[0009] Technical solution

[0010] According to one aspect of the present invention, a semiconductor device is provided, comprising: a first semiconductor chip; a metal substrate, which is rectangular in shape when viewed from above, and has a bonding region on its front side, and a first center line is provided at the center parallel to and sandwiched by a pair of opposing first sides; and a first insulating circuit substrate, comprising a first insulating plate that is rectangular in shape when viewed from above, a first circuit pattern formed on the front side of the first insulating plate and bonded to the first semiconductor chip, and a metal plate formed on the back side of the first insulating plate and bonded to the bonding region by a first bonding member, wherein the first bonding member has a first stress-relieving region at a first edge portion on a side away from the first center line, and in the first stress-relieving region, the density of voids contained in the first bonding member is higher than the density of voids contained in the first bonding member in other regions.

[0011] In addition, according to one aspect of the present invention, a method for manufacturing the above-described semiconductor device is provided.

[0012] Technical effect

[0013] According to the disclosed technology, heat dissipation can be improved by reducing the thickness of the solder, and damage to the ceramic circuit board and solder can be suppressed, thereby enabling semiconductor devices to achieve higher capacity and improved reliability.

[0014] The above and other objects, features and advantages of the present invention will become clear from the following description in conjunction with the accompanying drawings, which illustrate preferred embodiments as examples of the present invention. Attached Figure Description

[0015] Figure 1 This is a top view of the semiconductor device according to the embodiment.

[0016] Figure 2 This is a top view of the solder of the semiconductor device in the embodiment.

[0017] Figure 3 This is a cross-sectional view of the semiconductor device according to the embodiment.

[0018] Figure 4 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment.

[0019] Figure 5 This is a diagram illustrating the mounting process included in the manufacturing method of the semiconductor device for illustrating the embodiments.

[0020] Figure 6 This is a diagram (one of) illustrating the heating process included in the manufacturing method of a semiconductor device for explaining an embodiment.

[0021] Figure 7This is a diagram (second one) illustrating the heating process included in the manufacturing method of the semiconductor device for explaining the embodiments.

[0022] Figure 8 This is a diagram illustrating the cooling process included in the manufacturing method of a semiconductor device according to an embodiment.

[0023] Figure 9 This is a diagram illustrating the solder in the heating and cooling processes of a semiconductor device manufacturing method according to an embodiment.

[0024] Figure 10 This is a top view (one) of a semiconductor device for reference.

[0025] Figure 11 This is a cross-sectional view (one) of a semiconductor device for reference.

[0026] Figure 12 This is a top view (one) of a semiconductor device for reference.

[0027] Figure 13 This is a cross-sectional view (second example) of a semiconductor device.

[0028] Figure 14 This is a cross-sectional view (third one) of a semiconductor device for reference.

[0029] Figure 15 This is a top view of a semiconductor device according to a variation of embodiment 1.

[0030] Figure 16 This is a top view of a semiconductor device according to a variation of the embodiment 2.

[0031] Figure 17 This is a top view of the semiconductor device of the embodiments of variation 3 and variation 4.

[0032] Figure 18 This is a top view of the semiconductor device of Embodiment 5.

[0033] Symbol Explanation

[0034] 10: Semiconductor devices

[0035] 20, 20a, 20b, 20c: Semiconductor units

[0036] 21: Ceramic circuit board

[0037] 22: Ceramic substrate

[0038] 23: Metal plate

[0039] 24a, 24b, 24c, 24d: Circuit patterns

[0040] 25a, 25b, 25c: Solder

[0041] 25a1~25a3, 25b1~25b3: Stress-relieving regions

[0042] 27a, 27b, 27c: Board solder

[0043] 27a1, 27b1, 27c1: Molten solder

[0044] 28a, 28b: Semiconductor chips

[0045] 29a, 29b, 29c: Low heat dissipation areas

[0046] 29a1, 29b1, 29c1, 29c4: Short side portion

[0047] 29a2, 29a3, 29b2, 29b3, 29c2, 29c3: Long side portion

[0048] 30: Metal base plate

[0049] 31: Heat sink

[0050] 31a, 31c: Short side

[0051] 31b, 31d: Long side

[0052] 32a~35a, 32b~35b: Protrusions

[0053] 36a, 36b: Joint area

[0054] 50: Platform

[0055] 51: Heating plate

[0056] 52: Cooling plate Detailed Implementation

[0057] The embodiments will now be described with reference to the accompanying drawings. It should be noted that in the following description, "front" and "top surface" refer to the... Figure 1 and Figure 3 The upper surface of the semiconductor device 10. Similarly, "upper" indicates that... Figure 1 and Figure 3 The direction of the upper side in the semiconductor device 10. "Back side" and "lower surface" indicate that in Figure 1 and Figure 3 The downward-facing surface in the semiconductor device 10. Similarly, "downward" indicates that... Figure 1 and Figure 3The direction of the semiconductor device 10 is shown on the lower side. The same orientation is indicated in other figures as needed. The terms "front," "upper surface," "upper," "back side," "lower surface," "lower," and "side" are merely convenient expressions for determining relative positional relationships and do not limit the technical concept of the invention. For example, "upper" and "lower" do not necessarily indicate the vertical direction relative to the ground. That is, the directions of "upper" and "lower" are not limited to the direction of gravity. Furthermore, in the following description, "main component" indicates a content of 80 vol% or more.

[0058] use Figures 1-3 The semiconductor device in the embodiments will be described. Figure 1 This is a top view of the semiconductor device according to the embodiment. Figure 2 This is a top view of the solder in the semiconductor device according to the embodiment. Figure 3 This is a cross-sectional view of the semiconductor device according to the embodiment. It should be noted that... Figure 1 and Figure 2 The center line CL1 shown is parallel to the pair of opposing short sides 31a and 31c of the metal substrate 30, and passes through the center point enclosed by the pair of short sides 31a and 31c. Similarly, the center line CL2 is parallel to the pair of opposing long sides 31b and 31d of the metal substrate 30, and passes through the center point enclosed by the pair of long sides 31b and 31d. That is, the intersection of center lines CL1 and CL2 is the center point of the semiconductor device 10 when viewed from above. It should be noted that center line CL1 is a dashed line, and center line CL2 is a single-dot dashed line. Furthermore, Figure 2 Is Figure 1 The top view shows the solder 25a and 25b when semiconductor cells 20a and 20b are removed. Figure 3 Show Figure 1 A cross-sectional view at the point marked by a single-dotted line XX.

[0059] Semiconductor device 10 includes two semiconductor units 20a and 20b and a metal substrate 30 on which the semiconductor units 20a and 20b are disposed via solder 25a and 25b. Furthermore, the semiconductor units 20a and 20b are arranged along the long sides 31b and 31d of the metal substrate 30. That is, the center line CL2 crosses the center of the semiconductor units 20a and 20b. Further, the semiconductor units 20a and 20b are arranged on the metal substrate 30 in a linearly symmetrical manner with respect to the center line CL1. The semiconductor units 20a and 20b are thus arranged perpendicularly and parallel to the metal substrate 30. That is, each side of the semiconductor units 20a and 20b is parallel to the short sides 31a and 31c and the long sides 31b and 31d of the metal substrate 30. It should be noted that, hereinafter, without specifically distinguishing between semiconductor units 20a and 20b, they will be described as semiconductor unit 20.

[0060] Semiconductor units 20a and 20b each have a ceramic circuit substrate 21 and semiconductor chips 28a and 28b disposed on the ceramic circuit substrate 21 by solder (not shown). That is, semiconductor units 20a and 20b are both composed of the same components. The ceramic circuit substrate 21 is rectangular in shape when viewed from above. The ceramic circuit substrate 21 includes a ceramic substrate 22, a metal plate 23 disposed on the back side of the ceramic substrate 22, and circuit patterns 24a to 24d disposed on the front side of the ceramic substrate 22. Furthermore, the semiconductor chips 28a and 28b are mechanically and electrically connected to the circuit patterns 24a to 24d by solder.

[0061] The ceramic substrate 22 is rectangular when viewed from above. Furthermore, the corners of the ceramic substrate 22 may be chamfered. The chamfering can be, for example, an R-shaped chamfer or a C-shaped chamfer. The ceramic substrate 22 is made of ceramic with good thermal conductivity. The ceramic may be made of a material primarily composed of alumina, aluminum nitride, or silicon nitride. Additionally, the thickness of the ceramic substrate 22 is 0.5 mm or more and 2.0 mm or less.

[0062] The metal plate 23 is rectangular when viewed from above. Additionally, the metal plate 23 may be chamfered. The chamfer can be, for example, an R-shaped chamfer or a C-shaped chamfer. The size of the metal plate 23 is smaller than the size of the ceramic substrate 22, and it is formed on the entire surface of the ceramic substrate 22 except for the edges. The metal plate 23 is configured with a metal with excellent thermal conductivity as its main component. The metal is, for example, copper, aluminum, or an alloy containing at least one of these. Furthermore, the thickness of the metal plate 23 is 0.1 mm or more and 2.0 mm or less. To improve the corrosion resistance of the metal plate 23, a plating process can be performed. In this case, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy.

[0063] Circuit patterns 24a to 24d are uniformly formed across the entire surface of the ceramic substrate 22, excluding the edges. Preferably, when viewed from above, the outer peripheral ends of the circuit patterns 24a to 24d on the ceramic substrate 22 overlap with the outer peripheral ends of the ceramic substrate 22 on the metal plate 23. Circuit patterns 24a and 24d that are not bonded to the semiconductor chips 28a and 28b are formed on the long sides 31d and 31b of the metal base plate 30 relative to the ceramic substrate 22. Circuit patterns 24b and 24c that are bonded to the semiconductor chips 28a and 28b are formed between the circuit patterns 24a and 24d relative to the ceramic substrate 22. Furthermore, circuit pattern 24c is formed on the side of the center line CL1, and circuit pattern 24b is formed on the side away from the center line CL1, and is formed to extend adjacent to circuit pattern 24c along the short sides 31a and 31c of the metal base plate 30.

[0064] If the circuit pattern 24b is not formed in the region that overlaps with the first stress relief regions 25a1 and 25b1 (described later) when viewed from above, the stress balance between the ceramic circuit substrate 21 and the metal plate 23 on the back side of the ceramic substrate 22 is disrupted. Therefore, excessive warping, cracks, or other damage to the ceramic substrate 22 may occur. It should be noted that in this embodiment, the circuit pattern 24b is shown extending to the region overlapping with the first stress relief regions 25a1 and 25b1. That is, the circuit pattern 24b includes a non-mounted region that overlaps with the first stress relief regions 25a1 and 25b1 and is not bonded to the semiconductor chips 28a and 28b. However, this is not a limitation; the circuit pattern 24b may be formed in a region that does not overlap with the first stress relief regions 25a1 and 25b1, and other circuit patterns may be formed in the regions that overlap with the first stress relief regions 25a1 and 25b1. For example, the circuit patterns 24a and 24d may also extend to the regions overlapping with the first stress relief regions 25a1 and 25b1.

[0065] Furthermore, the thickness of circuit patterns 24a to 24d is 0.5 mm or more and 1.5 mm or less. Circuit patterns 24a to 24d are made of a metal with excellent electrical conductivity. Such metals are, for example, copper, aluminum, or alloys containing at least one of these. Additionally, to improve corrosion resistance, the surface of circuit patterns 24a to 24d can be plated. The plating material used is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy. The circuit patterns 24a to 24d relative to the ceramic substrate 22 are obtained by forming a metal plate on the front side of the ceramic substrate 22 and etching the metal plate. Alternatively, circuit patterns 24a to 24d, pre-cut from a metal plate, can be pressed onto the front side of the ceramic substrate 22. It should be noted that circuit patterns 24a to 24d are just one example. The number, shape, and size of the circuit patterns can be appropriately selected as needed. As such a ceramic circuit board 21, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate can be used.

[0066] In addition, such as Figure 1As shown, the front surface of the ceramic circuit substrate 21 of the semiconductor units 20a and 20b is provided with low heat dissipation regions 29a and 29b along three sides when viewed from above. Specifically, the low heat dissipation regions 29a and 29b include short side portions 29a1 and 29b1 and long side portions 29a2, 29a3, 29b2, and 29b3. The short side portions 29a1 and 29b1 are positioned relative to the front surface of the ceramic circuit substrate 21 on the side of short sides 31c and 31a away from the center line CL1 of the metal base plate 30 (heat sink 31). The long side portions 29a2, 29a3, 29b2, and 29b3 are positioned relative to the front surface of the ceramic circuit substrate 21 on the side of long sides 31d and 31b that sandwich the center line CL2 of the metal base plate 30 (heat sink 31). Furthermore, as... Figure 2 As shown, stress-relieving regions 25a1–25a3 and 25b1–25b3 are respectively set at the locations where the solder 25a and 25b of semiconductor cells 20a and 20b overlap with the low-heat dissipation regions 29a and 29b when viewed from above. It should be noted that the low-heat dissipation regions 29a and 29b and the stress-relieving regions 25a1–25a3 and 25b1–25b3 will be described later.

[0067] Semiconductor chip 28a includes switching elements. These switching elements are, for example, IGBTs or power MOSFETs. When semiconductor chip 28a is an IGBT, it has a collector electrode as a main electrode on its back side, a gate electrode as a control electrode on its front side, and an emitter electrode as a main electrode. When semiconductor chip 28a is a power MOSFET, it has a drain electrode as a main electrode on its back side, a gate electrode as a control electrode on its front side, and a source electrode as a main electrode. The back side of the semiconductor chip 28a is bonded to circuit pattern 24c by solder (not shown). Wiring components are appropriately connected to the main electrode and gate electrode on the front side of the semiconductor chip 28a via electrical or mechanical connections. These wiring components are, for example, bonding wires, lead frames, pin-shaped or strip-shaped components.

[0068] Semiconductor chip 28b includes a diode. The diode is, for example, an SBD (Schottky Barrier Diode), a PiN (P-intrinsic-N) diode, or a FWD (Free Wheeling Diode). Such a semiconductor chip 28b has an output electrode (cathode) as a main electrode on its back side and an input electrode (anode) as a main electrode on its front side. The back side of the semiconductor chip 28b is bonded to the circuit pattern 24b by solder (not shown). It should be noted that the semiconductor chip 28b is bonded to the area of ​​the circuit pattern 24b except for the area overlapping with the low-heat dissipation areas 29a and 29b. Wiring components are also appropriately connected to the main electrode on the front side of the semiconductor chip 28b by electrical and mechanical connections. Wiring components are, for example, bonding wires, lead frames, pin-shaped or strip-shaped components.

[0069] Alternatively, RC (Reverse-Conducting)-IGBTs, which combine the functions of IGBTs and FWD, can be used to replace semiconductor chips 28a and 28b. Furthermore, in Figure 1 and Figure 3 The diagram only shows the case where two sets of semiconductor chips 28a and 28b are provided. It is possible to provide a number of sets corresponding to the specifications of the semiconductor device 10, not limited to two sets. These semiconductor chips are bonded to the front side of the ceramic circuit board 21, excluding the low-heat-dissipation regions 29a and 29b that overlap with the stress-relieving regions 25a1–25a3 and 25b1–25b3.

[0070] Alternatively, depending on the design and specifications of the semiconductor device 10, wiring components and electronic components may be mounted. In this case, the wiring components and electronic components may also be mounted in the area of ​​the circuit pattern 24b that overlaps with the low-heat dissipation areas 29a and 29b. It should be noted that wiring components include, for example, terminals, lead frames, and wires. Electronic components include, for example, resistors, capacitors, and thermistors.

[0071] Lead-free solder is used to bond semiconductor chips 28a and 28b to circuit patterns 24b and 24c. The lead-free solder has at least one alloy as its main component. Examples of such alloys include, for example, tin-silver-copper alloys, tin-zinc-bismuth alloys, tin-copper alloys, and tin-silver-indium-bismuth alloys. Furthermore, the solder may contain additives. These additives are, for example, nickel, germanium, cobalt, or silicon. By including additives, the solder's wettability, gloss, bond strength, and reliability can be improved. Alternatively, a sintered metal body may be used instead of solder. The sintered metal body is primarily composed of silver or a silver alloy.

[0072] The metal base plate 30 is made of a metal with excellent thermal conductivity. Such a metal is, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these. Furthermore, to improve corrosion resistance, the surface of the metal base plate 30 can be plated. The plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy. Additionally, the coefficient of thermal expansion of the metal base plate 30 is greater than that of the ceramic circuit board 21. The metal base plate 30 can be rectangular in shape when viewed from above. Furthermore, the corners can be chamfered. The chamfer can be an R-shaped chamfer or a C-shaped chamfer. This metal base plate 30 includes a heat sink 31 and protrusions 32a-35a, 32b-35b formed on the front side of the heat sink 31.

[0073] The heat sink 31 is a flat section within the metal base plate 30. For example... Figure 3 As shown, the heat sink 31 is convex downwards with the center portion through which the center line CL1 on the back side passes as its lower side. That is, the heat sink 31 is convex downwards with the center portion as its lower side, and the short sides 31a, 31c and the long sides 31b, 31d of the heat sink 31 are located above the center portion. This is caused by the heating performed during the manufacturing process of the semiconductor device 10, as described later. The average thickness of the entire heat sink 31 is more than 1 mm and less than 10 mm. In addition, bonding regions 36a and 36b are provided on the front side of the heat sink 31. Semiconductor units 20a and 20b are arranged in the bonding regions 36a and 36b as described later. The metal base plate 30 (heat sink 31) is convex downwards with its center portion. Therefore, the two bonding regions 36a and 36b are not provided at the center portion of the heat sink 31, but are provided to be linearly symmetrical, sandwiching the center line CL1 of the heat sink 31. Specifically, in Figure 1 In this case, the mating areas 36a and 36b are respectively positioned on the left and right sides, sandwiching a centerline CL1 that passes through the center of the heat sink 31 and is parallel to the short sides 31a and 31c. It should be noted that the heat sink 31 has mounting holes formed at corners, etc., as needed. By threading the mounting holes, the metal base plate 30 is mounted in a predetermined position, and the cooler, described later, is also installed.

[0074] Furthermore, the protrusions 32a-35a and 32b-35b of the metal base plate 30 are integrally formed with the corners of the bonding areas 36a and 36b of the heat sink 31. The bonding areas 36a and 36b of the heat sink 31 can be located opposite to the semiconductor units 20a and 20b. That is, the bonding areas 36a and 36b of the heat sink 31 can be located opposite to the back surface of the metal plate 23 of the ceramic circuit board 21. Therefore, the protrusions 32a-35a and 32b-35b can be located opposite to the corners of the semiconductor units 20a and 20b. More specifically, they can be located opposite to the corners of the back surface of the metal plate 23 of the ceramic circuit board 21. It should be noted that the protrusions 32a-35a and 32b-35b have the same height. Their height is, for example, 0.05 mm or more and 0.5 mm or less. Furthermore, the diameters of the protrusions 32a-35a and 32b-35b are, for example, 50 μm or more and 500 μm or less. Additionally, the protrusions 32a-35a and 32b-35b are not limited to... Figure 3 The protrusions 32a-35a and 32b-35b can also be, for example, hemispherical, semi-ellipsoidal, or cubic. Alternatively, they can be convex shapes that connect the protrusions 32a and 34a along the edge of the ceramic circuit board 21. Similarly, the protrusions 33b, 35b, 33a, 35a, 32b, and 34b can also be convex shapes that connect the protrusions along the edge of the ceramic circuit board 21.

[0075] It should be noted that a cooler (not shown) can also be mounted on the back of such a metal base plate 30 via heat sinks or thermal grease. In this case, the mounting holes of the metal base plate 30 and the cooler are threaded together. Alternatively, they can be joined using solder or silver solder. This improves the heat dissipation of the metal base plate 30. In this case, the cooler is made of a metal with excellent thermal conductivity. Such a metal is, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these. Furthermore, as a cooler, a radiator consisting of multiple heat sinks, a water-based cooling device, etc., can be used. In addition, the metal base plate 30 can also be integrated with such a cooler. Moreover, to improve corrosion resistance, the surface of the cooler mounted on the metal base plate 30 can be plated. In this case, the plating material used is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy.

[0076] Semiconductor units 20a and 20b are disposed in the bonding areas 36a and 36b of the metal base plate 30 via solder 25a and 25b. At this time, as... Figure 3 As shown, solder 25a and 25b are formed between the front side of the metal base plate 30 and the back side of the metal plate 23 of the ceramic circuit board 21. Thus, the front side of the metal base plate 30 is bonded to the back side of the metal plate 23 of the ceramic circuit board 21. It should be noted that in Figure 3 In the diagram, the positions of protrusions 34a and 35b are indicated by dashed lines. Furthermore, the front ends of protrusions 33a, 35a, 32b, and 34b located on the side furthest from the center line CL1 of the metal substrate 30 abut against the back surfaces of semiconductor cells 20a and 20b. On the other hand, protrusions 32a, 34a, 33b, and 35b closer to the center line CL1 are separated from the back surfaces of semiconductor cells 20a and 20b at all locations, including their front ends. Thus, the ceramic circuit board 21 is maintained at approximately a horizontal position. Moreover, solder 25a and 25b are located between the bonding regions 36a and 36b of the ceramic circuit board 21 and the metal substrate 30. Therefore, the thickness of the solder 25a and 25b on the side furthest from the center line CL1 corresponds to the height of the protrusions 33a, 35a, 32b, and 34b.

[0077] Here, the details of solders 25a and 25b are explained. It should be noted that solders 25a and 25b are the same solders used to bond semiconductor chips 28a and 28b and circuit patterns 24b and 24c (in... Figure 3 Solder 25c) is the same solder shown. In addition, solders 25a and 25b, like the solders already described, may contain additives as needed.

[0078] Solder 25a and 25b join the metal base plate 30 and the metal plate 23. Solder 25a and 25b form solder feet that extend smoothly downwards from the outer periphery of the metal plate 23. Furthermore, solder 25a and 25b correspond to the joining areas 36a and 36b of the downwardly convex, warped metal base plate 30 and the flat metal plate 23. That is, the metal plate 23 side of solder 25a and 25b is generally flat, while the metal base plate 30 side of solder 25a and 25b is curved into an arc shape. Additionally, the thickness of solder 25a and 25b is sufficiently thin. Moreover, the thickness of solder 25a and 25b is thinner outside the centerline CL1 (on the short sides 31a and 31c of the metal base plate 30) than on the centerline CL1 side. Preferably, the thickness of solders 25a and 25b is 0.20 mm or more and 0.60 mm or less at the edge near the center line CL1, and 0.05 mm or more and 0.45 mm or less at the edge away from the center line CL1. For example, the thickness at the edge away from the center line CL1 is about 0.25 mm, and the thickness at the edge near the center line CL1 is about 0.40 mm. Alternatively, solders 25a and 25b may include a warped portion that matches the shape of the metal base plate 30. Therefore, solders 25a and 25b may also have a portion that is thicker than the edge near the center line CL1 from the edge near the center line CL1 to the edge away from the center line CL1.

[0079] like Figure 2As shown, solders 25a and 25b respectively include stress-relieving regions 25a1-25a3 and 25b1-25b3. The stress-relieving regions 25a1-25a3 and 25b1-25b3 are regions where the density of voids (cavities CA1-CA3 and / or voids VO) contained in solders 25a and 25b is higher than the density of voids contained in other regions of solders 25a and 25b. The stress-relieving regions 25a1 and 25b1 (first stress-relieving regions) are included along one edge of solders 25a and 25b away from the center line CL1, encompassing a region of a predetermined width from that edge. Furthermore, stress-relieving regions 25a2, 25a3, 25b2, and 25b3 (second stress-relieving regions) are respectively included at the edges of solders 25a and 25b away from the center line CL2. The stress relief regions 25a1 to 25a3 and 25b1 to 25b3 can be regions extending inward from the end edge of the joint regions 36a and 36b on the side away from the center lines CL1 and CL2 until they reach a length of more than 5% and less than 30% of the length of the end edge orthogonal to that end edge.

[0080] Furthermore, the stress-relieving regions 25a1-25a3 and 25b1-25b3 can be regions corresponding to the central portions of each side of the ceramic circuit substrate 21. This is because in the semiconductor device 10, the shrinkage holes CA1-CA3 are as follows: Figure 2As shown, the cavity CA1 is formed by entering the inner side from the center of the end edge on the side away from the center lines CL1 and CL2 of the ceramic circuit board 21. It should be noted that the cavities CA1 are formed by entering the inner side from the center of the end edge on the side away from the center line CL1. The cavities CA2 and CA3 are formed by entering the inner side from the center of the end edge on the side away from the center line CL2. The stress relief regions 25a1 to 25a3 and 25b1 to 25b3 are simply regions that at least include such cavities CA1 to CA3. It should be noted that voids VO are easily generated around the cavities CA1 to CA3. For example, the stress relief regions 25a1 and 25b1 (first stress relief regions) can be formed on one edge of the solder 25a and 25b on the side away from the center line CL1 and include the region of the center line CL2 of the solder 25a and 25b. Furthermore, stress-relief regions 25a2, 25a3, 25b2, and 25b3 can be formed on a pair of edges of solder 25a and 25b away from the center line CL2, and include the respective center lines of solder 25a and 25b (lines parallel to the short sides 31a and 31c and passing through the center of solder 25a and 25b respectively). Given the location and extent of the shrinkage cavities CA1 to CA3, the stress-relief regions 25a1 to 25a3 and 25b1 to 25b3 in this case can have the following ranges. That is, the stress relief regions 25a1 to 25a3 and 25b1 to 25b3 can be regions extending inward from the end edge of the joint regions 36a and 36b on the side away from the center lines CL1 and CL2 until they reach a length of more than 5% and less than 30% of the length of the end edge orthogonal to that end edge. Further, they are the outward regions extending from the center of that end edge to a length of more than 5% and less than 30% of the length of that end edge.

[0081] Solder 25a and 25b contain voids within them. These voids include, for example, voids VO surrounded by solder 25a and 25b, and shrinkage cavities CA1 to CA3 extending from the edges of the bonding regions 36a and 36b into the interior of the bonding regions 36a and 36b and connecting to the exterior of the bonding regions 36a and 36b. It should be noted that the formation of voids (shrinkage cavities CA1 to CA3, voids VO) during the manufacturing process of the semiconductor device 10 will be described later.

[0082] In the semiconductor device 10, cracks and / or peeling are easily generated at the outer periphery of the ceramic circuit board 21 and the outer periphery of the solders 25a and 25b due to the difference in the coefficients of thermal expansion between the ceramic circuit board 21 and the metal substrate 30. In this embodiment, by providing stress-relieving regions 25a1 to 25a3 and 25b1 to 25b3 in the solders 25a and 25b, the generation of cracks and peeling can be suppressed in the ceramic circuit board 21 and the solders 25a and 25b.

[0083] On the other hand, heat generated from semiconductor chips 28a and 28b is conducted from the ceramic circuit substrate 21 through solders 25a and 25b, thereby dissipating heat from the metal base plate 30 to the outside. At this time, if gaps exist at the locations where heat is conducted through the solders 25a and 25b, the thermal conductivity decreases (thermal resistance increases), resulting in reduced heat dissipation. Specifically, the stress-relief regions 25a1–25a3 and 25b1–25b3 included in the solders 25a and 25b have a higher density of gaps compared to other regions, thus significantly reducing thermal conductivity. Therefore, when viewed from above, low-heat dissipation regions 29a and 29b are respectively provided on the front side of the ceramic circuit substrate 21, overlapping with the stress-relief regions 25a1–25a3 and 25b1–25b3. Furthermore, the semiconductor chips 28a and 28b are bonded to the circuit patterns 24b and 24c on the front side of the ceramic circuit substrate 21, excluding the low-heat dissipation regions 29a and 29b. Therefore, it is possible to suppress the decrease in heat dissipation of the semiconductor device 10.

[0084] It should be noted that, although the illustrations are omitted in this embodiment, the semiconductor device 10 can also be encapsulated using an encapsulating resin. In this case, the encapsulation component comprises a thermosetting resin and a filler contained within the thermosetting resin. Thermosetting resins are, for example, epoxy resins, phenolic resins, or maleimide resins. As an example of such an encapsulation component, there is an epoxy resin containing a filler. The filler is an inorganic material. Examples of inorganic materials include silicon oxide, aluminum oxide, boron nitride, or aluminum nitride.

[0085] Next, use Figures 4-8 The manufacturing method of the semiconductor device 10 will be described. Figure 4 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment. Figure 5 This is a diagram illustrating the mounting process included in the manufacturing method of the semiconductor device according to the embodiment. Figure 6 and Figure 7 This is a diagram illustrating the heating process included in the manufacturing method of the semiconductor device according to the embodiment. Figure 8 This diagram illustrates the cooling process included in the manufacturing method of the semiconductor device according to the embodiment. It should be noted that... Figures 5-8 Is with Figure 1 A sectional view of the location corresponding to the single-dotted line XX.

[0086] First, a preparation process (step S1) is performed to prepare the components of the semiconductor device 10, such as semiconductor chips 28a and 28b, ceramic circuit board 21, metal substrate 30, and board solder. In addition, along with the solder bonding device described later, a jig for position alignment used in the mounting process is also prepared.

[0087] Next, a mounting process is performed on the placement stage 50 of the solder bonding apparatus, in which the metal base plate 30, solder 27a and 27b, ceramic circuit board 21, and semiconductor chips 28a and 28b are sequentially mounted (see reference). Figure 5 (Step S2). It should be noted that, in Figure 5 The semiconductor chip 28b is shown in the diagram. Additionally, the center portion through which the centerline CL1 of the metal substrate 30 passes can also be slightly convex upwards. That is, the metal substrate 30 can also be warped such that its center portion protrudes upwards compared to the short sides 31a, 31c and the long sides 31b, 31d. The solder plates 27a and 27b are respectively provided with their back surfaces supported by protrusions 32a-35a and 32b-35b formed in the bonding areas 36a and 36b of the metal substrate 30. The solder plates 27a and 27b are plate-shaped and composed of the same material as the solder plates 25a and 25b described above. Furthermore, the dimensions of the solder plates 27a and 27b are such that, when viewed from above, their corners are supported by protrusions 32a-35a and 32b-35b, respectively. Furthermore, the thickness of the solder 27a and 27b is configured to be approximately the same as or slightly higher than the heights of the protrusions 32a-35a and 32b-35b. A ceramic circuit board 21 is disposed on such solder 27a and 27b. The solder 27a and 27b are disposed on the back side of the metal plate 23 of the ceramic circuit board 21. Alternatively, solder paste may be used instead of solder 27a and 27b. In the case of solder paste, it can be applied to the bonding areas 36a and 36b including the protrusions 32a-35a and 32b-35b.

[0088] It should be noted that the solder bonding apparatus includes a mounting stage 50, a heating plate 51 and a cooling plate 52 (described later), and a control device for controlling them. In the solder bonding apparatus, a metal base plate 30 is fed to the mounting stage 50, the heating plate 51, and the cooling plate 52 in each step S2 to S4. Furthermore, the control device included in the solder bonding apparatus appropriately heats the heating plate 51 and then stops heating. The heating temperature and heating time are appropriately controlled by the control device included in the solder bonding apparatus. Similarly, the control device included in the solder bonding apparatus appropriately cools the cooling plate 52 and then stops cooling. The cooling temperature and cooling time are appropriately controlled by the control device included in the solder bonding apparatus.

[0089] Furthermore, semiconductor chips 28a and 28b are disposed on circuit patterns 24b and 24c of the ceramic circuit board 21 using solder 27c. Semiconductor chips 28b are mounted on circuit patterns 24b, avoiding low-heat-dissipation areas 29a and 29b. It should be noted that the solder 27c beneath semiconductor chips 28a and 28b is of the same type as solder 27a and 27b. Additionally, in step S2, a jig capable of aligning with the bonding areas 36a and 36b of the metal base plate 30 is used. This jig is flat and has the same dimensions as the metal base plate 30 when viewed from above, with an opening slightly larger than the bonding areas 36a and 36b in the area corresponding to them. Furthermore, the jig is made of a material with excellent heat resistance. Such materials include, for example, composite ceramic materials and carbon. The opening of the fixture on the metal base plate 30 is provided with board solder 27a, 27b, ceramic circuit board 21, board solder 27c, and semiconductor chips 28a, 28b.

[0090] Next, a heating process (step S3) is performed in which the metal base plate 30, board solder 27a, 27b, ceramic circuit board 21, board solder 27c, and semiconductor chips 28a, 28b are heated by driving the solder bonding device.

[0091] In step S3, with the back of the metal base plate 30 positioned on the heating plate 51 in the solder bonding apparatus, the solder bonding apparatus is driven to heat the heating plate 51, thereby heating the metal base plate 30, the solder 27a and 27b, the ceramic circuit board 21, the solder 27c, and the semiconductor chips 28a and 28b. The upper surface of the heating plate 51 is flat, and it contains a heating mechanism such as a heater. First, heat emitted from the heating plate 51 is conducted to the back of the metal base plate 30. At this time, the metal base plate 30 is heated from the back, causing rapid thermal expansion on the back side, such as... Figure 6 As shown, the metal base plate 30 is warped in a manner that bulges downwards from the center. That is, the short sides 31a, 31c and the long sides 31b, 31d are warped such that they are positioned above the center. Therefore, the metal base plate 30 is heated from the center of the back surface by the heating plate 51. Heat travels along... Figure 6 The dashed arrows extend from the center of the back of the metal base plate 30 (centerline CL1) to the outer edge of the metal base plate 30 (heat sink 31). Heat is conducted through the heat sink 31 to the protrusions 32a-35a and 32b-35b. Then, the solder 27a and 27b supported by the protrusions 32a-35a and 32b-35b are heated and melted.

[0092] The molten solder 27a1 and 27b1, formed from the melting of solder 27a and 27b, flows towards the heat sink 31. Furthermore, they are pressed towards the heat sink 31 by the weight of the ceramic circuit board 21 and the semiconductor chips 28a and 28b. At this time, as... Figure 7 As shown, the ceramic circuit board 21 is approximately horizontal relative to the heating plate 51. Therefore, in this state, the thickness of the edge portion of the molten solder 27a1, 27b1, which is completely melted from the board solder 27a, 27b, away from the center line CL1 of the metal substrate 30, is thinner than the thickness of the edge portion closer to the center line CL1. Additionally, at this time, the board solder 27c under the semiconductor chips 28a, 28b also melts into molten solder 27c1. The molten solder 27c1 is pressed towards the circuit patterns 24a to 24d by the weight of the semiconductor chips 28a, 28b.

[0093] It should be noted that protrusions 32a-35a and protrusions 32b-35b are rod-shaped. Therefore, the molten solder 27a1 and 27b1 formed from the melted solder 27a and 27b easily descends along the protrusions 32a-35a and protrusions 32b-35b towards the bonding regions 36a and 36b. Furthermore, the protrusions 32a-35a and protrusions 32b-35b are rod-shaped and are located at the corners of the bonding regions 36a and 36b. Therefore, it is less likely to hinder the spread of the molten solder 27a1 and 27b1 in the bonding regions 36a and 36b. Additionally, the protrusions 33a, 35a and 32b, 34b of the metal base plate 30 located on the side away from the center line CL1 abut against the back side of the semiconductor units 20a and 20b at least at their front ends. On the other hand, the protrusions 32a, 34a and 33b, 35b near the centerline CL1 are separated from the back surface of the semiconductor cells 20a, 20b at all locations, including their front ends. It should be noted that details regarding the melting of the board solder 27a, 27b into the molten solder 27a1, 27b1 during the heating process will be described later.

[0094] Next, the heating of the heating plate 51 by the solder bonding device is stopped, and the cooling process of the molten solder 27a1 and 27b1 is carried out (step S4). Figure 8As shown, with the metal base plate 30 positioned on the cooling plate 52 of the solder bonding device on its back side, the cooling plate 52 is cooled. Thus, the metal base plate 30, molten solder 27a1, 27b1, ceramic circuit board 21, molten solder 27c1, and semiconductor chips 28a, 28b are cooled. The upper surface of the cooling plate 52 is flat, and it contains a cooling mechanism such as water-cooling pipes. It should be noted that the heating plate 51 and cooling plate 52 can also be heating and cooling plates, each serving as both a heating mechanism and a cooling mechanism. It should be noted that the metal base plate 30 is warped such that its short sides 31a, 31c and long sides 31b, 31d are positioned higher than the center. Therefore, the metal base plate 30 is cooled by the cooling plate 52 from the center of its back side. That is, the metal base plate 30 (heat sink 31) is cooled along... Figure 8 The dashed arrows shown indicate that cooling occurs from the center (centerline CL1) towards the outer edge of the metal base plate 30 (heat sink 31). Simultaneously, the molten solder 27a1 and 27b1 are also cooled from the centerline CL1 side outwards. Therefore, as... Figure 8 As shown, during the cooling process, the molten solders 27a1 and 27b1 become as follows: they solidify from the center (centerline CL1), with solidified solder 25a and 25b present on the center (centerline CL1) side and molten solder 27a1 and 27b1 present on the outer edge side of the metal base plate 30. Then, through a further cooling process, they become completely solidified solder 25a and 25b. Additionally, the molten solder 27c1 also becomes completely solidified solder 25c. It should be noted that details regarding the cooling of the molten solders 27a1 and 27b1 during the cooling process will be described later.

[0095] Thus, molten solder 27a1 and 27b1 become solidified solder 25a and 25b. Similarly, molten solder 27c1 becomes solidified solder 25c. As a result, semiconductor chips 28a and 28b are bonded to circuit patterns 24b and 24c via solder 25c. Furthermore, semiconductor units 20a and 20b are bonded to the metal substrate 30 via solder 25a and 25b, thereby manufacturing a semiconductor device 10. This semiconductor device 10 is then removed from the cooling plate 52 of the solder bonding apparatus, resulting in... Figure 1 and Figure 3 The semiconductor device 10 shown.

[0096] Here, use Figure 9 right Figures 4-8 The changes in the plate solder 27a, 27b and molten solder 27a1, 27b2 during the heating and cooling processes are explained. Figure 9 This diagram illustrates the solder in the heating and cooling processes of the semiconductor device manufacturing method according to the embodiment. It should be noted that... Figure 9 schematically shown Figures 6-8 The metal substrate 30, solder 27a and 27b, molten solder 27a1 and 27b1, and the left side of the ceramic circuit board 21 are shown. Furthermore, the heating and cooling processes are shown in chronological order. It should be noted that detailed descriptions of the ceramic circuit board 21 and the semiconductor chip 28a are omitted. Additionally, their respective thicknesses are described at a scale different from the actual thicknesses.

[0097] After the mounting process in step S2, the heating plate 51 is heated, starting from the back of the metal base plate 30. It should be noted that the ceramic circuit board 21 can also be warped with the front side facing up, slightly convex upwards. Alternatively, if the metal base plate 30 is heated, it is warped as described above, with the center convex downwards. Heat travels along... Figure 9 The dashed arrow in (A) conducts heat from the center of the back side of the metal base plate 30 (center line CL1) to the outer edge of the metal base plate 30. Heat is conducted to the protrusions 32a-35a and protrusions 32b-35b. Then, the plate solder 27a and 27b supported by the protrusions 32a-35a and protrusions 32b-35b are heated and melted.

[0098] Then, the molten solder 27a1, formed from the molten solder 27a, is pressed against the metal base plate 30 by the ceramic circuit board 21. Meanwhile, the ceramic circuit board 21 is heated, causing it to warp downwards with its back side facing down. In this state, the molten solder 27a1 and 27b1, formed from the completely molten solder 27a and 27b, are held between the ceramic circuit board 21 and the metal base plate 30. Further, the ceramic circuit board 21 is heated from its back side, causing thermal expansion and warping downwards. That is, both the metal base plate 30 and the ceramic circuit board 21 warp downwards. Therefore, the metal base plate 30 and the ceramic circuit board 21 tilt upwards at positions away from the center line CL1. Therefore, as... Figure 9 As shown in (B), the molten solder 27a1 flows particularly from the edge portion away from the center line CL1 towards the center line CL1. Therefore, the thickness of the molten solder 27a1 at the edge portion near the center line CL1 becomes thicker. On the other hand, the thickness of the molten solder 27a1 at the edge portion away from the center line CL1 becomes thinner. That is, in terms of volume, the edge portion away from the center line CL1 is smaller than the edge portion closer to the center line CL1.

[0099] Next, if cooling begins by the cooling plate 52 of the solder bonding device, the metal base plate 30 along... Figure 9The dashed arrow shown in (C) indicates that the metal substrate 30 is cooled from the center (centerline CL1) toward the outer edge. Simultaneously, the molten solder 27a1 is also cooled from the centerline CL1 side toward the outside. Therefore, the molten solder 27a1 begins to solidify from the centerline CL1 side. The molten solder 27a1 shrinks in volume as it changes from a molten state to a solidified state. Furthermore, the ceramic circuit board 21 is cooled from the back side, causing thermal shrinkage on the back side, resulting in upward warping. Therefore, the molten solder 27a1 at the edge away from the centerline CL1 is introduced to the centerline CL1 side. Thus, the volume of the molten solder 27a1 decreases at the edge away from the centerline CL1. A predetermined gap is provided between the heat sink 31 of the metal substrate 30 and the ceramic circuit board 21 at this position on the side of the molten solder 27a1 away from the centerline CL1 via the protrusion 35a of the metal substrate 30. Therefore, voids and / or shrinkage cavities can be formed on the edge of the molten solder 27a1 on the side away from the centerline CL1. Figure 9 The diagram shows a shrinkage cavity (CA1). In this state, a semiconductor device 10 containing solder 25a formed by the solidification of molten solder 27a1 is shown. Figure 2 and Figure 3 As shown, at the edge of the solder 25a away from the center line CL1, there are first stress relief regions 25a1 and 25b1 where the density of voids contained in the solder 25a is higher than that of voids contained in the solder 25a in other regions.

[0100] Here, use Figures 10-14 A semiconductor device relative to the reference example of semiconductor device 10 will be described. Figure 10 and Figure 12 This is a top view of a semiconductor device for reference. Figure 11 , Figure 13 , Figure 14 This is a cross-sectional view of a semiconductor device as an example. It should be noted that... Figure 10 This illustrates a case where two ceramic circuit boards 210 are arranged on a metal base plate 30. Figure 12 This illustrates a case where a ceramic circuit board 210 is disposed on a metal base plate 30. Figure 11 (A) and Figure 11 (B) shows Figure 10 A cross-sectional view at the point marked by a single-dotted line XX. Figure 11 (A) shows a case where a solder with a thickness that is the same as conventional solder and thicker than the solder of semiconductor device 10 is formed. Figure 11 (B) shows the formation of a thickness ratio Figure 11 The case of (A) is a case where the solder thickness is thin and the solder thickness is the same as that of the semiconductor device 10. Figure 13 and Figure 14This is a cross-sectional view of the semiconductor device 100b without any protrusions on the metal base plate 30. Figure 13 With semiconductor device 10 Figure 3 Corresponding. Additionally. Figure 14 yes Figure 13 Enlarged view of the main part of the dashed area. Furthermore, the semiconductor device in the reference example, which has the same configuration as semiconductor device 10, is labeled with the same symbols, and their descriptions are omitted.

[0101] Semiconductor device 100, such as Figure 10 As shown, semiconductor units 200a and 200b are bonded to the metal substrate 30 along their long sides 31b and 31d in a symmetrical manner about the center line CL1 via solder 25a and 25b. It should be noted that the solder 25a and 25b are thicker than the solder of the semiconductor device 10. Semiconductor units 200a and 200b include a ceramic circuit board 210 and semiconductor chips 28a and 28b disposed on the front side of the ceramic circuit board 210. Semiconductor units 200a and 200b are disposed on the metal substrate 30 along their long sides 31b and 31d. The ceramic circuit board 210 includes a ceramic substrate 22, a metal plate 23 formed on the back side of the ceramic substrate 22, and circuit patterns 24a, 24d, 240b, and 240c formed on the front side of the ceramic substrate 22. The circuit patterns 240b and 240c are different from the circuit pattern of the semiconductor device 10 but have the same shape. In addition, circuit patterns 240b and 240c are bonded to semiconductor chips 28a and 28b, respectively.

[0102] In addition, the semiconductor device 100 is capable of interacting with Figure 4 The flowchart shown is also followed in the manufacturing process. In the semiconductor device 100 thus manufactured, the solders 25a and 25b... Figure 10 No shrinkage cavities were detected in regions A1 and A2 shown. That is, as... Figure 11 As shown in (A), when the thickness of solder 25a and 25b is sufficiently thick, the density of voids such as shrinkage cavities formed in the edge of solder 25a and 25b away from the center line CL1 is higher than the density of voids in other areas.

[0103] In recent years, with the development of large-capacity and miniaturization of semiconductor devices 100, the heat density generated by semiconductor devices 100 has also increased. Therefore, it is desirable for semiconductor devices 100 to efficiently dissipate the heat generated by semiconductor chips 28a, 28b, etc. This is achieved by increasing the thickness of solder 25a, 25b as has been done previously. Figure 11In case (A), regions with a higher density of voids such as shrinkage cavities than other regions will not form. However, since the solder 25a and 25b are relatively thick, there is concern that the thermal resistance may also increase. Therefore, the semiconductor device 100 may overheat and be damaged due to the heat generated by the semiconductor chips 28a and 28b.

[0104] To further improve the heat dissipation of the semiconductor device 100, it is desirable to thin the solder 25a and 25b. By forming the solder 25a and 25b to a sufficiently thin thickness, similar to that of the semiconductor device 10, it is also possible to... Figure 4 The same process is performed as shown in the flowchart. The semiconductor device 100 manufactured by thinning the solder 25a and 25b in this way can achieve improved heat dissipation. However, as in... Figure 9 As explained in the document, if the thickness of solder 25a and 25b is reduced, then as Figure 11 As shown in (B), regions (stress-relieving regions 25a1, 25b1) have a higher density of voids, such as shrinkage cavities CA1, formed at the edges of solder 25a and 25b away from the center line CL1 than other regions. If the stress-relieving regions 25a1 and 25b1 are located at the lower part of semiconductor chips 28a and 28b, the thermal resistance in semiconductor chips 28a and 28b increases.

[0105] In addition, Figure 10 In the semiconductor device 100 shown, semiconductor units 200a and 200b are symmetrically arranged on the metal substrate 30 along the long sides 31b and 31d about the center line CL1. Furthermore, Figure 10 Semiconductor chips 28a and 28b are also disposed in areas A1 and A2 shown. In such a semiconductor device 100, solder 25a and 25b... Figure 10 Stress-relief regions 25a1 and 25b1 are formed in regions A1 and A2 shown. Therefore, semiconductor chips 28a and 28b are disposed in a low-heat-dissipation region overlapping the stress-relief regions 25a1 and 25b1 on the front side of the ceramic circuit board 21. Consequently, the heat dissipation of the semiconductor chips 28a and 28b is reduced, and the semiconductor device 100 may overheat and be damaged.

[0106] Additionally, as another example, in Figure 12 In the semiconductor device 100a shown, a semiconductor unit 200 is disposed at the center of the metal substrate 30 via solder (not shown). It should be noted that the semiconductor unit 200 has the same configuration as semiconductor units 200a and 200b. In this case, the solder on the back side of the semiconductor unit 200, except... Figure 12In addition to regions A1 and A2, regions A3 and A4 contain areas with a higher density of voids such as shrinkage cavities than other regions (stress-relieving regions). That is, when a semiconductor unit 200 is disposed at the center of the metal substrate 30, stress-relieving regions are formed not only on the short sides 31a and 31c of the metal substrate 30, but also on the edges (outer periphery) of the solder on the long sides 31b and 31d. Furthermore, in Figure 12 Semiconductor chips 28a and 28b are also disposed in areas A3 and A4 shown. Therefore, semiconductor chips 28a and 28b are disposed in a low-heat-dissipation area overlapping the stress-relief area on the front side of the ceramic circuit board 21. Consequently, the heat dissipation of semiconductor chips 28a and 28b is reduced, and the semiconductor device 100a may overheat and be damaged.

[0107] Additionally, as another example, regarding Figure 13 and Figure 14 The semiconductor device 100b shown will be described below. Semiconductor device 100b has a sufficiently thin solder layer, similar to semiconductor device 10, and unlike semiconductor device 10, it has no protrusions on the metal substrate 30. In this case, it can also be used with… Figure 4 The same process is followed in the flowchart shown.

[0108] The semiconductor device 100b manufactured by thinning the solders 25a and 25b can achieve improved heat dissipation. However, no stress-relieving region is formed at the edges (outer periphery) of the solders 25a and 25b. Therefore, due to the difference in the coefficients of thermal expansion between the ceramic circuit board 21 and the heat sink 31, stress is generated at the outer periphery of the ceramic circuit board 210 and the outer periphery of the solders 25a and 25b with temperature changes. In particular, the solder thickness is thinner at the edge on the side away from the center line CL1. Therefore, as Figure 14 As shown, such stress may cause cracks CK1, CK2, and other damage caused by peeling in the ceramic substrate 22 and solders 25a, 25b.

[0109] Therefore, the semiconductor device 10 described above includes semiconductor chips 28a and 28b, a metal substrate 30, and a ceramic circuit board 21 bonded to the metal substrate 30 by solder 25a and 25b. The metal substrate 30 is rectangular in shape when viewed from above, and has bonding areas 36a and 36b on its front side. A center line CL1 is provided at the very center of the substrate, parallel to and sandwiched between a pair of opposing short sides 31a and 31c. The ceramic circuit board 21 includes a rectangular ceramic substrate 22 when viewed from above, a circuit pattern 24b formed on the front side of the ceramic substrate 22 and bonded to the semiconductor chips 28a and 28b, and a metal plate 23 formed on the back side of the ceramic substrate 22 and bonded to the bonding areas 36a and 36b by solder 25a and 25b. At this time, the edge portion of solders 25a and 25b on the side away from the center line CL1 has stress-relieving regions 25a1 and 25b1 where the density of voids contained in solders 25a and 25b is higher than that in other regions. In such a semiconductor device 10, low-heat dissipation regions 29a and 29b are provided on the ceramic circuit board 21, which overlap with the stress-relieving regions 25a1 and 25b1 when viewed from above. Therefore, in the semiconductor device 10, semiconductor chips 28a and 28b can be bonded to the ceramic circuit board 21 while avoiding the low-heat dissipation regions 29a and 29b. Therefore, the semiconductor device 10 can reduce the thickness of solders 25a and 25b and suppress damage to the ceramic circuit board 21 and solders 25a and 25b, thereby achieving miniaturization and stable operation at high temperatures.

[0110] The following is for reference Figures 1 to 8 The following describes variations of the solder stress relief region and the corresponding low heat dissipation region in the semiconductor device, corresponding to various configuration patterns of the semiconductor unit 20 disposed on the metal substrate 30. It should be noted that in the following variations, illustrations and explanations of symbols for components not required for the description are omitted.

[0111] [Variation Example 1]

[0112] use Figure 15 The semiconductor device of Modified Example 1 will be described. Figure 15 This is a top view of the semiconductor device according to Embodiment 1, Modification 1. In Modification 1, it is... Figure 1 In the semiconductor device 10 shown, multiple semiconductor units 20a and 20b are arranged symmetrically with respect to the center line CL1 along the long sides 31b and 31d of the metal substrate 30, via solder 25a and 25b (not shown). For example, Figure 15The semiconductor device 10a shown in (A) has two semiconductor units 20a and 20b arranged symmetrically with respect to the center line CL1 on the metal substrate 30, for a total of four semiconductor units 20a and 20b. Furthermore, Figure 15 The semiconductor device 10b shown in (B) has three semiconductor units 20a and 20b arranged symmetrically with respect to the center line CL1 on the metal substrate 30, for a total of six semiconductor units 20a and 20b.

[0113] In the case where multiple semiconductor units 20a and 20b are arranged symmetrically with respect to the center line CL1 along the long sides 31b and 31d of the metal base plate 30 via solder 25a and 25b, the solder of the semiconductor units 20a and 20b... Figures 1-3 Similarly, stress-relieving regions 25a1–25a3 and 25b1–25b3 are also included. Correspondingly, low-heat dissipation regions 29a and 29b are provided on the front side of semiconductor units 20a and 20b. However, if multiple semiconductor units 20a and 20b are arranged symmetrically with respect to the center line CL1 along the long sides 31b and 31d of the metal base plate 30, the width of the stress-relieving regions 25a1 and 25b1 (along the long side direction of the metal base plate 30) increases as the semiconductor units 20a and 20b move away from the center line CL1. Accompanyingly, the width of the short side portions 29a1 and 29b1 included in the low-heat dissipation regions 29a and 29b also increases.

[0114] The manufacturing of semiconductor devices 10a and 10b is as follows: Figure 9 As explained, the ceramic circuit board 21 is bonded to the metal base plate 30 via solder 25a and 25b. At this time, the metal base plate 30 is warped in a downward convex manner. Therefore, the further away from the center line CL1 of the metal base plate 30, the greater the tilt of the metal base plate 30. That is, the further away from the center line CL1 of the metal base plate 30, the greater the flow of molten solder 27a1 and 27b1 towards the center line CL1. Therefore, the volume of the edge portion of the molten solder 27a1 and 27b1 on the side away from the center line CL1 decreases as it moves further away from the center line CL1.

[0115] Furthermore, to solidify the molten solder 27a1 and 27b1, cooling is performed from the center of the back side of the metal base plate 30, which is warped in a downwardly convex manner. Therefore, the further away from the centerline CL1 of the metal base plate 30, the slower the cooling. That is, the further away the molten solder 27a1 and 27b1 are from the centerline CL1 of the metal base plate 30, the slower the volume shrinkage occurs. Therefore, for the molten solder 27a1 and 27b1 far from the centerline CL1, the volume of the edge portion on the side far from the centerline CL1 is smaller, and the volume shrinkage is slower. Additionally, as described above, through the protrusion 35a of the metal base plate 30, a predetermined gap is provided between the heat sink 31 of the metal base plate 30 and the ceramic circuit board 21 at this position on the side of the molten solder 27a1 far from the centerline CL1. Therefore, the further away the molten solder 27a1 and 27b1 are from the centerline CL1, the longer the shrinkage cavity is formed at the edge portion far from the centerline CL1.

[0116] For this reason, when multiple semiconductor cells 20a and 20b are arranged symmetrically with respect to the center line CL1 along the long sides 31b and 31d of the metal substrate 30 via solder 25a and 25b, the width of the stress-relieving regions 25a1 and 25b1 of the solder 25a and 25b (along the long side direction of the metal substrate 30) increases as they move away from the center line CL1. Therefore, the width of the short side portions 29a1 and 29b1 of the low-heat dissipation regions 29a and 29b also increases.

[0117] [Variation Example 2]

[0118] use Figure 16 The semiconductor device 10c of Modified Example 2 will be described. Figure 16 This is a top view of the semiconductor device according to Embodiment 2. In Embodiment 2, for the semiconductor device in… Figure 1 The semiconductor device 10 shown will be described in the case where semiconductor units 20 are arranged symmetrically with respect to the center lines CL1 and CL2. For example, in Figure 16 In the semiconductor device 10c shown, semiconductor units 20a and 20b are bonded to the metal substrate 30 in two rows and two columns with solder 25a and 25b in a manner that is linearly symmetrical about the center lines CL1 and CL2, respectively.

[0119] During the manufacture of the semiconductor device 10c, in the metal substrate 30, which has semiconductor units 20a and 20b arranged in two rows and two columns and warped downwards, due to the reasons described above, voids such as shrinkage cavities and cracks occur in the solder 25a and 25b at the center point O where the center lines CL1 and CL2 intersect. Therefore, the semiconductor units 20a and 20b in the first row have short side portions 29a1 and 29b1 and long side portions 29a2 and 29b2 corresponding to stress-relieving areas (not shown) at their edges away from the center point O, where low-heat dissipation areas 29a and 29b are provided. The semiconductor units 20a and 20b in the second row also have short side portions 29a1 and 29b1 and long side portions 29a3 and 29b3 corresponding to stress-relieving areas (not shown) at their edges away from the center point O, where low-heat dissipation areas 29a and 29b are provided.

[0120] [Variations 3 and 4]

[0121] use Figure 17 The semiconductor devices 10d and 10e of variations 3 and 4 will be described. Figure 17 These are top views of the semiconductor devices according to variations 3 and 4 of the embodiments. It should be noted that... Figure 17 (A) represents the semiconductor device 10d of variation example 3. Figure 17 (B) represents the semiconductor device 10e of variation 4.

[0122] In Variation Example 3, the case where a semiconductor unit is arranged centered on the center line CL1 on the metal base plate 30 will be described (and...). Figure 12 (The reference example shown corresponds to this). Figure 17 The semiconductor device 10d shown in (A) has a metal substrate 30 and a semiconductor unit 20c bonded to the metal substrate 30 by solder (not shown).

[0123] As in Figure 12 As explained, in the solder of the semiconductor device 10d, voids such as shrinkage cavities and cracks were observed not only at the pair of edges sandwiching the center line CL1, but also at the pair of edges orthogonal to these edges. Therefore, the semiconductor unit 20c is provided with an O-shaped low heat dissipation region 29c corresponding to the stress relief region (not shown) along the outer periphery of the semiconductor unit 20c. The low heat dissipation region 29c includes short side portions 29c1 and 29c4 and long side portions 29c2 and 29c3 provided on the outer periphery of the semiconductor unit 20c.

[0124] Therefore, the circuit patterns 24b and 24c of the ceramic circuit substrate 21 included in the semiconductor unit 20c have the same shape and extend to the edge of the ceramic substrate 22 (the side opposite the long side of the metal base plate 30), and include areas (non-mounted areas) that overlap with the short side portions 29c1 and 29c4 of the low heat dissipation area 29c. The semiconductor chips 28a and 28b are frontally bonded to the circuit patterns 24b and 24c except for the short side portions 29c1 and 29c4 of the low heat dissipation area 29c.

[0125] In Modification 4, the semiconductor unit 20c of Modification 3 is arranged at the center of the metal base plate 30, and the semiconductor units 20a and 20b are arranged on both sides of the semiconductor unit 20c of the metal base plate 30 in a linearly symmetrical manner with respect to the center line CL1, and are connected by solder 25a and 25b (not shown).

[0126] Figure 17 The semiconductor device 10e shown in (B) includes a metal substrate 30, semiconductor units 20c arranged around the center line CL1 of the metal substrate 30, and adjacent bonding regions of semiconductor units 20a and 20b arranged on both sides of the semiconductor units 20c by solder 25a and 25b, which are linearly symmetrical with respect to the center line CL1. In this semiconductor device 10e, the semiconductor units 20c are arranged around the center line CL1 of the metal substrate 30. Therefore, in this case, as in the case of modified example 3, voids such as shrinkage cavities and cracks are found not only at the pair of edges sandwiching the center line CL1, but also at the pair of edges orthogonal to the pair of edges. Therefore, the semiconductor unit 20c is provided with an O-shaped low heat dissipation region 29c corresponding to the stress relief region (not shown) along the outer periphery of the semiconductor unit 20c.

[0127] In addition, similar to the case of Modified Example 1, the ceramic circuit board 21 of semiconductor units 20a and 20b has low heat dissipation regions 29a and 29b corresponding to stress relief regions (not shown) at the edges of solder 25a and 25b away from the center line CL1.

[0128] [Variation Example 5]

[0129] use Figure 18 The semiconductor device of Modified Example 5 will be described. Figure 18 This is a top view of the semiconductor device according to Embodiment 5. In Embodiment 5, the case of semiconductor cells 20a, 20c, and 20b of Embodiment 4 arranged in two rows will be described. Figure 18The semiconductor device 10f shown includes a metal substrate 30 and semiconductor units 20a, 20c, and 20b of Modified Example 4, which are arranged in two rows on the metal substrate 30 by solder.

[0130] In this semiconductor device 10f, similar to Modification 2, firstly, in the metal substrate 30 with two rows and three columns of semiconductor cells 20a, 20c, and 20b, voids such as shrinkage cavities and cracks are identified in the solder at the center point O, away from the intersection of center lines CL1 and CL2. Therefore, the semiconductor cells 20a, 20c, and 20b in the first row have low heat dissipation regions 29a, 29c, and 29b (short side portions 29a1, 29b1 and long side portions 29a2, 29c2, 29b2) corresponding to the stress relief region (not shown) at their edges away from the center point O. The semiconductor cells 20a, 20c, and 20b in the second row also have low heat dissipation regions 29a, 29c, and 29b (short side portions 29a1, 29b1 and long side portions 29a3, 29c3, 29b3) corresponding to the stress relief region (not shown) at their edges away from the center point O.

[0131] Furthermore, as explained in Modification 4, the solder of the semiconductor cell 20c, which is arranged with the center line CL1 of the metal substrate 30 as its center, includes stress-relieving regions (not shown) at a pair of edges sandwiching the center line CL1. Therefore, the ceramic circuit board 21 of the semiconductor cell 20c is provided with short side portions 29c1 and 29c4 of a low heat dissipation region 29c corresponding to the stress-relieving region.

[0132] In the semiconductor devices 10a-10f of the above-described modifications 1-5, it is also possible to avoid the low heat dissipation areas 29a, 29b, and 29c and bond the semiconductor chips 28a and 28b to the ceramic circuit board 21, reduce the thickness of the solder, and suppress the damage to the ceramic circuit board 21 and the solders 25a and 25b, thereby achieving miniaturization and stable operation at high temperatures.

[0133] The above only illustrates the principles of the present invention. Furthermore, those skilled in the art can make various modifications and alterations, and the present invention is not limited to the exact configurations and applications shown and described above. All corresponding modifications and equivalents are considered to be within the scope of the present invention as defined by the appended claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, have: First semiconductor chip; A metal base plate, rectangular in shape when viewed from above, has a joint area on its front side and a first center line at its center, parallel to and sandwiched between a pair of opposing first sides; and The first insulating circuit substrate includes a first insulating plate that is rectangular in shape when viewed from above, a first circuit pattern formed on the front side of the first insulating plate and bonded to the first semiconductor chip, and a first metal plate formed on the back side of the first insulating plate and bonded to the bonding area by a first bonding member. The first joining component joins the metal base plate to the first metal plate and forms a weld leg that extends outward from the outer peripheral end of the first metal plate in a downward-sloping shape. A portion of the first edge on the side away from the first center line has a first stress-relieving region. In the first stress-relieving region, the density of voids contained in the first joining component is higher than the density of voids contained in other regions of the first joining component. The metal base plate is provided with multiple rows of the aforementioned joint areas along a pair of second sides that are orthogonal to and opposite to the pair of first sides, symmetrically arranged with respect to the first center line. The first insulating circuit board is bonded to the multiple rows of bonding regions respectively via the first bonding member. In adjacent first insulating circuit boards, the width of the first stress relief region parallel to the second side is wider on the side of the first insulating circuit board farther from the first center line than on the side of the first insulating circuit board closer to the first center line.

2. The semiconductor device according to claim 1, characterized in that, The first semiconductor chip, when viewed from above, is bonded to the first circuit pattern on the front side of the first insulating circuit substrate, excluding the area overlapping with the first stress relief region.

3. The semiconductor device according to claim 1 or 2, characterized in that, The first circuit pattern includes a region that does not overlap with the first stress-relieving region of the first insulating plate when viewed from above, and a region extending from the non-overlapping region to the first edge and overlapping with the first stress-relieving region. The first semiconductor chip is bonded to the non-overlapping region and not to the overlapping region.

4. The semiconductor device according to claim 1, characterized in that, When viewed from above, other circuit patterns are formed in the area of ​​the first insulating plate that overlaps with the first stress-relieving area.

5. The semiconductor device according to claim 1, characterized in that, The metal base plate is also provided with a second center line, which is orthogonal to the pair of first sides, parallel to the pair of opposite second sides, and located in the exact center between the pair of second sides. The first joining member also has a second stress-relieving region on a second edge portion on the side away from the second center line. In the second stress-relieving region, the density of voids contained in the first joining member is higher than the density of voids contained in the first joining member in other regions besides the first stress-relieving region.

6. The semiconductor device according to claim 5, characterized in that, The first insulating circuit board is disposed on the metal base plate, and the second center line is located at the center of the first insulating circuit board. The first engaging member has a second stress-relieving region at a pair of opposing second edge portions, which are parallel to the pair of second sides.

7. The semiconductor device according to claim 5 or 6, characterized in that, At least one of the first stress relief region and the second stress relief region includes a gap that extends into the interior from the first edge portion and the second edge portion of the first engaging member.

8. The semiconductor device according to claim 1, characterized in that, The thickness of the first edge side of the first joining member is thinner than the thickness of the first centerline side.

9. The semiconductor device according to claim 1, characterized in that, At least one of the metal base plate and the first insulating circuit board is warped. The warping of the metal base plate is centered on the first center line, with the back side facing down and convex downwards. The warping of the first insulating circuit board is centered on the position of the first center line, with the front side facing upward and in an upward convex manner.

10. The semiconductor device according to claim 1, characterized in that, The first engagement member does not include the first stress relief region on the edge portion of the side near the first centerline.

11. The semiconductor device according to claim 1 or 10, characterized in that, The metal base plate is also provided with a second center line, which is orthogonal to the pair of first sides, parallel to the pair of second sides, and located at the exact center between the pair of second sides. The multi-column joint area is arranged symmetrically in multiple rows along the pair of first sides with respect to the second center line. The first insulating circuit board is bonded to the multiple rows of bonding regions respectively via the first bonding member. The first joining member has a second stress-relieving region at one edge on the side away from the second center line. In the second stress-relieving region, the density of voids contained in the first joining member is higher than the density of voids contained in the first joining member in other regions besides the first stress-relieving region.

12. The semiconductor device according to claim 1, characterized in that, The first bonding component is solder.

13. The semiconductor device according to claim 1, characterized in that, Protrusions integrally formed with the metal base plate are formed at the corners of the joint area of ​​the metal base plate.

14. A semiconductor device, characterized in that, have: First semiconductor chip; A metal base plate, rectangular in shape when viewed from above, has a joint area on its front side and a first center line at its center, parallel to and sandwiched between a pair of opposing first sides; and The first insulating circuit substrate includes a first insulating plate that is rectangular in shape when viewed from above, a first circuit pattern formed on the front side of the first insulating plate and bonded to the first semiconductor chip, and a first metal plate formed on the back side of the first insulating plate and bonded to the bonding area by a first bonding member. The first joining component joins the metal base plate to the first metal plate and forms a weld leg that extends outward from the outer peripheral end of the first metal plate in a downward-sloping shape. A portion of the first edge on the side away from the first center line has a first stress-relieving region. In the first stress-relieving region, the density of voids contained in the first joining component is higher than the density of voids contained in other regions of the first joining component. A joint area is provided at the center of the metal base plate, and the first joint member includes the first stress-relieving area along its entire circumferential edge, which includes an edge portion. A second insulating circuit substrate, to which a second semiconductor chip is bonded, sandwiches the bonding region of the metal base plate and is bonded to an adjacent bonding region by a second bonding member. The adjacent bonding regions are arranged symmetrically with respect to the first center line along a pair of second sides orthogonal to and opposite to the pair of first sides. The second insulating circuit board includes: A second insulating plate, which is rectangular when viewed from above; a second circuit pattern, formed on the front side of the second insulating plate and bonded to the second semiconductor chip; a second metal plate, formed on the back side of the second insulating plate and bonded to the adjacent bonding area by a second bonding member. The second joining component joins the metal base plate and the second metal plate and forms a weld foot that extends outward from the outer peripheral end of the second metal plate in a downward-sloping shape. A portion of an edge portion on the side of the second insulating plate away from the first center line has a second stress relief region. In the second stress relief region, the density of voids contained in the second joining component is higher than the density of voids contained in the second joining component in other regions.

15. The semiconductor device according to claim 14, characterized in that, The first semiconductor chip, when viewed from above, is bonded to the first circuit pattern on the front side of the first insulating circuit substrate, excluding the area overlapping with the first stress relief region.

16. The semiconductor device according to claim 14 or 15, characterized in that, The first circuit pattern includes a region that does not overlap with the first stress-relieving region of the first insulating plate when viewed from above, and a region extending from the non-overlapping region to the first edge and overlapping with the first stress-relieving region. The first semiconductor chip is bonded to the non-overlapping region and not to the overlapping region.

17. The semiconductor device according to claim 14, characterized in that, When viewed from above, other circuit patterns are formed in the area of ​​the first insulating plate that overlaps with the first stress-relieving area.

18. The semiconductor device according to claim 14, characterized in that, The metal base plate is also provided with a second center line, which is orthogonal to the pair of first sides, parallel to the pair of opposite second sides, and located in the exact center between the pair of second sides. The first joining member also has a second stress-relieving region on a second edge portion on the side away from the second center line. In the second stress-relieving region, the density of voids contained in the first joining member is higher than the density of voids contained in the first joining member in other regions besides the first stress-relieving region.

19. The semiconductor device according to claim 18, characterized in that, The first insulating circuit board is disposed on the metal base plate, and the second center line is located at the center of the first insulating circuit board. The first engaging member has a second stress-relieving region at a pair of opposing second edge portions, which are parallel to the pair of second sides.

20. The semiconductor device according to claim 18 or 19, characterized in that, At least one of the first stress relief region and the second stress relief region includes a gap that extends into the interior from the first edge portion and the second edge portion of the first engaging member.

21. The semiconductor device according to claim 14, characterized in that, The thickness of the first edge side of the first joining member is thinner than the thickness of the first centerline side.

22. The semiconductor device according to claim 14, characterized in that, At least one of the metal base plate and the first insulating circuit board is warped. The warping of the metal base plate is centered on the first center line, with the back side facing down and convex downwards. The warping of the first insulating circuit board is centered on the position of the first center line, with the front side facing upward and in an upward convex manner.

23. The semiconductor device according to claim 14, characterized in that, The first bonding component is solder.

24. The semiconductor device according to claim 14, characterized in that, Protrusions integrally formed with the metal base plate are formed at the corners of the joint area of ​​the metal base plate.

25. A semiconductor device, characterized in that, have: First semiconductor chip; A metal base plate, rectangular in shape when viewed from above, has a joint area on its front side and a first center line at its center, parallel to and sandwiched between a pair of opposing first sides; and The first insulating circuit substrate includes a first insulating plate that is rectangular in shape when viewed from above, a first circuit pattern formed on the front side of the first insulating plate and bonded to the first semiconductor chip, and a first metal plate formed on the back side of the first insulating plate and bonded to the bonding area by a first bonding member. The first joining component joins the metal base plate to the first metal plate and forms a weld leg that extends outward from the outer peripheral end of the first metal plate in a downward-sloping shape. A portion of the first edge on the side away from the first center line has a first stress-relieving region. In the first stress-relieving region, the density of voids contained in the first joining component is higher than the density of voids contained in other regions of the first joining component. The metal base plate is also provided with a second center line, which is orthogonal to the pair of first sides, parallel to the pair of opposite second sides, and located in the exact center between the pair of second sides. A joining area is provided at the center of the metal base plate. Adjacent joining areas are arranged symmetrically along the pair of second sides relative to the first center line. A row of the joining areas and the adjacent joining areas are arranged symmetrically along the pair of first sides relative to the second center line. The first insulating circuit board is bonded to multiple rows of bonding areas by the first bonding member. The first bonding member has the first stress-relieving area on one edge portion opposite to the first center line and on one edge portion away from the second center line. A second insulating circuit board to which a second semiconductor chip is bonded is bonded to the adjacent bonding regions of the multiple rows via a second bonding component. The second insulating circuit board includes: A second insulating plate, which is rectangular when viewed from above; a second circuit pattern, formed on the front side of the second insulating plate and bonded to the second semiconductor chip; a second metal plate, formed on the back side of the second insulating plate and bonded to the adjacent bonding area by a second bonding member. The second joining component joins the metal base plate and the second metal plate, and forms a weld foot that extends outward from the outer peripheral end of the second metal plate in a downward-sloping shape. It also has a second stress relief region on a portion of one edge away from the first center line and a portion of another edge away from the second center line. In the second stress relief region, the density of voids contained in the second joining component is higher than the density of voids contained in the second joining component in other regions.

26. The semiconductor device according to claim 25, characterized in that, The first semiconductor chip, when viewed from above, is bonded to the first circuit pattern on the front side of the first insulating circuit substrate, excluding the area overlapping with the first stress relief region.

27. The semiconductor device according to claim 25 or 26, characterized in that, The first circuit pattern includes a region that does not overlap with the first stress-relieving region of the first insulating plate when viewed from above, and a region extending from the non-overlapping region to the first edge and overlapping with the first stress-relieving region. The first semiconductor chip is bonded to the non-overlapping region and not to the overlapping region.

28. The semiconductor device according to claim 25, characterized in that, When viewed from above, other circuit patterns are formed in the area of ​​the first insulating plate that overlaps with the first stress-relieving area.

29. The semiconductor device according to claim 25, characterized in that, The metal base plate is also provided with a second center line, which is orthogonal to the pair of first sides, parallel to the pair of opposite second sides, and located in the exact center between the pair of second sides. The first joining member also has a second stress-relieving region on a second edge portion on the side away from the second center line. In the second stress-relieving region, the density of voids contained in the first joining member is higher than the density of voids contained in the first joining member in other regions besides the first stress-relieving region.

30. The semiconductor device according to claim 29, characterized in that, The first insulating circuit board is disposed on the metal base plate, and the second center line is located at the center of the first insulating circuit board. The first engaging member has a second stress-relieving region at a pair of opposing second edge portions, which are parallel to the pair of second sides.

31. The semiconductor device according to claim 29 or 30, characterized in that, At least one of the first stress relief region and the second stress relief region includes a gap that extends into the interior from the first edge portion and the second edge portion of the first engaging member.

32. The semiconductor device according to claim 25, characterized in that, The thickness of the first edge side of the first joining member is thinner than the thickness of the first centerline side.

33. The semiconductor device according to claim 25, characterized in that, At least one of the metal base plate and the first insulating circuit board is warped. The warping of the metal base plate is centered on the first center line, with the back side facing down and convex downwards. The warping of the first insulating circuit board is centered on the position of the first center line, with the front side facing upward and in an upward convex manner.

34. The semiconductor device according to claim 25, characterized in that, The first bonding component is solder.

35. The semiconductor device according to claim 25, characterized in that, Protrusions integrally formed with the metal base plate are formed at the corners of the joint area of ​​the metal base plate.

36. A method for manufacturing a semiconductor device, characterized in that, A method for manufacturing a semiconductor device according to any one of claims 1, 14, and 25, the method comprising: The preparation process includes preparing a metal base plate, a semiconductor chip, and an insulating circuit board. The metal base plate is rectangular in shape when viewed from above, and has a bonding area on its front side. A first center line is set at the center of the base plate, which is parallel to and sandwiched between a pair of opposing first sides. The insulating circuit board includes an insulating plate that is rectangular in shape when viewed from above, a circuit pattern formed on the front side of the insulating plate, and a metal plate formed on the back side of the insulating plate. In the mounting process, the insulating circuit board is mounted in the bonding area of ​​the metal base plate via a bonding plate component, and the semiconductor chip is mounted on the circuit pattern on the front side of the insulating circuit board along an edge portion on the side away from the first center line, in an area other than a predetermined range from the edge portion. In the heating process, the metal base plate, the bonding plate component, the insulating circuit board, and the semiconductor chip are heated to melt the bonding plate component into a molten bonding component; and In the cooling process, the metal base plate, the fusion bonding component, the insulating circuit board, and the semiconductor chip are cooled. The bonding component, formed by the solidification of the fusion bonding component, bonds the insulating circuit board to the metal base plate. The bonding component joins the metal base plate and the metal plate and forms a solder foot that extends outward from the outer peripheral end of the metal plate in a downward-sloping shape. A portion of the area that overlaps with the predetermined range when the bonding component is viewed from above creates a stress-relieving region where the density of voids contained in the bonding component is higher than that in other areas of the bonding component.

37. The method for manufacturing a semiconductor device according to claim 36, characterized in that, The metal base plate prepared in the preparation process has its back side facing down and is warped so that the center of the back side bulges downward. When the joining plate component is melted by the heating process, the metal base plate moves away from the center and is positioned higher than the center.

38. The method for manufacturing a semiconductor device according to claim 37, characterized in that, In the cooling process, after the heating process, the metal substrate on which the insulating circuit board and the semiconductor chip are stacked is placed on a flat cooling plate, and cooling is performed from the center of the metal substrate.

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