Display panel and manufacturing method thereof, and display device

Abstract

The present application discloses a display panel and a manufacturing method thereof, and a display device, which relate to the field of display technology. The display panel includes a blocking structure, at least one first power line, and a row driving circuit that overlap each other, thereby effectively reducing the total width of each structure located in the peripheral area, thereby reducing the width of the display panel frame, and facilitating the realization of a narrow-frame display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for preparing the same, and a display device. Background Art

[0002] The display panel generally has a display area and a peripheral area surrounding the display area. The display panel includes a plurality of pixel units located in the display area, a driving circuit located in the peripheral area for providing a driving signal to the pixel units, and a power supply line located in the peripheral area for providing a negative power supply signal to the cathode layer of the display panel, which is generally called a VSS line.

[0003] However, since the driving circuit and the VSS wiring are both located in the peripheral area, it is not conducive to achieving a narrow frame of the display panel. Summary of the invention

[0004] The present application provides a display panel and a manufacturing method thereof, and a display device, which can solve the problem in the related art that the driving circuit and VSS wiring are located in the peripheral area, which is not conducive to the realization of a narrow frame of the display panel. The technical solution is as follows:

[0005] In one aspect, a display panel is provided, the display panel comprising:

[0006] A base substrate, the base substrate having a display area and a peripheral area surrounding the display area;

[0007] A plurality of pixel units, located in the display area;

[0008] A blocking structure, located in the peripheral area and surrounding the plurality of pixel units;

[0009] At least one first power line is located in the peripheral area, the at least one first power line includes a first portion and a second portion, the first portion is located on a side of the blocking structure away from the plurality of pixel units and is used to receive a first power signal, the second portion surrounds the plurality of pixel units and is electrically connected to the first portion and the first electrode layer in the plurality of pixel units, respectively;

[0010] and a row driving circuit, located in the peripheral area, the row driving circuit being electrically connected to the plurality of pixel units and configured to provide driving signals to the plurality of pixel units;

[0011] Wherein, the orthographic projections of any two of the following structures on the substrate at least partially overlap: the blocking structure, the at least one first power line, and the row driving circuit.

[0012] Optionally, the peripheral region includes: a first region and a second region arranged oppositely and in parallel, and a third region and a fourth region arranged oppositely and in parallel, wherein an extension direction of the first region is perpendicular to an extension direction of the third region;

[0013] The first portion is located in the first area, and the second portion is located in the second area, the third area, and the fourth area.

[0014] Optionally, the row driving circuit includes: a first sub-driving circuit and a second sub-driving circuit, the first sub-driving circuit is located in the third area, and the second sub-driving circuit is located in the fourth area.

[0015] Optionally, the first sub-driving circuit and the second sub-driving circuit both include: a light-emitting control driving circuit, a first type of driving circuit and a second type of driving circuit, the light-emitting control driving circuit is used to provide a light-emitting control signal, and the first type of driving circuit and the second type of driving circuit are both used to provide a scanning signal;

[0016] The orthographic projection of the first power line on the base substrate at least partially overlaps with the orthographic projection of the light emitting control driving circuit on the base substrate, and the orthographic projection of the blocking structure on the base substrate at least partially overlaps with the orthographic projection of the light emitting control driving circuit on the base substrate.

[0017] Optionally, the blocking structure comprises: a first blocking dam and a second blocking dam;

[0018] The first barrier dam is closer to the plurality of pixel units than the second barrier dam, and a thickness of the first barrier dam is smaller than a thickness of the second barrier dam.

[0019] Optionally, the first barrier dam comprises: a first pattern and a second pattern sequentially stacked in a direction away from the substrate;

[0020] The second blocking dam comprises: a third pattern, a fourth pattern and a fifth pattern stacked in sequence in a direction away from the base substrate;

[0021] The first pattern and the fourth pattern are located on a pixel defining layer of the display panel, the second pattern and the fifth pattern are located on a supporting layer of the display panel, and the third pattern is located on a first planar layer of the display panel.

[0022] Optionally, the first power line includes: two first parts and one second part;

[0023] The two first parts are symmetrically arranged with the axis of the substrate as the axis, one end of the second part is connected to one of the first parts, and the other end of the second part is connected to another first part, wherein the axis is parallel to the column direction of the multiple pixel units.

[0024] Optionally, the display panel further comprises: at least one second power line located in the peripheral area;

[0025] One end of the at least one second power line is located at a side of the blocking structure away from the plurality of pixel units and is used to receive a second power signal, and the other end is located at a side of the blocking structure close to the plurality of pixel units and is electrically connected to the plurality of pixel units;

[0026] The orthographic projection of the at least one second power line on the base substrate at least partially overlaps with the orthographic projection of the blocking structure on the base substrate.

[0027] Optionally, the second power line includes a third portion, two fourth portions, a fifth portion and two sixth portions, the third portion is located on a side of the blocking structure close to the plurality of pixel units and electrically connected to the plurality of pixel units, the two fourth portions are both located on a side of the third portion away from the plurality of pixel units and electrically connected to the third portion, the fifth portion is located on a side of the two fourth portions away from the plurality of pixel units and electrically connected to the two fourth portions, the two sixth portions are located on a side of the blocking structure away from the plurality of pixel units, and are used to receive a second power signal, and the two sixth portions are both electrically connected to the fifth portion;

[0028] The two fourth parts are symmetrically arranged with the axis of the base substrate as an axis, and the two sixth parts are symmetrically arranged with the axis of the base substrate as an axis, and the axis is parallel to the column direction of the plurality of pixel units.

[0029] Optionally, the first power line includes: two first parts, the two first parts are symmetrically arranged with the axis as an axis;

[0030] The distance between the sixth portion and the first portion, which are located on the same side of the axis, is smaller than the distance between the sixth portion and the axis.

[0031] Optionally, the third portion and the fifth portion both extend along a row direction, and the two fourth portions and the two sixth portions both extend along a column direction.

[0032] Optionally, an orthographic projection of each of the fourth portions on the substrate at least partially overlaps with an orthographic projection of the blocking structure on the substrate.

[0033] Optionally, each of the pixel units comprises: a thin film transistor and a light emitting unit stacked in sequence in a direction away from the substrate;

[0034] The thin film transistor comprises: a first buffer layer, a first active pattern, a first gate insulating layer, a first gate pattern, a second gate insulating layer, a second buffer layer, an interlayer dielectric layer, and a source and a drain electrode stacked in sequence in a direction away from the base substrate, wherein the source and the drain electrode comprise a source electrode and a drain electrode arranged at intervals, and the source electrode and the drain electrode are both electrically connected to the first active pattern;

[0035] The light-emitting unit comprises: an electrode pattern, a light-emitting pattern and the first electrode layer which are sequentially stacked in a direction away from the base substrate; the electrode pattern is located in the second electrode layer and connected to the drain.

[0036] Optionally, the row driving circuit includes: the first buffer layer, the second active pattern, the first gate insulating layer, the second gate pattern, the second gate insulating layer, the third gate pattern, the second buffer layer, the interlayer dielectric layer, and a connecting layer, which are sequentially stacked in a direction away from the base substrate, and the connecting layer is electrically connected to the first gate pattern;

[0037] The first active pattern and the second active pattern are located in the same layer, the first gate pattern and the second gate pattern are located in the same layer, and the source and drain and the connection layer are located in the same layer.

[0038] Optionally, the display panel further includes: a passivation layer, a first planar layer and a second planar layer;

[0039] The passivation layer is located on a side of the source and drain away from the substrate, the second flat layer is located on a side of the passivation layer away from the substrate, the at least one first power line is located on a side of the second flat layer away from the substrate, and the first flat layer is located on a side of the at least one first power line away from the substrate.

[0040] Optionally, the target portion of the at least one first power line has at least one opening;

[0041] The orthographic projection of the target portion on the substrate overlaps with the orthographic projection of the blocking structure on the substrate.

[0042] Optionally, the display panel further comprises: a power driving circuit, wherein the power driving circuit is located in the peripheral area and located on a side of the first portion away from the blocking structure;

[0043] The power driving circuit is electrically connected to the first part, and is used to provide the first power signal to the at least one first power line.

[0044] Optionally, the display panel further includes: a packaging film layer;

[0045] The packaging film layer is located on a side of the plurality of pixel units away from the substrate, and the packaging film layer covers the area surrounded by the blocking structure.

[0046] In another aspect, a method for preparing a display panel is provided, the method comprising:

[0047] Providing a base substrate, the base substrate having a display area and a peripheral area surrounding the display area;

[0048] Forming a plurality of pixel units in the display area, and forming a blocking structure, at least one first power line and a row driving circuit in the peripheral area;

[0049] The blocking structure surrounds the plurality of pixel units; the at least one first power line includes a first portion and a second portion, the first portion is located on a side of the blocking structure away from the plurality of pixel units, and is used to receive a first power signal, and the second portion surrounds the plurality of pixel units and is electrically connected to the first portion and the first electrode layer in the plurality of pixel units, respectively; the row driving circuit is electrically connected to the plurality of pixel units, and is used to provide driving signals to the plurality of pixel units;

[0050] Orthographic projections of any two of the following structures on the substrate at least partially overlap: the blocking structure, the at least one first power line, and the row driving circuit.

[0051] In yet another aspect, a display device is provided, the display device comprising: a power supply component and the display panel as described in the above aspect;

[0052] The power supply component is used to supply power to the display panel.

[0053] The beneficial effects of the technical solution provided by this application include at least:

[0054] The present application provides a display panel and a method for preparing the same, and a display device. The display panel includes a blocking structure, at least one first power line, and a row driving circuit that overlap each other, thereby effectively reducing the total width of each structure located in the peripheral area, thereby reducing the width of the display panel frame, and facilitating the realization of a narrow-frame display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0056] Figure 1 is a structural schematic diagram of a display panel provided in an embodiment of the present application;

[0057] Figure 2 It is a structural schematic diagram of a substrate provided in an embodiment of the present application;

[0058] Figure 3 is a structural schematic diagram of another display panel provided in an embodiment of the present application;

[0059] Figure 4 is an equivalent circuit diagram of a pixel circuit provided in an embodiment of the present application;

[0060] Figure 5 is an equivalent circuit diagram of a light emitting control circuit provided in an embodiment of the present application;

[0061] Figure 6 is a timing diagram of a light emitting control circuit provided in an embodiment of the present application;

[0062] Figure 7 yes Figure 1 A cross-sectional view of the display panel along the BB direction is shown;

[0063] Figure 8 is a structural schematic diagram of another display panel provided in an embodiment of the present application;

[0064] Fig. 9 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0065] Fig.10 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0066] Fig.11 is a schematic diagram of a first power line and a blocking structure provided in an embodiment of the present application;

[0067] Fig.12 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0068] Fig.13 is a flow chart of a method for preparing a display panel provided in an embodiment of the present application;

[0069] Fig.14is a flow chart of another method for preparing a display panel provided in an embodiment of the present application;

[0070] Fig.15 is a schematic diagram of an active layer provided in an embodiment of the present application;

[0071] Fig.16 is a schematic diagram of a first gate layer provided in an embodiment of the present application;

[0072] Fig.17 is a schematic diagram of forming a first gate layer provided in an embodiment of the present application;

[0073] Fig.18 is a schematic diagram of a second gate layer provided in an embodiment of the present application;

[0074] Fig.19 is a schematic diagram of forming a second gate layer provided in an embodiment of the present application;

[0075] Fig. 20 is a schematic diagram of an interlayer dielectric layer provided in an embodiment of the present application;

[0076] Fig.21 is a schematic diagram of forming an interlayer dielectric layer provided by an embodiment of the present application;

[0077] Fig. 22 is a schematic diagram of a source and drain layer provided in an embodiment of the present application;

[0078] Fig.23 is a schematic diagram of forming a source and drain layer provided in an embodiment of the present application;

[0079] Fig.24 is a schematic diagram of a passivation layer provided in an embodiment of the present application;

[0080] Fig.25 is a schematic diagram of forming a passivation layer provided in an embodiment of the present application;

[0081] Fig.26 is a schematic diagram of a first power line provided in an embodiment of the present application;

[0082] Fig. 27 is a schematic diagram of forming a first power line provided by an embodiment of the present application;

[0083] Fig.28 is a schematic diagram of a first flat layer provided in an embodiment of the present application;

[0084] Fig.29 is a schematic diagram of forming a first flat layer provided in an embodiment of the present application;

[0085] Fig.30is a schematic diagram of a pixel definition layer provided in an embodiment of the present application;

[0086] Fig.31 is a schematic diagram of forming a pixel defining layer provided in an embodiment of the present application;

[0087] Fig.32 is a schematic diagram of a support layer provided in an embodiment of the present application;

[0088] Fig.33 is a schematic diagram of forming a support layer provided in an embodiment of the present application;

[0089] Fig.34 It is a structural schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0090] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0091] The terms used in the implementation mode of the present application are only used to explain the embodiments of the present application, and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the implementation mode of the present application should be the common meanings understood by people with ordinary skills in the field to which the present application belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limit, but indicate that there is at least one. Words such as "include" or "include" and similar words mean that the elements or objects appearing in front of "include" or "include" include the elements or objects listed after "include" or "include" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0092] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application. Figure 1 It can be seen that the display panel 10 includes: a base substrate 101 , a plurality of pixel units 102 , a blocking structure 103 , at least one first power line 104 and a row driving circuit (gate driver on array, GOA) 105 .

[0093] Figure 2Schematic diagram of a substrate provided by an embodiment of the present application. Figure 2 It can be seen that the base substrate 101 may have a display area 101a and a peripheral area 101b surrounding the display area 101a. Figure 1 and Figure 2 The plurality of pixel units 102 are located in the display region 101a, and the blocking structure 103, at least one first power line 104 and the row driving circuit 105 are all located in the peripheral region 101b.

[0094] refer to Figure 1 , the blocking structure 103 surrounds the plurality of pixel units 102. At least one first power line 104 includes a first portion 1041 and a second portion 1042. The first portion 1041 is located on a side of the blocking structure 103 away from the plurality of pixel units 102, and is used to receive a first power signal, and the second portion 1042 surrounds the plurality of pixel units 102, and is electrically connected to the first portion 1041 and the first electrode layer b3 in the plurality of pixel units 102, respectively. The row driving circuit 105 is electrically connected to the plurality of pixel units 102, and is used to provide driving signals to the plurality of pixel units 102.

[0095] Among them, reference Figure 1 , the orthographic projections of any two of the following structures on the substrate 101 at least partially overlap: the blocking structure 103, the at least one first power line 104, and the row driving circuit 105. That is, the orthographic projection of the blocking structure 103 on the substrate 101 at least partially overlaps with the orthographic projection of the at least one first power line 104 on the substrate 101, the orthographic projection of the blocking structure 103 on the substrate 101 at least partially overlaps with the orthographic projection of the row driving circuit 105 on the substrate 101, and the orthographic projection of the at least one first power line 104 on the substrate 101 at least partially overlaps with the orthographic projection of the row driving circuit 105 on the substrate 101.

[0096] To summarize, an embodiment of the present application provides a display panel, which includes a blocking structure, at least one first power line and a row driving circuit that overlap in parts, thereby effectively reducing the total width of each structure located in the peripheral area, thereby reducing the width of the display panel frame, and facilitating the realization of a narrow-frame display panel.

[0097] Optionally, the first power signal provided by the second portion 1042 of the first power line 104 to the first electrode layer b3 of the plurality of pixel units 102 may be a negative power signal, so the first power line 104 may also be referred to as a VSS power line or a VSS trace. The first electrode layer b3 may be a cathode layer. The material of the first power line 104 may include a metal material for transmitting the first power signal. The width of the first power line 104 ranges from 300 μm (micrometers) to 340 μm, for example, the width of the first power line 104 is 320 μm.

[0098] Since the orthographic projection of the first power line 104 on the base substrate 101 at least partially overlaps with the orthographic projection of the row driving circuit 105 on the base substrate 101, and the voltage of the negative power signal transmitted by the first power line 104 is a stable voltage, the influence of other circuits on the side of the first power line 104 away from the base substrate 101 on the row driving circuit 105 can be effectively shielded, and the stability of the row driving circuit 105 is better.

[0099] In the embodiment of the present application, the display area 101a where the orthographic projections of the plurality of pixel units 102 on the base substrate 101 are located is the active display area (AA) of the display panel 10. The blocking structure 103 may be disposed around the AA area.

[0100] Optionally, the first electrode layer b3 of the plurality of pixel units 102 may be shared and may cover the AA region in its entirety. The orthographic projection of the first electrode layer b3 shared by the plurality of pixel units 102 on the base substrate 101 may be located within the orthographic projection of the region enclosed by the blocking structure 103 on the base substrate 101.

[0101] In the embodiment of the present application, the display panel 10 may be an organic light-emitting diode (OLED) or a liquid crystal display device, which is not limited in the embodiment of the present application. The embodiment of the present application is described by taking the display panel 10 as an OLED display panel as an example.

[0102] refer to Figure 3 The display panel 10 includes a plurality of color pixel units 102 arranged in a display area 101a, and the pixel units 102 may also be referred to as sub-pixels. The plurality of color pixel units include at least a first color pixel unit, a second color pixel unit, and a third color pixel unit, and the first color, the second color, and the third color may be three primary colors (e.g., red, green, and blue).

[0103] For the convenience of explanation, the above-mentioned multiple pixel units 102 in the embodiment of the present application are described as being arranged in a matrix form. In this case, the pixel units 102 arranged in a row along the horizontal direction M are called a row of pixel units; the pixel units 102 arranged in a row along the vertical direction N are called a column of pixel units.

[0104] refer to Figure 4 Each pixel unit 102 is provided with a pixel circuit S, and the pixel circuit S includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a capacitor Cst.

[0105] Wherein, the control electrode of the first transistor T1 is coupled to the second node N2, and the first electrode of the first transistor T1 is coupled to the first node N1; the control electrode of the second transistor T2 is coupled to the first scan signal terminal GATE1, the first electrode of the second transistor T2 is coupled to the data signal terminal DATA, and the second electrode of the second transistor T2 is coupled to the first node N1; the control electrode of the third transistor T3 is coupled to the second scan signal terminal GATE2, the first electrode of the third transistor T3 is coupled to the second node N2, and the second electrode of the third transistor T3 is coupled to the second electrode of the first transistor T1; the control electrode of the fourth transistor T4 is coupled to the third scan signal terminal GATE3, the first electrode of the fourth transistor T4 is coupled to the initial signal terminal VINT, and the second electrode of the fourth transistor T4 is coupled to the initial signal terminal VINT. The first electrode of the fifth transistor T5 is coupled to the second node N2; the control electrode of the fifth transistor T5 is coupled to the light-emitting control signal terminal EM, the first electrode of the fifth transistor T5 is coupled to the first voltage signal terminal VDD, and the second electrode of the fifth transistor T5 is coupled to the first node N1; the control electrode of the sixth transistor T6 is coupled to the light-emitting control signal terminal EM, the first electrode of the sixth transistor T6 is coupled to the second electrode of the first transistor T1; the control electrode of the seventh transistor T7 is coupled to the fourth scanning signal terminal GATE4, the first electrode of the seventh transistor T7 is coupled to the initial signal terminal VINT, and the second electrode of the seventh transistor T7 is coupled to the second electrode of the sixth transistor T6; the first end of the capacitor Cst is coupled to the first voltage signal terminal VDD, and the second end of the capacitor Cst is coupled to the second node N2.

[0106] The pixel circuit 102 further includes a light emitting unit D, a first electrode of the light emitting unit D is coupled to the second electrode of the sixth transistor T6, and a second electrode of the light emitting unit D is coupled to the second voltage signal terminal VSS. The pixel circuits S in the same row are coupled to the same control signal line L, and the pixel circuits S in the same column are coupled to the same data line DL (data line) to drive the light emitting unit D in the pixel unit 102 to emit light.

[0107] It should be noted that the pixel circuit S is not limited to Figure 4The circuit structure shown in the figure may also be other circuit structures, which are not listed here.

[0108] The transistors included in the pixel circuit S may all be N-type transistors, or may all be P-type transistors, or may include both N-type and P-type transistors, and may be designed according to actual needs. In addition, the transistors included in the pixel circuit S may all be low temperature polysilicon (LTPS) transistors, or may all be oxide transistors, or may include both low temperature polysilicon and oxide transistors.

[0109] In some embodiments, since the voltage controlling the brightness of the pixel unit changes over time due to the leakage of the transistor in the pixel circuit S, in order to keep the pixel brightness fluctuation within a reasonable range, it is still necessary to refresh the data when displaying a static image. In order to reduce power consumption when displaying a static image, reducing the refresh frequency is a more effective method. At the same time, in order to maintain the display quality, it is necessary to reduce the leakage speed of the transistor in the pixel circuit S.

[0110] To solve the above problems, in some embodiments, the excellent properties of low temperature polysilicon and oxide can be combined to adopt a low temperature polycrystalline oxide (LTPO) process to make the transistors used for driving in the pixel circuit S (for example Figure 4 The first transistor T1, the fifth transistor T5 and the sixth transistor T6) in the pixel circuit S are set as oxide transistors, and the ultra-low leakage characteristics of oxide semiconductors are utilized to improve the transistor leakage phenomenon; the transistors used for switching in the pixel circuit S (such as the second transistor T2, the third transistor T3, the fourth transistor T4 and the seventh transistor T7) are set as low-temperature polysilicon transistors to ensure the charging speed of the pixel unit 102 and the smaller parasitic capacitance.

[0111] refer to Figure 3 As shown, the peripheral region 101b is provided with at least one row driving circuit 105 and a data driving circuit DD. In some embodiments, the row driving circuit 105 can be provided on the side along the extension direction of the control signal line L, and the data driving circuit DD can be provided on the side along the extension direction of the data line DL to drive the pixel circuit S in the pixel unit 102, thereby driving the light-emitting unit to emit light, so that the display panel 10 performs display.

[0112] For example, the row driving circuit may be a row driving circuit for transmitting a light emitting control signal Em to the pixel circuit S, or may be a row driving circuit for transmitting a scanning signal Gate to the pixel circuit S.

[0113] For example, Figure 3As shown, the peripheral area 101b is provided with a first row driving circuit e1, a second row driving circuit e2 and a third row driving circuit e3. Figure 4 The first row driving circuit e1 is configured to transmit a light emitting control signal Em to the light emitting control signal terminal EM of the pixel circuit S; the second row driving circuit e2 is configured to transmit a second scanning signal Gate2 to the second scanning signal terminal GATE2 of the pixel circuit S, and to transmit a third scanning signal Gate3 to the third scanning signal terminal GATE3; the third row driving circuit e3 is configured to transmit a first scanning signal Gate1 to the first scanning signal terminal GATE1 of the pixel circuit S, and to transmit a fourth scanning signal Gate4 to the fourth scanning signal terminal GATE4.

[0114] The number of row driving circuits 105 included in the display panel 10 may be determined according to specific circumstances, and the above is only an example.

[0115] In some embodiments, the row driving circuit 105 may be a gate driver on array (GOA) circuit, that is, the row driving circuit 105 is directly integrated on the array substrate of the display panel 10. The following embodiments are all described by taking the row driving circuit as a GOA circuit as an example.

[0116] It needs to be explained that, Figure 3 It is only for illustration, and the description is made by setting a row driving circuit 105 on a single side of the peripheral area 101b, and driving each control signal line L row by row from the single side, that is, taking single-side driving as an example. In other embodiments, row driving circuits 105 may be respectively set on two sides along the extension direction of the control signal line L in the peripheral area 101b, and each control signal line L may be driven row by row from both sides at the same time by two row driving circuits 105, that is, double-sided driving. In other embodiments, a first sub-driving circuit 1051 and a second sub-driving circuit 1052 of the row driving circuit 105 may be respectively set on two sides along the extension direction of the control signal line L in the peripheral area 101b, and each control signal line L may be driven row by row alternately from both sides, that is, cross driving.

[0117] In some embodiments of the present disclosure, the row driving circuit 105 includes a plurality of shift register circuits cascaded in sequence, and each stage of the shift register circuit is coupled to at least one control signal line L.

[0118] For example, Figure 3As shown, N shift register circuits (RS1, RS2, ... RS(N)) are coupled to N control signal lines (L1, L2, ... L(N)) in a one-to-one correspondence, each shift register circuit is coupled to a control signal line L, and each control signal line L is coupled to a row of sub-pixels P, that is, each shift register circuit drives a row of pixel units 102. Wherein, N is a positive integer. In other embodiments, each control signal line L can be coupled to two adjacent rows of pixel units 102, that is, except for the first and last shift register circuits, each shift register circuit can drive two rows of pixel units 102.

[0119] For example, Figure 3 As shown, along the extension direction of the control signal line L, when the second row driving circuit e2 is located between the first row driving circuit e1 and the third row driving circuit e3, except for the first and last shift register circuits in the second row driving circuit e2, each shift register circuit drives two adjacent rows of pixel units 102. Moreover, except for the first and last shift register circuits in the third row driving circuit e3, each shift register circuit drives two adjacent rows of pixel units 102.

[0120] For another example, along the extension direction of the control signal line L, when the third row driving circuit e3 is located between the first row driving circuit e1 and the second row driving circuit e2, each stage of the shift register circuit in the second row driving circuit e2 drives a row of pixel units 102, and each stage of the shift register circuit in the third row driving circuit e3 drives a row of pixel units 102.

[0121] refer to Figure 3 It can also be seen that the display panel 10 may further include: a timing controller TCON. The timing controller TCON may be coupled to the shift register circuits to transmit voltage signals from the timing controller TCON to the shift register circuits.

[0122] In the examples of this application, refer to Figure 2 The peripheral region 101b may include: a first region 101b1 and a second region 101b2 arranged oppositely and in parallel, and a third region 101b3 and a fourth region 101b4 arranged oppositely and in parallel. The extension direction of the first region 101b1 is perpendicular to the extension direction of the third region 101b3.

[0123] Optionally, the first area 101b1 may be an area below the display area 101a, the second area 101b2 may be an area above the display area 101a, the third area 101b3 may be an area on the left side of the display area 101a, and the fourth area 101b4 may be an area on the right side of the display area 101a.

[0124] Among them, combined Figure 1 and Figure 2 , the first portion 1041 of the first power line 104 may be located in the first area 101b1, and the second portion 1042 may be located in the second area 101b2, the third area 101b3 and the fourth area 101b4. That is, the second portion 1042 of the first power line 104 may surround three sides of the display area 101a. Of course, the second portion 1042 may also surround two sides or four sides of the display area 101a, which is not limited in the embodiment of the present application.

[0125] In the embodiment of the present application, the portion of the blocking structure 103 through which the power line passes can be referred to as a port, for example, the portion through which the first power line 104 passes can be referred to as a first port 10a. Figure 1 The first power line 104 may include two first parts 1041 , whereby the two first parts 1041 may pass through the blocking structure 103 respectively, and the blocking structure 103 may have two first line inlets 10a for the two first parts 1041 to pass through.

[0126] Furthermore, the two first portions 1041 may be arranged symmetrically with respect to the axis X of the base substrate 101. For example, the two first portions 1041 may be located on both sides of the base substrate 101. The axis X of the base substrate 101 may be parallel to the column direction of the plurality of pixel units 102.

[0127] Optionally, the two first portions 1041 located on both sides of the substrate 101 may mean: for a first portion 1041 located on the same side of the axis X as the third region 101b3, the distance between the first portion 1041 and the third region 101b3 is smaller than the distance between the first portion 1041 and the axis X; for another first portion 1041 located on the same side of the axis X as the fourth region 101b4, the distance between the first portion 1041 and the fourth region 101b4 is smaller than the distance between the first portion 1041 and the axis X.

[0128] refer to Figure 1 It can also be seen that the first power cord 104 may further include a second portion 1042. One end of the second portion 1042 may be connected to a first portion 1041, and the other end of the second portion 1042 may be connected to another first portion 1041. Optionally, the two first portions 1041 and the one second portion 1042 may be an integral structure, and the second portion 1042 of the first power cord 104 may be a non-enclosed structure.

[0129] In the embodiment of the present application, the row driving circuit 105 may include: a first sub-driving circuit 1051 and a second sub-driving circuit 1052. The first sub-driving circuit 1051 may be located in the third area 101b3, and the second sub-driving circuit 1052 may be located in the fourth area 101b4.

[0130] Thus, the orthographic projection of the first sub-driving circuit 1051 on the base substrate 101 overlaps with the orthographic projection of the portion of the second portion 1042 located in the third region 101b3 on the base substrate 101, and the orthographic projection of the portion of the blocking structure 103 located in the third region 101b3 on the base substrate 101. The orthographic projection of the second sub-driving circuit 1052 on the base substrate 101 overlaps with the orthographic projection of the portion of the second portion 1042 located in the fourth region 101b4 on the base substrate 101, and the orthographic projection of the portion of the blocking structure 103 located in the fourth region 101b4 on the base substrate 101.

[0131] Optionally, the first sub-driving circuit 1051 and the second sub-driving circuit 1052 may include: an emission control (EM) circuit, a first type of driving circuit, and a second type of driving circuit. The emission control circuit may be Figure 3 The first row driving circuit e1 in the figure, the first type of driving circuit can be Figure 3 The second type of driving circuit may be one of the second row driving circuit e2 and the third row driving circuit e3. Figure 3 Another circuit in the second row driving circuit e2 and the third row driving circuit e3.

[0132] Optionally, the first type of driving circuit may be an N-type driving circuit, and the second type of driving circuit may be a P-type driving circuit. Both the N-type driving circuit and the P-type driving circuit may include a P-type transistor. Furthermore, the difference between the N-type driving circuit and the P-type driving circuit is that the potential of the scanning signal provided by the N-type driving circuit is higher than the potential of the scanning signal provided by the P-type driving circuit.

[0133] The orthographic projection of the first power line 104 on the base substrate 101 may at least partially overlap with the orthographic projection of the light emitting control circuit on the base substrate 101. Optionally, the width of the first power line 104 may be 1.5 to 2.5 times the width of the length of the light emitting control circuit along the row direction. For example, the length of the light emitting control circuit along the row direction ranges from 150 μm to 190 μm, for example, 170 μm.

[0134] According to the width of the first power line 104 and the length of the light emitting control circuit along the row direction, it can be known that the width of the first power line 104 is greater than the width of the light emitting control circuit. Therefore, part of the orthographic projection of the first power line 104 on the base substrate 101 overlaps with the orthographic projection of the light emitting control circuit on the base substrate 101, and the other part overlaps with the orthographic projection of the N-type driving circuit on the base substrate.

[0135] Figure 5 is an equivalent circuit diagram of a light emitting control circuit provided in an embodiment of the present application. In order to distinguish the transistors in the above pixel circuit, the transistors in the light emitting control circuit are represented by the symbol M. Figure 5 The light emitting control circuit includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, a first capacitor C1, a second capacitor C2 and a third capacitor C3.

[0136] Wherein, the control electrode of the first transistor M1 is coupled to the first clock signal terminal CK, the first electrode of the first transistor M1 is coupled to the start signal terminal ESTV, and the second electrode of the first transistor M1 is coupled to the first node N1; the control electrode of the second transistor M2 is coupled to the first node N1, the first electrode of the second transistor M2 is coupled to the first clock signal terminal CK, and the second electrode of the second transistor M2 is coupled to the second node N2; the control electrode of the third transistor M3 is coupled to the clock signal terminal CK, the first electrode of the third transistor M3 is coupled to the first power supply terminal VGL, and the second electrode of the third transistor M3 is coupled to The second node N2 is coupled; the control electrode of the fourth transistor M4 is coupled to the second clock signal terminal CB, the first electrode of the fourth transistor M4 is coupled to the first node N1, and the second electrode of the fourth transistor M4 is coupled to the first electrode of the fifth transistor M5; the control electrode of the fifth transistor M5 is coupled to the second node N2, and the second electrode of the fifth transistor M5 is coupled to the second power supply terminal VGH; the control electrode of the sixth transistor M6 is coupled to the second node N2, the first electrode of the sixth transistor M6 is coupled to the second clock signal terminal CB, and the second electrode of the sixth transistor M6 is coupled to the third node N3; the seventh transistor A control electrode of M7 is coupled to the second clock signal terminal CB, a first electrode of the seventh transistor M7 is coupled to the third node N3, and a second electrode of the seventh transistor M7 is coupled to the fourth node; a control electrode of the eighth transistor M8 is coupled to the first node N1, a first electrode of the eighth transistor M8 is coupled to the second power supply terminal VGH, and a second electrode of the eighth transistor M8 is coupled to the fourth node N4; a control electrode of the ninth transistor M9 is coupled to the fourth node N4, a first electrode of the ninth transistor M9 is coupled to the second power supply terminal VGH, and a second electrode of the ninth transistor M9 is coupled to the output terminal EM of the light emitting control circuit; The control electrode of the tenth transistor M10 is coupled to the first node N1, the first electrode of the tenth transistor M10 is coupled to the first power supply terminal VGL, and the second electrode of the tenth transistor M10 is coupled to the output terminal of the light emitting control circuit; the first end of the first capacitor C1 is coupled to the second node N2, and the second end of the first capacitor C2 is coupled to the third node N3; the first end of the second capacitor C2 is coupled to the first node N1, and the second end of the second capacitor C2 is coupled to the second clock signal terminal CB; the first end of the third capacitor C3 is coupled to the fourth node N4, and the second end of the third capacitor C3 is coupled to the second power supply terminal VGH.

[0137] Figure 6 is a timing diagram of a light emitting control circuit provided in an embodiment of the present application. Figure 6 It can be seen that:

[0138] In the first stage P1, the first clock signal CK is at a low level, so the first transistor M1 and the third transistor M3 are turned on, and the turned-on first transistor M1 transmits the start signal of the high-level start signal terminal ESTV to the first node N1, so that the level of the first node N1 becomes high, so the second transistor M2, the eighth transistor M8 and the tenth transistor M10 are turned off. In addition, the turned-on third transistor M3 transmits the low-level first voltage of the first power supply terminal VGL to the second node N2, so that the level of the second node N2 becomes low, so the fifth transistor M5 and the sixth transistor M6 are turned on. Since the second clock signal of the second clock signal terminal CB is at a high level, the seventh transistor M7 is turned off. In addition, due to the storage effect of the third capacitor C3, the level of the fourth node N4 can be kept at a high level, so that the ninth transistor M9 is turned off. In the first stage P1, since the ninth transistor M9 and the tenth transistor M10 are both turned off, the light-emitting control pulse signal output by the output terminal EM of the light-emitting control circuit maintains the previous low level.

[0139] In the second stage P2, the second clock signal of the second clock signal terminal CB is at a low level, so the fourth transistor M4 and the seventh transistor M7 are turned on. Since the first clock signal of the first clock signal terminal CK is at a high level, the first transistor M1 and the third transistor M3 are turned off. Due to the storage function of the first capacitor C1, the second node N2 can continue to maintain the low level of the previous stage, so the fifth transistor M5 and the sixth transistor M6 are turned on. The high-level second voltage of the second power supply terminal VGH is transmitted to the first node N1 through the turned-on fifth transistor M5 and the fourth transistor M4, so that the level of the first node N1 continues to maintain the high level of the previous stage, so the second transistor M2, the eighth transistor M8 and the tenth transistor M10 are turned off. In addition, the low-level second clock signal of the second clock signal terminal CB is transmitted to the fourth node N4 through the turned-on sixth transistor M6 and the seventh transistor M7, so that the level of the fourth node N4 becomes a low level, so the ninth transistor M9 is turned on, and the turned-on ninth transistor M9 outputs a high-level second voltage, so the light-emitting control pulse signal output by the output terminal EM of the light-emitting control circuit in the second stage P2 is high.

[0140] In the third stage P3, the first clock signal of the first clock signal terminal CK is at a low level, so the first transistor M1 and the third transistor M3 are turned on. The second clock signal of the second clock signal terminal CB is at a high level, so the fourth transistor M4 and the seventh transistor M7 are turned off. Due to the storage function of the third capacitor C3, the level of the fourth node N4 can maintain the low level of the previous stage, so that the ninth transistor M9 remains in the on state, and the turned-on ninth transistor M9 outputs the second voltage of the high level, so the light-emitting control pulse signal output by the output terminal EM of the light-emitting control circuit in the third stage P3 is still at a high level.

[0141] In the fourth stage P4, the first clock signal of the first clock signal terminal CK is at a high level, so the first transistor M1 and the third transistor M3 are turned off. The second clock signal of the second clock signal terminal CB is at a low level, so the fourth transistor M4 and the seventh transistor M7 are turned on. Due to the storage function of the second capacitor C2, the level of the first node N1 remains at a high level in the previous stage, so that the second transistor M2, the eighth transistor M8 and the tenth transistor M10 are turned off. Due to the storage function of the first capacitor C1, the second node N2 continues to maintain the low level in the previous stage, so that the fifth transistor M5 and the sixth transistor M6 are turned on. In addition, the second clock signal of the second clock signal terminal CB of the low level is transmitted to the fourth node N4 through the turned-on sixth transistor M6 and the seventh transistor M7, so that the level of the fourth node N4 becomes a low level, so the ninth transistor M9 is turned on, and the turned-on ninth transistor M9 outputs the second voltage of the high level, so the light control pulse signal EM output by the output terminal EM of the light emitting control circuit in the second stage P2 is still at a high level.

[0142] In the fifth stage P5, the first clock signal of the first clock signal terminal CK is at a low level, so the first transistor M1 and the third transistor M3 are turned on. The second clock signal of the second clock signal terminal CB is at a high level, so the fourth transistor M4 and the seventh transistor M7 are turned off. The turned-on first transistor M1 transmits the start signal of the low-level start signal terminal ESTV to the first node N1, so that the level of the first node N1 becomes a low level, so the second transistor M2, the eighth transistor M8 and the tenth transistor M10 are turned on. The turned-on second transistor M2 transmits the first clock signal of the low-level first clock signal terminal CK to the second node N2, so that the level of the second node N2 can be further lowered, so the second node N2 continues to maintain the low level of the previous stage, so that the fifth transistor M5 and the sixth transistor M6 are turned on. In addition, the turned-on eighth transistor M8 transmits the high-level second voltage to the fourth node N4, so that the level of the fourth node N4 becomes a high level, so the ninth transistor M9 is turned off. The turned-on tenth transistor M10 outputs the second voltage of a low level, so the light emitting control pulse signal outputted by the output terminal EM of the light emitting control circuit in the fifth stage P5 becomes a low level.

[0143] In the examples of this application, refer to Figure 1 The blocking structure 103 may be a ring-shaped structure surrounding the plurality of pixel units 102, and is used to block the overflow of the organic layer in the area surrounded by the blocking structure 103 in the display panel 10. The blocking structure 103 may include: a first blocking dam 1031 and a second blocking dam 1032. The first blocking dam 1031 is closer to the plurality of pixel units 102 than the second blocking dam 1032, and the thickness of the first blocking dam 1031 may be less than the thickness of the second blocking dam 1032.

[0144] By providing two blocking dams, and the thickness of the second blocking dam 1032 away from the plurality of pixel units 102 is greater than the thickness of the first blocking dam 1031 close to the plurality of pixel units 102, it is possible to further prevent the organic layer from overflowing in the area surrounded by the blocking structure 103. Of course, the blocking structure 103 may also include one blocking dam, or more than two blocking dams, which is not limited in the embodiment of the present application.

[0145] refer to Figure 1 The orthographic projections of the first barrier dam 1031 and the second barrier dam 1032 on the substrate 101 may be annular. The first barrier dam 1031 being closer to the plurality of pixel units 102 relative to the second barrier dam 1032 may be used to indicate that the area enclosed by the first barrier dam 1031 is within the area enclosed by the second barrier dam 1032.

[0146] Optionally, the width of the first barrier dam 1031 and the width of the second barrier dam 1032 may be 1 / 4 to 1 / 2 times the width of the light emitting control circuit. For example, the width of the first barrier dam 1031 and the width of the second barrier dam 1032 are both greater than or equal to 40 μm. Furthermore, the distance between the first barrier dam 1031 and the second barrier dam 1032 may be greater than or equal to 40 μm.

[0147] Figure 7 yes Figure 1 The cross-sectional view of the display panel along the BB direction is shown. Figure 7 The first barrier dam 1031 may include: a first pattern 106a and a second pattern 107a sequentially stacked in a direction away from the base substrate 101. The second barrier dam 1032 may include: a third pattern 108a, a fourth pattern 106b and a fifth pattern 107b sequentially stacked in a direction away from the base substrate 101. The first pattern 106a and the fourth pattern 106b may be located in a pixel definition layer (PDL) 106 of the display panel 10, the second pattern 107a and the fifth pattern 107b may be located in a photo spacer (PS) 107 of the display panel, and the third pattern 108a may be located in a first planarization layer (PLN) 108 of the display panel.

[0148] The patterns in the same layer may include the same material and be made by the same patterning process. For example, the first pattern 106a and the fourth pattern 106b may include the same material and be made by the same patterning process. The second pattern 107a and the fifth pattern 107b may include the same material and be made by the same patterning process.

[0149] refer to Figure 7 The second barrier dam 1032 is provided with an additional third pattern 108a of the first planar layer 108 relative to the first barrier dam 1031, so that the thickness of the second barrier dam 1032 can be greater than that of the first barrier dam 1031 to prevent the organic layer from overflowing.

[0150] Optionally, the material used to make the pixel defining layer 106 , the support layer 107 , and the first planar layer 108 may include: organic materials such as resin, etc. This embodiment of the present application does not limit this.

[0151] Figure 8 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. Figure 8, the display panel may further include: at least one second power line 109 located in the peripheral area 101b. One end of the at least one first power line 104 may be located on a side of the blocking structure 103 away from the plurality of pixel units 102, for receiving a second power signal, and the other end may be located on a side of the blocking structure 103 close to the plurality of pixel units 102, and electrically connected to the plurality of pixel units 102, so that the second power line 109 may provide the second power signal to the plurality of pixel units 102. Optionally, each second power line 109 may be located in the first area 101b1 of the peripheral area 101b.

[0152] Optionally, the other end of the at least one second power line 109 may be electrically connected to the thin film transistors 1021 in the plurality of pixel units 102. For example, it may be connected to the source a81 or the drain a82 of the thin film transistor 1021 in the pixel unit 102. The second power signal provided by the second power line 109 to the thin film transistor 1021 in the pixel unit 102 may be a positive power signal, so the second power line 109 may also be referred to as a VDD power line or a VDD routing.

[0153] Furthermore, the orthographic projection of at least one second power line 109 on the base substrate 101 may at least partially overlap with the orthographic projection of the blocking structure 103 on the base substrate 101. For example, the orthographic projections of the two second power lines 109 included in the display panel 10 on the base substrate 101 both at least partially overlap with the orthographic projections of the blocking structure 103 on the base substrate 101. Thus, the width of the first region 101b1 in the base substrate 101 where the second power lines 109 are disposed may be reduced, thereby reducing the width of the frame of the display panel 10, and facilitating the realization of a narrow frame of the display panel 10.

[0154] refer to Figure 8 , one end of each second power line 109 is located outside the area surrounded by the blocking structure 103, and the other end is located within the area surrounded by the blocking structure 103. That is, each second power line 109 can pass through the blocking structure 103 and enter the area surrounded by the blocking structure 103. Among them, the part of the blocking structure 103 through which the second power line 109 passes can be called a second line inlet 10b.

[0155] Typically, the second power signal received by the second power line 109 needs to be transmitted to each pixel unit 102 in the display area 101a, and the reliability of the second power signal received by the pixel unit 102 that is farther away from the second power line 109 is lower than that of the pixel unit 102 that is farther away from the second power line 109.

[0156] Therefore, as an optional implementation, refer to Figure 8The display panel 10 may include: two second power lines 109, wherein the two second power lines 109 may be symmetrically arranged with respect to the axis X of the base substrate 101. Thus, the reliability of the second power signal received by each pixel unit 102 may be improved by transmitting the second power signal through two second power lines 109 compared with transmitting the second power signal through only one second power line 109.

[0157] Optionally, the two second power lines 109 may be located on both sides of the base substrate 101. The two second power lines 109 being located on both sides of the base substrate 101 may mean that the distance between the second power line 109 and the first portion 1041 of the first power line 104 located on the same side of the axis X is less than the distance between the second power line 109 and the axis X. That is, for the second power line 109 where one of the two first portions 1041 included in the first power line 104 is located on the same side of the axis X, the distance between the second power line 109 and the first portion 1041 is less than the distance between the second power line 109 and the axis X; for the second power line 109 where the other of the two first portions 1041 included in the first power line 104 is located on the same side of the axis X, the distance between the second power line 109 and the other first portion 1041 is less than the distance between the second power line 109 and the axis X.

[0158] Alternatively, the two second power lines 109 may also be located in the middle of the base substrate 101, and the embodiment of the present application does not limit the location of the second power lines 109. The two second power lines 109 being located in the middle of the base substrate 101 may mean that the distance between the second power line 109 and the first portion 1041 of the first power line 104 located on the same side of the axis X is greater than the distance between the second power line 109 and the axis X.

[0159] As another optional implementation, refer to Fig. 9, the second power line 109 included in the display panel 10 may include: a third portion 1091, two fourth portions 1092, a fifth portion 1093, and two sixth portions 1094. The third portion 1091 is located on a side of the blocking structure 103 close to the multiple pixel units 102, and is electrically connected to the multiple pixel units 102. The two fourth portions 1092 are both located on a side of the third portion 1091 away from the multiple pixel units 102, and are electrically connected to the third portion 1091. The fifth portion 1093 is located on a side of the two fourth portions 1092 away from the multiple pixel units 102, and is electrically connected to the two fourth portions 1092. The two sixth portions 1094 are located on a side of the blocking structure 103 away from the multiple pixel units 102, and are used to receive the second power signal, and the two sixth portions 1094 are both electrically connected to the fifth portion 1093. Reference Fig. 9 The two fourth portions 1092 are symmetrically arranged with the axis X of the base substrate 101 as the axis, and the two sixth portions are symmetrically arranged with the axis X of the base substrate 101 as the axis.

[0160] Therefore, the second power signal received by the second power line 109 can be transmitted to the pixel units 102 located in various areas of the display area 101a through the second power line 109 including the third part 1091, two fourth parts 1092, the fifth part 1093, and the two sixth parts 1094, thereby ensuring the reliability and consistency of the second power signal received by the pixel units 102 located in various areas of the display area 101a, and further ensuring the display effect of the display panel 10.

[0161] Optionally, the third part 1091, two fourth parts 1092, the fifth part 1093, and two sixth parts 1094 included in the second power line 109 can be prepared using the same material and the same composition process, and the third part 1091, the two fourth parts 1092, the fifth part 1093, and the two sixth parts 1094 can be an integrated structure.

[0162] refer to Fig. 9, the two sixth portions 1094 may be located on both sides of the base substrate 101. The two sixth portions 1094 being located on both sides of the base substrate 101 may mean that: the distance between the sixth portion 1094 and the first portion 1041 of the first power line 104, which are located on the same side of the axis X, is smaller than the distance between the sixth portion 1094 and the axis X. That is, for the sixth portion 1094, which is located on the same side of the axis X as one of the two first portions 1041 included in the first power line 104, the distance between the sixth portion 1094 and the first portion 1041 is smaller than the distance between the sixth portion 1094 and the axis X; for the sixth portion 1094, which is located on the same side of the axis X as the other of the two first portions 1041 included in the first power line 104, the distance between the sixth portion 1094 and the other first portion 1041 is smaller than the distance between the sixth portion 1094 and the axis X.

[0163] And, reference Fig. 9 , the third portion 1091 and the fifth portion 1093 both extend in the row direction, and the two fourth portions 1092 and the two sixth portions 1094 both extend in the column direction. The extension direction of any of the two fourth portions 1092 does not overlap with the extension direction of any of the sixth portions 1094. Of course, the extension direction of each of the two fourth portions 1092 may overlap with the extension direction of the sixth portion 1094 located on the same side, which is not limited in the embodiment of the present application.

[0164] In the case where the display panel 10 includes the third portion 1091, two fourth portions 1092, a fifth portion 1093, and two sixth portions 1094, the orthographic projection of each of the two fourth portions 1092 on the base substrate 101 may at least partially overlap with the orthographic projection of the blocking structure 103 on the base substrate 101. For example, a side of each fourth portion 1092 close to the plurality of pixel units 102 is located within the region surrounded by the blocking structure 103, and another side of each fourth portion 1092 away from the plurality of pixel units 102 is located outside the region surrounded by the blocking structure 103.

[0165] Fig.10 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. Fig.10 It can be seen that each pixel unit 102 included in the display panel may include: a thin film transistor (TFT) 1021 and a light emitting unit 1022 stacked in sequence in a direction away from the base substrate 101. Figure 7 A pixel unit 102 is shown in FIG. Figure 7The thin film transistor 1021 in the pixel unit 102 shown in FIG. Figure 4 The transistor in.

[0166] refer to Fig.10 The thin film transistor 1021 may include: a first buffer layer (buffer) a1, a first active pattern a2, a first gate insulating layer (gate insulator, GI) a3, a first gate pattern a4, a second gate insulating layer a5, a second buffer layer a6, an interlayer dielectric layer (inter layer dielectric, ILD) a7 and a source and drain a8 stacked in sequence in a direction away from the base substrate 101. The source and drain a8 may include a source (source, S) a81 and a drain (drain, D) a82 arranged at intervals, and the source a81 and the drain a82 may be connected to the first active pattern a2.

[0167] Optional, above Fig.10 The thin film transistor 1021 shown in the figure can be a polysilicon transistor. Of course, the display panel 10 can also include an LTPO thin film transistor. Since the LTPO thin film transistor 1021 includes an oxide layer, electrons can pass through the LTPO thin film transistor faster and better, reducing the energy consumption required to excite the light emitting unit 1022 in the pixel unit 102 to emit light, thereby reducing the power consumption of the display panel 10 when displaying.

[0168] Reference Fig.10 The light emitting unit 1022 may include: an electrode pattern b1, a light emitting pattern b2 and a first electrode layer b3 stacked in sequence in a direction away from the base substrate 101. The electrode pattern b1 may be located in the second electrode layer, and the electrode pattern b1 may be connected to the drain a82.

[0169] refer to Fig.10 It can also be seen that the row driving circuit 105 included in the display panel 10 may include: a first buffer layer c1, a second active pattern c2, a first gate insulating layer c3, a second gate pattern c4, a second gate insulating layer c5, a third gate pattern c6, a second buffer layer c7, an interlayer dielectric layer c8, and a connection layer c9 stacked in sequence in a direction away from the base substrate 101. The connection layer c9 may be connected to the first gate pattern a4 to achieve the function of transmitting signals.

[0170] In the embodiment of the present application, the thin film transistors 1021 in the plurality of pixel units 102 included in the display panel 10 and the first buffer layer, the first gate insulating layer, the second gate insulating layer, the second buffer layer, and the interlayer dielectric layer of the row driving circuit 105 are all common film layers. That is, the first buffer layer a1 of the thin film transistor 1021 and the first buffer layer c1 of the row driving circuit 105 are an integrated structure. The first gate insulating layer a3 of the thin film transistor 1021 and the first gate insulating layer c3 of the row driving circuit 105 are an integrated structure. The second gate insulating layer a5 of the thin film transistor 1021 and the second gate insulating layer c5 of the row driving circuit 105 are an integrated structure. The second buffer layer a6 of the thin film transistor 1021 and the second buffer layer c7 of the row driving circuit 105 are an integrated structure. The interlayer dielectric layer a7 of the thin film transistor 1021 and the interlayer dielectric layer c8 of the row driving circuit 105 are an integrated structure.

[0171] Furthermore, the first active pattern a2 of the thin film transistor 1021 in the plurality of pixel units 102 included in the display panel 10, and the second active pattern c2 of the row driving circuit 105 are both located in the active layer. That is, the first active pattern a2 and the second active pattern c2 may include the same material and be made by the same patterning process. The first gate pattern a4 of the thin film transistor 1021 in the plurality of pixel units 102 included in the display panel, and the second gate pattern c4 of the row driving circuit 105 are both located in the first gate layer. That is, the first gate pattern a4 and the second gate pattern c4 may include the same material and be made by the same patterning process. The source and drain a8 of the thin film transistor 1021 in the plurality of pixel units 102 included in the display panel, and the connection layer c9 of the row driving circuit 105 are both located in the source and drain layer. That is, the source and drain a8 and the connection layer c9 may include the same material and be made by the same patterning process. In addition, the third gate pattern c6 of the row driving circuit 105 may be located in the second gate layer.

[0172] The electrode patterns b1 of the light-emitting units 1022 in the plurality of pixel units 102 included in the display panel 10 are all located in the anode layer. That is, the electrode patterns b1 of the light-emitting units 1022 in the plurality of pixel units 102 may include the same material and be made by the same patterning process. The light-emitting patterns b2 of the light-emitting units 1022 in the plurality of pixel units 102 included in the display panel 10 are all located in the light-emitting layer. That is, the light-emitting patterns b2 of the light-emitting units 1022 in the plurality of pixel units 102 may include the same material and be made by the same patterning process.

[0173] refer to Fig.10The display panel 10 includes a pixel defining layer 106 and a support layer 107. The pixel defining layer 106 may be located on a side of the anode layer away from the base substrate, and the support layer 107 may be located on a side of the pixel defining layer 106 away from the base substrate. The pixel defining layer 106 may have a plurality of openings, each of which may be used to expose an electrode pattern b1 in the anode layer, so that the light-emitting pattern b2 subsequently formed in the opening can contact the electrode pattern b1, thereby realizing light emission of the pixel unit.

[0174] refer to Fig.10 It can be seen that the display panel 10 may further include: a passivation layer (PVX) 110, a first flat layer 108 and a second flat layer 111. The passivation layer 110 may be located on the side of the source and drain a8 away from the base substrate 101, the second flat layer 111 is located on the side of the passivation layer 110 away from the base substrate 101, at least one first power line 104 is located on the side of the second flat layer 111 away from the base substrate 101, and the first flat layer 108 is located on the side of at least one first power line 104 away from the base substrate 101. That is, the passivation layer 110, the second flat layer 111, the at least one first power line 104 and the first flat layer 108 are stacked in sequence in a direction away from the base substrate 101.

[0175] In the examples of this application, refer to Fig.10 The orthographic projection of the second planar layer 111 on the base substrate 101 may overlap with the orthographic projection of the first blocking dam 1031 on the base substrate 101 and the orthographic projection of the second blocking dam 1032 on the base substrate 101 .

[0176] refer to Fig.10 It can also be seen that the display panel 10 may further include: a flexible film layer 112 and a barrier layer 113. The flexible film layer 112 may be located on one side of the base substrate 101, and the barrier layer 113 is located on the side of the flexible film layer 112 away from the base substrate 101. Moreover, the flexible film layer 112 and the barrier layer 113 are both located on the side of the plurality of pixel units 102 close to the base substrate 101.

[0177] Optionally, the material of the flexible film layer 112 may include polyimide (PI).

[0178] Fig.11 Schematic diagram of a first power line and a blocking structure provided by an embodiment of the present application. Fig.11It can be seen that the target portion of the at least one first power line 104 may have at least one opening 104a, and the opening 104a may expose the film layer located on the side of the at least one first power line 104 close to the base substrate 101. The orthographic projection of the target portion on the base substrate 101 may overlap with the orthographic projection of the blocking structure 103 on the base substrate 101. That is, the target portion is the portion of the at least one first power line 104 that overlaps with the blocking structure 103.

[0179] By providing at least one opening 104 a at the target portion of the first power line 104 , it is possible to avoid overflow of the organic layer in the display area 101 a causing bulging of the display panel there, and the quality of the display panel is improved.

[0180] Combination Figure 1 ,as well as Figures 8 to 9 The display panel 10 may further include: a power driving circuit 114. The power driving circuit 114 may be located in the peripheral area 101b and located on a side of the first portion 1041 away from the blocking structure 103. For example, the power driving circuit 114 may be located in the first area 101b1 of the peripheral area 101b.

[0181] The power driving circuit 114 can be connected to the first portion 1041 of the first power line 104, and is used to provide the first power signal to the first power line 104, so that the first power line 104 provides the first power signal from the power driving circuit 114 to the first electrode layer b3 of the plurality of pixel units 102. In addition, the power driving circuit 114 can also be connected to the second power line 109, and is used to provide the second power signal to the second power line 109, so that the second power line 109 provides the second power signal from the power driving circuit 114 to the plurality of pixel units 102.

[0182] For example, Figure 8 A first power line 104 is shown in FIG. 1 , and the first power line 104 includes two first parts 1041 , and two second power lines 109 are shown. The power driving circuit 114 can be connected to both the two first parts 1041 and the two second power lines 109 .

[0183] refer to Figure 7 as well as Fig.10 The display panel 10 may further include: a packaging film layer 115. The packaging film layer 115 may be located on a side of the plurality of pixel units 102 away from the base substrate 101, and the packaging film layer 115 covers the area surrounded by the blocking structure 103. Fig.10 The boundary of the area covered by the packaging film layer 115 may be located on a side of the blocking structure 103 away from the plurality of pixel units 102 .

[0184] In the embodiment of the present application, the encapsulation film layer 115 may include: a first film layer 1151 , a second film layer 1152 , and a third film layer 1153 which are stacked in a direction away from the base substrate 101 .

[0185] Optionally, the first film layer 1151 and the third film layer 1153 may be made of an inorganic material, and the second film layer 1152 may be made of an organic material. For example, the first film layer 1151 and the third film layer 1153 may be made of one or more inorganic oxides such as SiNx (silicon nitride), SiOx (silicon oxide) and SiOxNy (silicon oxynitride). The second film layer 1152 may be made of a resin material. The resin may be a thermoplastic resin or a thermoplastic resin, the thermoplastic resin may include an acrylic (PMMA) resin, and the thermosetting resin may include an epoxy resin.

[0186] It should be noted that the second film layer 1152 can be located in the area surrounded by the blocking structure 103, and the first film layer 1151 and the third film layer 1153 can cover the area surrounded by the blocking structure 103 and cover the blocking structure 103. That is, the orthographic projection of the blocking structure 103 on the base substrate 101 is located in the area covered by the encapsulation film layer 115, thereby ensuring that the encapsulation film layer 115 effectively encapsulates each structure located in the area surrounded by the blocking structure 103.

[0187] In the embodiment of the present application, the second film layer 1152 can be manufactured by ink jet printing (IJP) method, and the first film layer 1151 and the third film layer 1153 can be manufactured by chemical vapor deposition (CVD) method.

[0188] Fig.12 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. Fig.12 It can be seen that the display panel 10 may further include a driver integrated circuit 116 and a panel test circuit 117. The driver integrated circuit 116 and the panel test circuit 117 may be located in the first area 101b1 of the peripheral area 101b, and the driver integrated circuit 116 is away from the display area 101a relative to the panel test circuit 117. In addition, the first area 101b1 of the base substrate 101 may include a fanout bonding area 101b11, and the driver integrated circuit 116 and the panel test circuit 117 may be connected to the plurality of pixel units 102 through the fanout bonding area 101b11.

[0189] Furthermore, the display panel 10 may further include a reset (vinit) circuit 118. The reset circuit 118 may include a first sub-reset circuit 1181 and a second sub-reset circuit 1182, wherein the first sub-reset circuit 1181 is located in a third area 101b3 of the peripheral area 101b, and the second sub-reset circuit 1182 is located in a fourth area 101b4 of the peripheral area 101b. Furthermore, the first sub-reset circuit 1181 is located on a side of the first sub-driving circuit 1051 of the row driving circuit 105 close to the plurality of pixel units 102, and the orthographic projection of the first sub-reset circuit 1181 on the base substrate 101 may not overlap with the orthographic projection of the first sub-driving circuit 1051 on the base substrate 101. The second sub-reset circuit 1182 is located on a side of the second sub-driving circuit 1052 of the row driving circuit 105 close to the plurality of pixel units 102 , and the orthographic projection of the second sub-reset circuit 1182 on the substrate 101 may not overlap with the orthographic projection of the second sub-driving circuit 1052 on the substrate 101 .

[0190] Of course, the first sub-reset circuit 1181 may also be located on a side of the first sub-driving circuit 1051 away from the multiple pixel units 102, and the second sub-reset circuit 1182 may also be located on a side of the second sub-driving circuit 1052 away from the multiple pixel units 102. The embodiment of the present application does not limit the relative positions of the reset circuit 118 and the row driving circuit 105.

[0191] To summarize, an embodiment of the present application provides a display panel, which includes a blocking structure, at least one first power line and a row driving circuit that overlap in parts, thereby effectively reducing the total width of each structure located in the peripheral area, thereby reducing the width of the display panel frame, and facilitating the realization of a narrow-frame display panel.

[0192] Fig.13 is a flow chart of a method for preparing a display panel provided in an embodiment of the present application. The method can be used to prepare the display panel 10 provided in the above embodiment. Fig.13 , the method may include:

[0193] Step 201: Provide a substrate.

[0194] In the embodiment of the present application, when preparing the display panel, a base substrate 101 may be first obtained. The base substrate 101 may be a glass substrate or a flexible substrate. The base substrate 101 may have a display area 101a and a peripheral area 101b surrounding the display area 101a.

[0195] Step 202: forming a plurality of pixel units in the display area, and forming a blocking structure, at least one first power line and a row driving circuit in the peripheral area.

[0196] In an embodiment of the present application, the formed blocking structure 103 may surround the plurality of pixel units 102. The at least one first power line 104 may include a first portion 1041 and a second portion 1042. The first portion 1041 may be located on a side of the blocking structure 103 away from the plurality of pixel units 102, for receiving a first power signal. The second portion 1042 may surround the plurality of pixel units 102, and be connected to the first portion 1041 and the first electrode layer b3 in the plurality of pixel units 102, respectively. The row driving circuit 105 may be connected to the plurality of pixel units 102, for providing a driving signal to the plurality of pixel units 102.

[0197] It should be noted that, in step 202, a row driving circuit 105 may be first formed on the base substrate 101, and then at least one first power line 104 may be formed on a side of the row driving circuit 105 away from the base substrate 101. Then, a blocking structure 103 may be formed on a side of the first power line 104 away from the base substrate 101.

[0198] The row driving circuit 105 may be formed in the process of forming the thin film transistor 1021 in the pixel unit 102. The at least one first power line 104 may be formed after forming the thin film transistor 1021 in the pixel unit 102. The blocking structure 103 may be formed in the process of forming the second planar layer 111, the pixel defining layer 106 and the supporting layer 107.

[0199] In the embodiment of the present application, the orthographic projections of any two of the following structures on the base substrate 101 at least partially overlap: the blocking structure 103, the at least one first power line 104, and the row driving circuit 105. That is, the orthographic projection of the blocking structure 103 on the base substrate 101 at least partially overlaps with the orthographic projection of the at least one first power line 104 on the base substrate 101, the orthographic projection of the blocking structure 103 on the base substrate 101 at least partially overlaps with the orthographic projection of the row driving circuit 105 on the base substrate 101, and the orthographic projection of the at least one first power line 104 on the base substrate 101 at least partially overlaps with the orthographic projection of the row driving circuit 105 on the base substrate 101.

[0200] In summary, an embodiment of the present application provides a method for preparing a display panel. The display panel prepared by this method includes a blocking structure, at least one first power line and a row driving circuit that overlap each other, thereby effectively reducing the total width of each structure located in the peripheral area, thereby reducing the width of the display panel frame, and facilitating the realization of a narrow-frame display panel.

[0201] Fig.14is a flow chart of another method for preparing a display panel provided in an embodiment of the present application. This method can be used to prepare the display panel provided in the above embodiment. Fig.14 , the method may include:

[0202] Step 301: Provide a substrate.

[0203] In the embodiment of the present application, when preparing the display panel, a base substrate 101 may be first obtained. The base substrate 101 may be a glass substrate or a flexible substrate. The base substrate 101 may have a display area 101a and a peripheral area 101b surrounding the display area 101a.

[0204] Step 302: Form a flexible membrane layer, a barrier layer, a first buffer layer and an active layer in sequence on one side of the substrate.

[0205] In the embodiment of the present application, after the base substrate 101 is obtained, a flexible membrane layer 112 , a barrier layer 113 , a first buffer layer and an active layer may be sequentially formed on the base substrate 101 . Fig.15 Schematic diagram of an active layer provided in an embodiment of the present application. Fig.15 The active layer may include a plurality of patterns. The plurality of patterns may include a first active pattern a2 and a second active pattern c2. Fig.15 2 is a schematic diagram of a partial area of ​​the display panel where a row driving circuit is disposed, and thus only the second active pattern c2 in the row driving circuit is shown.

[0206] It should be noted that the flexible film layer 112 , the barrier layer 113 and the first buffer layer can cover the entire surface of the base substrate 101 , and therefore they are not shown in the drawings.

[0207] Step 303: forming a first gate insulating layer, a first gate layer, and a second gate insulating layer in sequence on a side of the active layer away from the substrate.

[0208] In the embodiment of the present application, after the active layer is formed, a first gate insulating layer, a first gate layer and a second gate insulating layer may be sequentially formed on one side of the base substrate 101 .

[0209] Fig.16 This is a schematic diagram of a first gate layer provided in an embodiment of the present application. Fig.17 1 is a schematic diagram of forming a first gate layer provided by an embodiment of the present application, wherein the first gate layer may include a plurality of patterns, including a first gate pattern a4 and a second gate pattern c4. Fig.16 and Fig.17FIG. 4 is a schematic diagram of a partial area of ​​a display panel where a row driving circuit is disposed, and thus only the second gate pattern c4 in the row driving circuit is shown.

[0210] And, reference Fig.17 The orthographic projection of the pattern in the active layer on the base substrate 101 may overlap with the orthographic projection of the pattern in the first gate layer on the base substrate 101 .

[0211] It should be noted that the first gate insulating layer and the second gate insulating layer can both cover the entire surface of the base substrate 101, so there is no need to Fig.16 and Fig.17 Shown in.

[0212] Step 304 : forming a second gate layer, a second buffer layer and an interlayer dielectric layer in sequence on a side of the second gate insulating layer away from the substrate.

[0213] In the embodiment of the present application, after forming the second gate insulating layer, a second gate layer, a second buffer layer and an interlayer dielectric layer may be formed in sequence on one side of the base substrate 101 .

[0214] Fig.18 This is a schematic diagram of a second gate layer provided in an embodiment of the present application. Fig.19 is a schematic diagram of forming a second gate layer provided by an embodiment of the present application, wherein the second gate layer may include a plurality of patterns, wherein the plurality of patterns include a third gate pattern c6.

[0215] Among them, reference Fig.18 and Fig.19 , the orthographic projection of the pattern in the second gate layer on the base substrate 101 may overlap with the orthographic projection of the pattern in the first gate layer on the base substrate 101. Furthermore, the orthographic projection of the pattern in the second gate layer on the base substrate 101 may also overlap with the orthographic projection of the pattern in the active layer on the base substrate 101.

[0216] Fig. 20 It is a schematic diagram of an interlayer dielectric layer provided in an embodiment of the present application. Fig.21 Schematic diagram of forming an interlayer dielectric layer provided by an embodiment of the present application. Fig. 20 and Fig.21 , the interlayer dielectric layer may have a plurality of vias. And, in order to facilitate the illustration of the various vias in the interlayer dielectric layer, Fig. 20 and Fig.21 Fill patterns are used to represent vias. Other areas without fill patterns are used to represent areas with solid material on the interlayer dielectric layer.

[0217] It should be noted that the shape of the second buffer layer can be the same as the shape of the interlayer dielectric layer, so the embodiments of the present application are not repeated here. In addition, the interlayer dielectric layer, the second buffer layer, the second gate insulating layer and the first gate insulating layer can all be formed with a first via, and the interlayer dielectric layer, the second buffer layer and the second gate insulating layer can all be formed with a second via. The first via can be used to allow the source and drain formed on the side of the interlayer dielectric layer away from the substrate to be connected to the active layer, and the second via can be used to allow the connection layer formed on the side of the interlayer dielectric layer away from the substrate to be connected to the second gate pattern in the first gate layer.

[0218] Step 305 : forming a source-drain layer on a side of the interlayer dielectric layer away from the substrate.

[0219] In the embodiment of the present application, after forming the interlayer dielectric layer, a source-drain electrode layer may be formed on the side of the interlayer dielectric layer away from the substrate. The source-drain electrode layer includes a source-drain electrode and a connection layer c9. The source-drain electrode includes a source electrode and a drain electrode spaced apart. The source electrode and the drain electrode may be connected to the active layer through the first via hole, respectively, and the connection layer c9 may be connected to the second gate pattern in the first gate layer through the second via hole.

[0220] in, Fig. 22 and Fig.23 FIG. 1 is a schematic diagram showing a partial area of ​​a display panel where a row driving circuit is disposed. Fig. 22 and Fig.23 Only the connection layer c9 included in the row driving circuit is shown.

[0221] Step 306: forming a passivation layer and a second planarization layer in sequence on a side of the source and drain electrode layer away from the substrate.

[0222] In the examples of this application, refer to Fig.24 and Fig.25 A passivation layer 110 may be formed on a side of the source and drain electrode layer away from the base substrate. Also, a second planarization layer 111 may be formed on a side of the passivation layer 110 away from the base substrate.

[0223] The passivation layer 110 and the second flat layer 111 may both have a third via hole (not shown in the figure), and the third via hole may be used to connect the electrode pattern of the anode layer formed on the side of the second flat layer 111 away from the base substrate to the drain.

[0224] and, Fig.24 and Fig.25 The fill pattern is used to represent the area without solid material in the passivation layer. Other areas without fill patterns are used to represent the area with solid material in the passivation layer. In addition, Fig.25A second planar layer is formed in a partial area of ​​each of the row driving circuits shown, and therefore the second planar layer is not separately illustrated in the drawings.

[0225] Step 307 : forming a first power line on a side of the second planar layer away from the base substrate.

[0226] In the embodiment of the present application, Fig.26 and Fig. 27 , a first power line 104 may be formed on a side of the second flat layer away from the base substrate. The first power line 104 may have at least one opening 104a, and each opening 104a may be used to expose a film layer located on a side of the first power line 104 close to the base substrate 101. Moreover, the opening 104a may be located in a region for forming the blocking structure 103.

[0227] For example, Fig.26 and Fig. 27 Three openings 104a are shown, and the three openings 104a are all located in the region of the second blocking dam 1032 used to form the blocking structure 103. Of course, the opening 104a in the first power line 104 can also be located in the region of the first blocking dam 1031 used to form the blocking structure 103, which is not limited in the embodiment of the present application.

[0228] Step 308: forming an anode layer on a side of the second planar layer away from the substrate.

[0229] In the embodiment of the present application, an anode layer may be formed on the side of the second flat layer away from the substrate. The anode layer may include electrode patterns of multiple light-emitting units. Each electrode pattern may be connected to the drain through the second flat layer and the third via hole in the passivation layer.

[0230] Step 309 , forming a first planarization layer, a pixel defining layer, a light emitting layer, a support layer and a first electrode layer in sequence on the side of the first power line and the anode layer away from the base substrate.

[0231] In the examples of this application, refer to Fig.28 and Fig.29 A first planar layer 108 may be formed on one side of the base substrate 101 . Furthermore, the third pattern 108 a in the first planar layer 108 may be located in a region for forming the second blocking dam 1032 in the blocking structure 103 . Fig.28 and Fig.29 In the figure, a fill pattern is used to indicate an area without solid material in the first flat layer 108. Other areas without a fill pattern are used to indicate an area with solid material in the first flat layer 108.

[0232] refer to Fig.30 and Fig.31, a pixel defining layer 106 may be formed on one side of the base substrate 101. The first pattern 106a in the pixel defining layer 106 may be used to form a region of the first blocking dam 1031 in the blocking structure 103, and the fourth pattern 106b in the pixel defining layer 106 may be used to form a region of the second blocking dam 1032 in the blocking structure. Fig.30 and Fig.31 In the figure, a filling pattern is used to represent an area without solid material in the pixel definition layer 106. Other areas without a filling pattern are used to represent an area with solid material in the pixel definition layer 106.

[0233] refer to Fig.32 and Fig.33 A support layer 107 may be formed on one side of the base substrate 101. The second pattern 107a in the support layer 107 may be used to form a region of the first barrier dam 1031 in the barrier structure 103, and the fifth pattern 107b in the support layer 107 may be used to form a region of the second barrier dam 1032 in the barrier structure. Fig.32 and Fig.33 In the figure, a filling pattern is used to represent the area with solid material in the support layer 107. Other areas without a filling pattern are used to represent the area without solid material in the support layer 107.

[0234] In addition, the portion of the pixel defining layer 106 located in the display area 101a may have multiple openings, each of which may be used to expose an electrode pattern b1 in the anode layer so that a light-emitting pattern b2 of the light-emitting layer subsequently formed in the opening can contact the electrode pattern b1, thereby realizing light emission of the pixel unit.

[0235] It should be noted that the light emitting layer and the first electrode layer are both located in the display area of ​​the base substrate 101 , and therefore are not illustrated in the drawings.

[0236] In summary, an embodiment of the present application provides a method for preparing a display panel. The display panel prepared by this method includes a blocking structure, at least one first power line and a row driving circuit that overlap each other, thereby effectively reducing the total width of each structure located in the peripheral area, thereby reducing the width of the display panel frame, and facilitating the realization of a narrow-frame display panel.

[0237] Fig.34 is a schematic diagram of the structure of a display device provided in an embodiment of the present application. Fig.34 It can be seen that the display device 00 may include a power supply component 40 and the display panel 10 provided in the above embodiment. The power supply component 40 may be used to supply power to the display panel 10.

[0238] Optionally, the display device may be an OLED display device, a liquid crystal display device, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator, or any other product or component with a display function.

[0239] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that: The display panel comprises: A base substrate, the base substrate having a display area and a peripheral area surrounding the display area; A plurality of pixel units, located in the display area; A blocking structure, located in the peripheral area and surrounding the plurality of pixel units; At least one first power line is located in the peripheral area, the at least one first power line includes a first portion and a second portion, the first portion is located on a side of the blocking structure away from the plurality of pixel units and is used to receive a first power signal, the second portion surrounds the plurality of pixel units and is electrically connected to the first portion and the first electrode layer in the plurality of pixel units, respectively; and a row driving circuit, located in the peripheral area, the row driving circuit being electrically connected to the plurality of pixel units and configured to provide driving signals to the plurality of pixel units; Wherein, the orthographic projections of any two of the following structures on the substrate at least partially overlap: the blocking structure, the at least one first power line, and the row driving circuit; The display panel further includes: at least one second power line located in the peripheral area, the second power line including a third portion, two fourth portions, a fifth portion and two sixth portions, the third portion being located on a side of the blocking structure close to the plurality of pixel units and electrically connected to the plurality of pixel units, the two fourth portions being located on a side of the third portion away from the plurality of pixel units and electrically connected to the third portion, the fifth portion being located on a side of the two fourth portions away from the plurality of pixel units and electrically connected to the two fourth portions, the two sixth portions being located on a side of the blocking structure away from the plurality of pixel units and used to receive a second power signal, and the two sixth portions being electrically connected to the fifth portion; The two fourth parts are symmetrically arranged with the axis of the base substrate as an axis, and the two sixth parts are symmetrically arranged with the axis of the base substrate as an axis, and the axis is parallel to the column direction of the plurality of pixel units.

2. The display panel according to claim 1, characterized in that: The peripheral area includes: a first area and a second area arranged oppositely and in parallel, and a third area and a fourth area arranged oppositely and in parallel, wherein the extension direction of the first area is perpendicular to the extension direction of the third area; The first portion is located in the first area, and the second portion is located in the second area, the third area, and the fourth area.

3. The display panel according to claim 2, characterized in that: The row driving circuit includes: a first sub-driving circuit and a second sub-driving circuit, the first sub-driving circuit is located in the third area, and the second sub-driving circuit is located in the fourth area.

4. The display panel according to claim 3, characterized in that: The first sub-driving circuit and the second sub-driving circuit both include: a light-emitting control driving circuit, a first type of driving circuit and a second type of driving circuit, the light-emitting control driving circuit is used to provide a light-emitting control signal, and the first type of driving circuit and the second type of driving circuit are both used to provide a scanning signal; The orthographic projection of the first power line on the base substrate at least partially overlaps with the orthographic projection of the light emitting control driving circuit on the base substrate, and the orthographic projection of the blocking structure on the base substrate at least partially overlaps with the orthographic projection of the light emitting control driving circuit on the base substrate.

5. The display panel according to claim 1, characterized in that: The blocking structure comprises: a first blocking dam and a second blocking dam; The first barrier dam is closer to the plurality of pixel units than the second barrier dam, and a thickness of the first barrier dam is smaller than a thickness of the second barrier dam.

6. The display panel according to claim 5, characterized in that: The first barrier dam comprises: a first pattern and a second pattern sequentially stacked in a direction away from the base substrate; The second blocking dam comprises: a third pattern, a fourth pattern and a fifth pattern stacked in sequence in a direction away from the base substrate; The first pattern and the fourth pattern are located on a pixel defining layer of the display panel, the second pattern and the fifth pattern are located on a supporting layer of the display panel, and the third pattern is located on a first planar layer of the display panel.

7. The display panel according to any one of claims 1 to 6, characterized in that: The first power line comprises: two first parts and one second part; The two first parts are symmetrically arranged with the axis of the substrate as the axis, one end of the second part is connected to one of the first parts, and the other end of the second part is connected to another first part, wherein the axis is parallel to the column direction of the multiple pixel units.

8. The display panel according to any one of claims 1 to 6, characterized in that: One end of the at least one second power line is located at a side of the blocking structure away from the plurality of pixel units and is used to receive a second power signal, and the other end is located at a side of the blocking structure close to the plurality of pixel units and is electrically connected to the plurality of pixel units; The orthographic projection of the at least one second power line on the base substrate at least partially overlaps with the orthographic projection of the blocking structure on the base substrate.

9. The display panel according to any one of claims 1 to 6, characterized in that: The first power line comprises: two first parts, the two first parts are symmetrically arranged with the axis as the axis; The distance between the sixth portion and the first portion, which are located on the same side of the axis, is smaller than the distance between the sixth portion and the axis.

10. The display panel according to claim 9, characterized in that: The third portion and the fifth portion both extend along a row direction, and the two fourth portions and the two sixth portions both extend along a column direction.

11. The display panel according to any one of claims 1 to 6, characterized in that: An orthographic projection of each of the fourth portions on the substrate at least partially overlaps with an orthographic projection of the blocking structure on the substrate.

12. The display panel according to any one of claims 1 to 6, characterized in that: Each of the pixel units comprises: a thin film transistor and a light emitting unit stacked in sequence in a direction away from the substrate; The thin film transistor comprises: a first buffer layer, a first active pattern, a first gate insulating layer, a first gate pattern, a second gate insulating layer, a second buffer layer, an interlayer dielectric layer, and a source and a drain electrode stacked in sequence in a direction away from the base substrate, wherein the source and the drain electrode comprise a source electrode and a drain electrode arranged at intervals, and the source electrode and the drain electrode are both electrically connected to the first active pattern; The light-emitting unit comprises: an electrode pattern, a light-emitting pattern and the first electrode layer which are sequentially stacked in a direction away from the base substrate; the electrode pattern is located in the second electrode layer and is electrically connected to the drain.

13. The display panel according to claim 12, characterized in that: The row driving circuit comprises: the first buffer layer, the second active pattern, the first gate insulating layer, the second gate pattern, the second gate insulating layer, the third gate pattern, the second buffer layer, the interlayer dielectric layer, and a connection layer which are sequentially stacked in a direction away from the base substrate, and the connection layer is electrically connected to the first gate pattern; The first active pattern and the second active pattern are located in the same layer, the first gate pattern and the second gate pattern are located in the same layer, and the source and drain and the connection layer are located in the same layer.

14. The display panel according to claim 13, characterized in that: The display panel further includes: a passivation layer, a first flat layer and a second flat layer; The passivation layer is located on a side of the source and drain away from the substrate, the second flat layer is located on a side of the passivation layer away from the substrate, the at least one first power line is located on a side of the second flat layer away from the substrate, and the first flat layer is located on a side of the at least one first power line away from the substrate.

15. The display panel according to any one of claims 1 to 6, characterized in that: The target portion of the at least one first power line has at least one opening; The orthographic projection of the target portion on the substrate overlaps with the orthographic projection of the blocking structure on the substrate.

16. The display panel according to any one of claims 1 to 6, characterized in that: The display panel further includes: a power driving circuit, the power driving circuit being located in the peripheral area and located on a side of the first portion away from the blocking structure; The power driving circuit is electrically connected to the first part, and is used to provide the first power signal to the at least one first power line.

17. The display panel according to any one of claims 1 to 6, characterized in that: The display panel further comprises: a packaging film layer; The packaging film layer is located on a side of the plurality of pixel units away from the substrate, and the packaging film layer covers the area surrounded by the blocking structure.

18. A method for preparing a display panel, characterized in that: The method is used to prepare the display panel according to any one of claims 1 to 17; the method comprises: Providing a base substrate, the base substrate having a display area and a peripheral area surrounding the display area; Forming a plurality of pixel units in the display area, and forming a blocking structure, at least one first power line and a row driving circuit in the peripheral area; The blocking structure surrounds the plurality of pixel units; the at least one first power line includes a first portion and a second portion, the first portion is located on a side of the blocking structure away from the plurality of pixel units, and is used to receive a first power signal, and the second portion surrounds the plurality of pixel units and is electrically connected to the first portion and the first electrode layer in the plurality of pixel units, respectively; the row driving circuit is electrically connected to the plurality of pixel units, and is used to provide driving signals to the plurality of pixel units; Orthographic projections of any two of the following structures on the substrate at least partially overlap: the blocking structure, the at least one first power line, and the row driving circuit.

19. A display device, characterized in that: The display device comprises: a power supply component and a display panel according to any one of claims 1 to 17; The power supply component is used to supply power to the display panel.

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