A method and system for detecting a superconducting device at room temperature

Abstract

The application provides a kind of superconducting device normal temperature detection method and system, comprising: selecting reference superconducting device, determining the normal temperature resistance value of reference superconducting device and the working state under low temperature;If the working state of reference superconducting device under low temperature condition is normal, the normal temperature resistance value of reference superconducting device is taken as reference value;If the state of reference superconducting device is not normal, the reference superconducting device is reselected;Under normal temperature condition, the normal temperature resistance value of the measured superconducting device is tested and compared with the reference value, to judge whether the measured superconducting device is damaged or not.The application utilizes the normal temperature characteristics of superconducting device for detection, and the detection method is fast and efficient, which can be applied to batch detection of superconducting chips on wafer.

Description

Technical Field

[0001] This invention relates to the field of superconducting device testing, and in particular to a room-temperature testing method and system for superconducting devices. Background Technology

[0002] Superconductors, also known as superconducting materials, are materials that exhibit zero electrical resistance and diamagnetism at extremely low temperatures. The temperature at which superconductors exhibit superconductivity is called the superconducting critical temperature. Based on their superconducting critical temperatures, superconducting materials can be classified into high-temperature superconductors and low-temperature superconductors. When a thin insulating layer is placed between two superconductors, electrons can flow between them, a phenomenon known as the Josephson effect, a macroscopic quantum phenomenon. The most common Josephson junction, also called a tunnel junction, is formed through a "sandwich" structure of superconductor-insulator-superconductor (SIS). Besides this, Josephson junctions also have point-contact, narrow-bridge, bicrystalline grain boundary, and tunnel junction structures. Combining a number of Josephson junctions with superconducting inductance and different electronic components can construct different types of superconducting devices. For example, superconducting quantum interference devices (SQUIDs) include DC SQUIDs and radio-frequency SQUIDs, composed of varying numbers of Josephson junctions. These devices are widely used in various fields, including weak magnetic exploration. For high-temperature superconducting materials, liquid nitrogen (77K) is a common cryogenic medium; while for low-temperature superconducting materials, liquid helium (4.2K) is more commonly used.

[0003] However, these devices are all fabricated using Josephson junctions based on superconducting materials. During normal operation, they need to be cooled below the critical temperature of the superconductor, a process that requires significant resources. During wafer substrate manufacturing and testing, to verify whether chips containing superconducting devices meet standards, the device under test (DUT) must be fixed on a specialized PCB substrate, test electrodes are brought out using wire bonding, and then mounted in a custom test probe. The device is then slowly cooled until it reaches the temperature required for normal operation, and after testing at that temperature, it undergoes a slow heating process. This entire testing process is a thermal cycling process, and performing one thermal cycle on a single chip consumes a considerable amount of time. Furthermore, the testing process is quite complex, and performing this test on every single chip is extremely tedious. In addition, due to limitations in thin film growth and photolithography processes, the chips produced in batches on a wafer cannot be 100% identical. Assuming a single chip diameter of 5 mm, a 4-inch silicon wafer can integrate 250 chips simultaneously. However, these 250 chips cannot be guaranteed to be completely consistent during manufacturing. Therefore, testing and analysis of all chips on the wafer are necessary. However, this hot-and-cold cycling method for chip testing is not only inefficient but also wasteful of resources. Increasing the number of chips tested simultaneously through additional extended test channels would further complicate the testing system and significantly increase costs.

[0004] For the reasons mentioned above, this invention provides a room-temperature detection method and system for superconducting devices, which can effectively improve detection efficiency and reduce detection costs.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a room temperature detection method and system for superconducting devices, which solves the problem that the chips of superconducting devices are repeatedly subjected to hot and cold cycles, resulting in significant cost waste and low efficiency.

[0007] To achieve the above and other related objectives, the present invention provides a room-temperature detection method for superconducting devices, comprising at least:

[0008] S1. Select a reference chip and verify whether the reference chip is functioning normally under low temperature conditions. If the reference chip is functioning normally, then use the reference chip as a reference. If the reference chip is not functioning normally, then select a new reference chip.

[0009] S2. Measure the room temperature resistance value of the reference superconducting device on the reference chip;

[0010] S3. Measure the room temperature resistance value of the superconducting device under test on the chip under test; the reference superconducting device and the superconducting device under test have the same structure and parameters and are respectively set on two chips;

[0011] S4. The room temperature resistance value of the superconducting device under test is compared with the room temperature resistance value of the reference superconducting device. If the error value is less than or equal to the preset value, the chip under test is determined to be good; if the error value is greater than the preset value, the chip under test is determined to be defective.

[0012] To achieve the above and other related objectives, the present invention also provides a room-temperature detection method for superconducting devices, comprising at least:

[0013] S1. Select a reference chip and measure the room temperature resistance value of the reference superconducting device on the reference chip;

[0014] S2. Verify whether the state of the reference chip is normal under low temperature conditions. If the state of the reference chip is normal, use the room temperature resistance value of the reference chip as the reference value. If the state of the reference chip is abnormal, return to step S1 and select a new reference chip.

[0015] S3. Measure the room temperature resistance value of the superconducting device under test on the chip under test; the reference superconducting device and the superconducting device under test have the same structure and parameters and are respectively set on two chips;

[0016] S4. The room temperature resistance value of the superconducting device under test is compared with the room temperature resistance value of the reference superconducting device. If the error value is less than or equal to the preset value, the chip under test is determined to be good; if the error value is greater than the preset value, the chip under test is determined to be defective.

[0017] Optionally, in step S2, if the reference chip is in normal condition under low temperature conditions, the room temperature resistance value of the reference superconducting device is measured again at room temperature and compared with the room temperature resistance value of the reference superconducting device in step S1. If the error value is less than or equal to the preset deviation value, the room temperature resistance value of the reference chip in step S1 is used as the reference value, and step S3 is executed; if the error value is greater than the preset deviation value, step S1 is executed again.

[0018] Optionally, the preset value is less than or equal to 3% of the room temperature resistance of the reference superconducting device.

[0019] Optionally, the preset deviation value is less than or equal to 3% of the room temperature resistance value of the reference superconducting device.

[0020] Optionally, the resistance value at room temperature can be measured using the four-terminal probe method.

[0021] Optionally, electrostatic protection can be applied to the test chip before and after measuring the resistance value at room temperature.

[0022] This invention provides a room temperature detection system for superconducting devices, used to implement the above-mentioned room temperature detection method for superconducting devices, comprising at least: a room temperature acquisition module, a low temperature testing module, and a data processing module;

[0023] The room temperature acquisition module is used to acquire the room temperature resistance value of the reference superconducting device and the room temperature resistance value of the superconducting device under test and transmit them to the data processing module.

[0024] The low-temperature testing module is used to test the low-temperature operating state of the reference chip;

[0025] The data processing module is connected to the room temperature acquisition module and the low temperature test module, and compares the room temperature resistance value of the reference superconducting device and the room temperature resistance value of the superconducting device under test based on the low temperature test results.

[0026] Optionally, the ambient temperature acquisition system module includes a test circuit and an electrostatic protection circuit;

[0027] The electrostatic discharge (ESD) protection circuit is connected in parallel across the two ends of the chip; before and after measuring the resistance value at room temperature, the ESD protection circuit is connected in parallel with the chip and then in series with the test circuit; when measuring the resistance value at room temperature, the two ends of the ESD protection circuit are grounded, and the chip is connected in series with the test circuit.

[0028] Optionally, the electrostatic protection circuit is configured as a transient voltage suppression diode.

[0029] Optionally, the test circuit is a four-terminal measurement unit; the four-terminal measurement unit includes a constant current source and four probes.

[0030] As described above, the room-temperature detection method and system for superconducting devices of the present invention have the following beneficial effects:

[0031] 1. The room temperature detection method and system for superconducting devices of the present invention utilize the room temperature characteristics of superconducting devices for detection. The detection method is fast and efficient, applicable to the batch detection of superconducting chips on wafers, and does not require maintaining low temperature conditions. It eliminates the testing process of thermal cycling, reduces the loss of equipment and media for maintaining low temperature conditions, such as liquid nitrogen, and greatly saves costs.

[0032] 2. The room temperature detection method and system for superconducting devices of the present invention can quickly detect and classify devices, and is simple to operate and easy to promote. Attached Figure Description

[0033] Figure 1 The flowchart shown is a method for room temperature detection of a superconducting device.

[0034] Figure 2 The diagram shows the equivalent circuit of the first Josephson junction.

[0035] Figure 3 The diagram shows a schematic of a superconducting device tested using the four-terminal probe method.

[0036] Figure 4 The diagram shows the equivalent circuit of the electrostatic discharge protection circuit.

[0037] Figure 5 The diagram shows a room-temperature detection system for a superconducting device.

[0038] Component designation explanation

[0039] 1. Room Temperature Detection System for Superconducting Devices

[0040] 11. Room temperature acquisition module

[0041] 111 probe

[0042] 12 Low Temperature Test Module

[0043] 13 Data Processing Module

[0044] 2 chips

[0045] 21 First Josephson knot

[0046] 211 First Superconductor

[0047] 212 Insulation layer

[0048] 213 Second Superconductor

[0049] 22 DC superconducting quantum interference device

[0050] 221 Second Josephson Node

[0051] 222 Third Josephson knot

[0052] 3. Wafer Detailed Implementation

[0053] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] Please see Figures 1-5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0055] Example 1

[0056] This embodiment provides a room-temperature detection method for superconducting devices, including:

[0057] S1. Select a reference chip and verify whether the reference chip is in normal condition under low temperature conditions. If the reference chip is in normal condition, use the reference chip as a reference. If the reference chip is not in normal condition, select a new reference chip.

[0058] S2. Measure the room temperature resistance value of the reference superconducting device on the reference chip;

[0059] S3. Measure the room temperature resistance value of the superconducting device under test on the chip under test; the reference superconducting device and the superconducting device under test have the same structure and parameters and are respectively set on two chips;

[0060] S4. The room temperature resistance value of the superconducting device under test is compared with the room temperature resistance value of the reference superconducting device. If the error value is less than or equal to the preset value, the chip under test is determined to be good; if the error value is greater than the preset value, the chip under test is determined to be defective.

[0061] Specifically, in step S1, the reference chip is selected randomly. In practical applications, other selection methods can be used, including but not limited to selecting a chip for measuring a specific location, such as the outermost or center chip of the wafer. The reference superconducting chip is verified to be functioning correctly under low-temperature conditions. If the reference superconducting chip is functioning correctly, it is used as a reference; if the reference chip is not functioning correctly, a new reference chip is selected. Figure 3As shown, a superconducting chip 2 is selected on wafer 3. The chip 2 is verified to function normally under low-temperature conditions. If chip 2 functions normally, it is used as a reference; if it does not function normally, a new reference chip is selected. The chip verification methods include, but are not limited to, testing the test electrodes of the superconducting device using wire bonding under low-temperature conditions, and conducting tests using customized test probes. Specific tests can measure the resistance, diamagnetism, and magnetic induction properties of the superconducting device to verify its physical parameters; they can also test the circuit potential and other circuit parameters of the superconducting chip to ensure they are normal; and they can test the functionality of the entire or partial circuit of the superconducting chip through wire bonding. In addition, additional test channels can be used for testing. Theoretically, any low-temperature testing technique that can verify the normal function of the reference chip, i.e., a testing method that fulfills the predetermined design function, falls within the protection scope of this embodiment.

[0062] Specifically, in step S2, the room-temperature resistance of the reference superconducting device on reference chip 2 is measured. The measurement of the room-temperature resistance utilizes the characteristics of a Josephson junction. The most common Josephson junction is a "sandwich" structure consisting of a superconductor-insulator-superconductor (SIS). The Josephson effect refers to the phenomenon where a thin insulating layer is placed between two superconductors, allowing electrons to flow between them; this is a macroscopic quantum phenomenon. Besides the Josephson junction with an insulating layer in the middle, there are other configurations of Josephson junctions, such as the "sandwich" structure with a semiconductor layer in the middle. The testing methods and principles for other Josephson junction structures are the same as those for the "sandwich" structure of the SIS structure. This embodiment uses the SIS "sandwich" structure as an example; other configurations of Josephson junctions are similar and will not be described in detail. In this embodiment, as... Figure 2As shown, the first Josephson junction 21 is composed of a first superconductor 211, an insulating layer 212, and a second superconductor 213. Both the first superconductor 211 and the second superconductor 213 are made of superconducting materials, which exhibit zero resistance and diamagnetism at extremely low temperatures. Therefore, it is often necessary to utilize these two characteristics of superconductors in device fabrication. In practice, the first superconductor 211 and the second superconductor 213 are mostly chosen as alloy-type superconducting materials. These materials behave like normal metals at room temperature and also have a certain resistivity; at low temperatures, they exhibit superconducting zero-resistance characteristics. In the "sandwich" structure of the first Josephson junction 21, that is, the structure of the first superconductor 211-insulating layer 212-second superconductor 213, the insulating layer 212 is relatively thin. Under ideal conditions, when a voltage is applied across the two ends of the first Josephson junction 21, the extremely thin insulating layer 212 will undergo quantum tunneling, allowing current to pass through, making the first Josephson junction 21 behave as a conductor at room temperature. Therefore, the resistance of the conductor can be obtained using the voltage-current relationship. Fabricating superconducting chips on a wafer involves creating a Josephson junction with a specific three-dimensional structure on a substrate. Besides the Josephson junction, leads and electrodes are also fabricated as leads. Since the resistance of the leads and electrodes is the normal resistance of the superconducting material, they can be considered as conductors. Furthermore, if the Josephson junction is considered a normal conductor at room temperature, then superconducting devices composed of a single Josephson junction or multiple Josephson junctions connected in series or parallel or through quantum effects can all be considered normal conductors. Here, superconducting devices composed of multiple Josephson junctions include, but are not limited to, DC-SQUIDs and RF-SQUIDs. Any superconducting device containing a Josephson junction that can be considered a conductor at room temperature can be considered a room-temperature conductor and falls within the scope of this embodiment. For example, ... Figure 3 As shown, the closed loop formed by the parallel connection of the second Josephson junction 221 and the third Josephson junction 222 constitutes the DC superconducting quantum interference device 22. Under ideal conditions, the DC superconducting quantum interference device 22 is considered a normal conductor at room temperature, and its resistance can be obtained using the voltage-current relationship.

[0063] As an example, the four-terminal probe method is used to measure the resistance value at room temperature. Figure 3As shown, the four-terminal probe method uses four equally spaced probes anchored to the surface of a superconducting device. A constant current source provides a small current to two probes, and the voltage V between the other two probes is measured. In this embodiment, four probes are led out from the two ends of the DC superconducting quantum interference device 22, consisting of two current probes and two voltage probes. The two current probes are located at opposite ends of the device, and the two voltage probes are also located at opposite ends of the device, meaning that a single current probe and a single voltage probe are paired and located on the same side of the device. A constant current source is added to the superconducting device, and the voltages are measured by the two voltage probes to obtain two voltages V. + V - And read the two current values ​​I from the two current probes. + I - Since the polarity of components on the same side is the same, the resistance can be obtained using the voltage-current relationship: R = V. + -V - / I + -I - Compared to other testing methods, the four-terminal probe method can better detect the resistance value of a device and avoids introducing additional resistance that could lead to incorrect chip identification. Because of unavoidable errors during the testing process, such as those from the testing equipment, there will be some deviation in the resistance value compared to room temperature. Introducing additional deviations such as resistance could lead to misidentification of the chip.

[0064] Specifically, in step S3, the room-temperature resistance of the superconducting device under test (DUT) on the chip under test is measured. The reference superconducting device and the DUT have identical structures and parameters and are respectively located on two chips. Generally, chips with completely identical structures are manufactured on the same wafer, including the internal circuit structure; the structure, materials, and dimensions of each basic unit are completely identical, which can be interpreted as identical. In practical applications, it is also possible to manufacture multiple chips with different structures on the same wafer. For example, superconducting chips based on DC superconducting quantum interference devices (QFIDs) and superconducting chips based on radio frequency QFIDs may be manufactured on the same wafer. In this case, when testing the DUT, it is necessary to select a chip that corresponds to the reference chip (with identical circuit structure, process, and design parameters), such as... Figure 3 As shown, reference chip 2 was selected on wafer 3 to test the DC superconducting quantum interference device 22 on reference chip 2. Therefore, when performing step 3, it should be considered that the chip under test has the same structure and parameters. Besides the DC superconducting quantum interference device needing to be identical, other parts of the reference chip and the chip under test, such as the remaining wires and resistors, should also have the same structure and parameters.

[0065] Specifically, in step S4, the room-temperature resistance value of the superconducting device under test is compared with that of the reference superconducting device. If the error value is less than or equal to a preset value, the chip under test is determined to be a good product; if the error value is greater than the preset value, the chip under test is determined to be a defective product. For example, the preset value is less than or equal to 3% of the room-temperature resistance value of the reference superconducting device. That is, when the room-temperature resistance value of the chip under test is 0.97 to 1.03 times that of the reference chip, the chip under test is considered normal and a good product; if the room-temperature resistance value of the chip under test is less than 0.97 times that of the reference chip, or greater than 1.03 times that of the reference chip, the chip under test is determined to be abnormal and a defective product. In fact, during the testing of superconducting devices using the four-terminal probe method, the overall resistance of the device includes not only the resistance of the Josephson junction as a whole, but also the lead resistance and electrode resistance. Lead resistance and electrode resistance are the normal resistance of superconducting materials, and their resistivity remains constant at a certain temperature. Their related dimensions can also be precisely controlled by micro-nano fabrication technology. According to the resistance law R = ρL / S (where ρ is resistivity, L is conductor length, and S is conductor cross-sectional area), the lead resistance and electrode resistance of two superconducting devices remain essentially unchanged during room-temperature resistivity testing. However, the barrier layer formed by the insulating layer on the Josephson junction, grown between the two superconducting films, is affected by the superconducting films, including their surface roughness. Furthermore, in-plane micro-short circuits (pin holes) can also cause changes in the barrier layer resistance. Therefore, the resistivity of the barrier layer cannot be guaranteed to be completely uniform; that is, in the resistance law R = ρL / S, ρ may differ in different superconducting devices, ultimately leading to inconsistencies between the reference resistance and the resistance of the superconducting device being tested. Simultaneously, due to the presence of film roughness, electrostatic discharge can also break down the barrier layer, causing micro-short circuits and further altering the barrier layer resistance. Therefore, by comparing the room-temperature resistance value of the reference superconducting device with that of the tested superconducting device, not only can the consistency of the chip be identified, including the chip type and whether the chips are manufactured consistently, but it can also be determined whether the chip has been damaged due to static electricity or other reasons, becoming an abnormal chip. In this embodiment, considering temperature fluctuations and errors in testing instruments, a resistance variation range of 3% is considered to indicate that the chip is consistent and undamaged. It should be noted that the actual resistance variation range can be set according to actual conditions. That is, the preset value is less than 3% of the room-temperature resistance value of the reference superconducting device. The accuracy of the range can be varied according to the required precision, such as the surface roughness of the barrier layer in the specific manufacturing process, including but not limited to specifying variation ranges of 1%, 1.5%, 1.75%, 2%, 2.25%, and 2.5%. This range is relatively small, so it is necessary to avoid introducing additional resistance or leads during the testing of the room-temperature resistance value, which could lead to deviations in the final chip.

[0066] Specifically, such as Figure 4 As shown, electrostatic discharge (ESD) protection is implemented for the test chip before and after measuring the room temperature resistance value. The ESD protection circuit is set up to protect the chip from ESD. It is turned on before and after the room temperature resistance value measurement process to avoid ESD shocks caused during operation; and turned off during the room temperature resistance value measurement process.

[0067] like Figure 3 As shown, by executing S1 to S4, the detection of a single superconducting device under test can be completed. When measuring other superconducting devices, steps S3 and S4 can be repeatedly executed based on S1 to S4, continuously comparing the measured room-temperature resistance value with the reference value of the reference superconducting device, until all superconducting devices on a single chip on a single wafer 3 have been tested and obtained corresponding results, achieving a rapid screening effect. Compared to the need to maintain a low temperature for detecting individual superconducting devices or chips containing superconducting devices under low-temperature conditions, and the complexity of the low-temperature testing procedure, this invention saves on the detection procedure and avoids the waste of resources for maintaining low-temperature conditions.

[0068] It should be noted that this embodiment provides a room-temperature detection method for superconducting devices, all based on comparing the room-temperature resistance values ​​of the superconducting devices on the chip. In practical applications, multiple superconducting devices may be set on a single chip. During actual testing, one superconducting device can be detected through the lead wire. When testing other chips, the corresponding superconducting device at the corresponding location needs to be detected. For example, if a reference chip is selected, which has a DC superconducting quantum interference device (CQFID) and a radio frequency quantum interference device (RFQFID), and the room-temperature resistance value is measured using the CQFID as the reference superconducting device, then when testing the chip under test, the room-temperature resistance value of the corresponding CQFID should be measured. Similarly, if the room-temperature resistance value is measured using the RFQFID as the reference superconducting device, then the room-temperature resistance value of the corresponding RFQFID should also be measured when testing the chip under test. Furthermore, if there are multiple superconducting devices with the same structure on the same chip, the reference superconducting device can be arbitrarily selected. However, when testing the chip under test, the superconducting device at the corresponding location must be selected. In other words, during rapid chip testing, detecting whether a portion is damaged can quickly achieve the testing objective. Because superconducting devices are easily damaged during production and testing in practical use, detecting damage to the superconducting device can quickly determine whether the chip is damaged. In other words, detecting damage to a part of the chip can achieve rapid detection. Therefore, after selecting the room-temperature resistance value of one superconducting device on a chip as a reference, all other chips should be tested using this superconducting device as the standard. For example, if a reference chip is selected with three DC superconducting quantum interference devices (SQFIDs) spaced apart along a certain direction, and the middle SQFID is selected to test the room-temperature resistance value, then the chip under test should also have three SQFIDs spaced apart along a certain direction, and the corresponding middle SQFID should be selected. Selecting a superconducting device at the same corresponding position avoids inaccurate room-temperature resistance values ​​due to differences in the surrounding circuitry or even lead lengths. The room-temperature detection method for superconducting devices provided in this embodiment is relatively fast, therefore, the detection is based on a single superconducting device on the chip. For more precise testing, multiple superconducting devices can be tested separately. This involves setting standards for multiple superconducting devices on a reference chip and measuring the room-temperature resistance of the corresponding superconducting devices on the chip under test. The room-temperature resistance values ​​of the devices at corresponding locations are then compared. In reality, testing just one device is sufficient for rapid screening.In large-scale manufacturing, wafer fabrication employs a tape-out process, similar to a production line strictly adhering to the established process. Therefore, when batch-testing wafers from different batches but with the same structural design, the room-temperature resistance value of a reference superconducting device on a reference chip can be used as a reference to test all chips with the same structure on other wafers of the same type from different batches, achieving industrial-scale testing. However, in industrial applications, if the initial tape-out or process parameters change significantly, or the chip itself is adjusted, a new reference chip needs to be selected, meaning this method needs to be re-executed.

[0069] Example 2

[0070] The difference between this embodiment and Embodiment 1 is that: in this embodiment, the room temperature resistance value of the reference superconducting device of the reference chip was first measured, and then the reference chip was subjected to low temperature testing.

[0071] like Figure 1 As shown, the room-temperature detection method for a superconducting device provided in this embodiment includes at least:

[0072] S1. Select a reference chip and measure the room temperature resistance value of the reference superconducting device on the reference chip;

[0073] S2. Verify whether the reference chip is functioning normally under low temperature conditions. If the reference chip is functioning normally, use the room temperature resistance value of the reference chip as the reference value. If the reference chip is not functioning normally, return to step S1 and select a new reference chip.

[0074] S3. Measure the room temperature resistance value of the superconducting device under test on the chip under test; the reference superconducting device and the superconducting device under test have the same structure and parameters and are respectively set on two chips;

[0075] S4. The room temperature resistance value of the superconducting device under test is compared with the room temperature resistance value of the reference superconducting device. If the error value is less than or equal to the preset value, the chip under test is determined to be good; if the error value is greater than the preset value, the chip under test is determined to be defective.

[0076] Specifically, in step S2, if the reference chip is functioning normally under low-temperature conditions, the room-temperature resistance value of the reference superconducting device is measured again at room temperature to compare it with the room-temperature resistance value of the reference superconducting device measured in step S1. If the error value is less than or equal to a preset deviation value, the room-temperature resistance value of the reference chip in step S1 is continued to be used as the reference value. The preset deviation value is less than or equal to 3% of the room-temperature resistance value of the reference superconducting device. The error range can be designed according to the required accuracy, including but not limited to a range of 1%, 1.5%, 1.75%, 2%, 2.25%, and 2.5%. The preset deviation value and the preset value can be set the same in actual use, such as both being 3%, or they can be different, depending on the required accuracy. In this embodiment, step S1 is performed at room temperature, step S2 is performed under low-temperature conditions, and step S3 should return to room temperature. The reference superconducting device is equivalent to undergoing two tests at room temperature, one before the low-temperature test and one after the low-temperature test. If the room temperature resistance values ​​measured in the two tests differ significantly, exceeding the preset deviation value, there are two possible reasons: First, at least one of the room temperature measurement values ​​may have been incorrect, making it impossible to determine the accurate room temperature resistance value; second, the reference superconducting device may have been damaged after completing the temperature change process from low to high temperature following steps S2 and S3. Since the specific reason for the change in reference resistance is uncertain, step S1 is executed again to select a new reference chip.

[0077] The difference between this embodiment and Embodiment 1 lies in the execution order. The fundamental principles and methods have been described above and will not be repeated here.

[0078] Example 3

[0079] like Figure 5 As shown, this embodiment also provides a room temperature detection system for superconducting devices, used to implement the above-described room temperature detection method for superconducting devices.

[0080] like Figure 5 As shown, the room temperature detection system for superconducting devices includes: a room temperature acquisition module 11, a low temperature testing module 12, and a data processing module 13.

[0081] Specifically, the room temperature acquisition module 11 is used to acquire the room temperature resistance value of the reference superconducting device and the room temperature resistance value of the superconducting device under test and transmit them to the data processing module 13.

[0082] Specifically, the room temperature acquisition module 11 includes a test circuit and an electrostatic discharge (ESD) protection circuit. The ESD protection circuit protects the test chip before and after measuring the room temperature resistance value. The ESD protection circuit is connected in parallel across the chip. Before and after measuring the room temperature resistance value, the ESD protection circuit and the chip are connected in parallel as a single unit, and connected in series with the test circuit. When measuring the room temperature resistance value, one end of the ESD protection circuit is grounded, and the chip and the test circuit are connected in series. In this embodiment, the ESD protection circuit is implemented through ESD protection circuits including but not limited to transient voltage suppression diodes: when the chip under test is connected to the test circuit for room temperature resistance measurement, the ESD protection circuit is disconnected, which can avoid interference with the test value of the test circuit; when the chip under test does not need to be measured for room temperature resistance, the ESD protection circuit is connected, which can avoid chip damage caused by testing, especially electrostatic shocks that may be introduced by human operation.

[0083] As an example, such as Figure 3 As shown, the test circuit uses a four-terminal measurement unit; the four-terminal measurement unit includes a constant current source and four probes 111. It is mainly used to collect the room-temperature resistance value of the superconducting device. In this embodiment, the four-terminal measurement unit includes at least one constant current source and four probes 111; the four probes 111 are evenly spaced and anchored to the surface of the superconducting device. The constant current source provides a small current to two probes, and then the voltage V between the other two probes is measured. The four probes are divided into two current probes and two voltage probes. The two current probes are located at both ends of the device, and the two voltage probes are also located at both ends of the device. A constant current source is added to the superconducting device, and the voltages are measured by the two voltage probes to obtain the two voltages V. + V - And read the two current values ​​I from the two current probes. + I - The resistance can be obtained using the voltage-current relationship: R = V + -V - / I + -I - .

[0084] Specifically, the low-temperature test module 12 tests the low-temperature operating status of the reference chip and the chip under test. In the actual testing process, testing can be performed through lead wire testing or by adding additional channels. The actual testing methods and principles have been discussed above and will not be repeated here.

[0085] Specifically, the data processing module 13 processes the data from the room temperature acquisition module 11, comparing the room temperature resistance value of the reference superconducting device with that of the superconducting device under test. In this embodiment, after acquiring the room temperature resistance value of the reference superconducting device, the data processing module receives a signal sent by the low-temperature testing module 12. If the low-temperature testing module 12 sends a signal indicating that the test is qualified, the room temperature resistance of the reference superconducting device is set as the reference value, and an error value of 3% of this reference value is set. If a signal indicating that the test is unqualified is sent, the data processing module 13 sends a feedback signal to the room temperature acquisition module 11, and reselects the reference superconducting device to acquire the room temperature resistance value. The data processing module 13 then compares the room temperature resistance value of the superconducting device under test tested by the room temperature acquisition module 11 with the reference value to see if the error is within 3%. If it is within 3%, it is considered a good product; otherwise, it is considered a defective product. In this embodiment, the data processing module also includes a storage unit. The room temperature resistance value of the reference superconducting device obtained by the low temperature detection module 12 can be stored in the storage unit, which facilitates batch detection of other superconducting devices on the wafer and batch detection of wafers in the same batch during the wafer fabrication process.

[0086] In addition, different superconducting devices, when combined in series or parallel using Josephson junctions or other methods, will produce different room-temperature resistance values. Different device combinations will yield different resistance measurements; therefore, by randomly selecting superconducting devices on a wafer, the different room-temperature resistance values ​​can be used to determine the device type.

[0087] In summary, this invention provides a room-temperature detection method and system for superconducting devices, comprising: selecting a reference superconducting device; measuring the room-temperature resistance value and operating status of the reference superconducting device at low temperatures; if the reference superconducting device operates normally under low-temperature conditions, then using the room-temperature resistance value of the reference superconducting device as a reference value; if the reference superconducting device is not functioning normally, then reselecting a reference superconducting device; and under room-temperature conditions, testing the room-temperature resistance value of the superconducting device under test and comparing it with the reference value to determine whether the superconducting device under test is damaged. This invention utilizes the room-temperature characteristics of superconducting devices for detection, and the detection method is fast and efficient, applicable to the batch detection of superconducting chips on wafers. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0088] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A room-temperature detection method for superconducting devices, characterized in that, The room-temperature detection method for the superconducting device includes: S1. Select a reference chip and verify whether the reference chip is functioning normally under low temperature conditions. If the reference chip is functioning normally, then use the reference chip as a reference. If the reference chip is not functioning normally, then select a new reference chip. S2. Measure the room temperature resistance value of the reference superconducting device on the reference chip; S3. Measure the room temperature resistance value of the superconducting device under test on the chip under test; the reference superconducting device and the superconducting device under test have the same structure and parameters and are respectively set on two chips; S4. The room temperature resistance value of the superconducting device under test is compared with the room temperature resistance value of the reference superconducting device. If the error value is less than or equal to the preset value, the chip under test is determined to be good; if the error value is greater than the preset value, the chip under test is determined to be defective.

2. The room-temperature detection method for superconducting devices according to claim 1, characterized in that: The preset value is less than or equal to 3% of the room temperature resistance value of the reference superconducting device.

3. The room-temperature detection method for superconducting devices according to claim 1, characterized in that: The resistance value at room temperature was measured using the four-terminal probe method.

4. The room-temperature detection method for superconducting devices according to claim 1, characterized in that: Electrostatic protection was applied to the test chip before and after measuring its resistance at room temperature.

5. A room-temperature detection method for superconducting devices, characterized in that, The room-temperature detection method for the superconducting device includes: S1. Select a reference chip and measure the room temperature resistance value of the reference superconducting device on the reference chip; S2. Verify whether the reference chip is in normal condition under low temperature conditions. If the reference chip is in normal condition, use the room temperature resistance value of the reference chip as the reference value. If the reference chip is not in normal condition, return to step S1 and select a new reference chip. S3. Measure the room temperature resistance value of the superconducting device under test on the chip under test; the reference superconducting device and the superconducting device under test have the same structure and parameters and are respectively set on two chips; S4. The room temperature resistance value of the superconducting device under test is compared with the room temperature resistance value of the reference superconducting device. If the error value is less than or equal to the preset value, the chip under test is determined to be good; if the error value is greater than the preset value, the chip under test is determined to be defective. In step S2, if the reference chip is in normal condition under low temperature conditions, the room temperature resistance value of the reference superconducting device is measured again at room temperature and compared with the room temperature resistance value of the reference superconducting device in step S1. If the error value is less than or equal to the preset deviation value, the room temperature resistance value of the reference chip in step S1 is used as the reference value, and step S3 is executed. If the error value is greater than the preset deviation value, step S1 is executed again.

6. The room-temperature detection method for superconducting devices according to claim 5, characterized in that: The preset value is less than or equal to 3% of the room temperature resistance value of the reference superconducting device.

7. The room-temperature detection method for superconducting devices according to claim 5, characterized in that: The preset deviation value is less than or equal to 3% of the room temperature resistance value of the reference superconducting device.

8. The room-temperature detection method for superconducting devices according to claim 5, characterized in that: The resistance value at room temperature was measured using the four-terminal probe method.

9. The room-temperature detection method for superconducting devices according to claim 5, characterized in that: Electrostatic protection was applied to the test chip before and after measuring its resistance at room temperature.

10. A room-temperature detection system for superconducting devices, used to implement the room-temperature detection method for superconducting devices according to any one of claims 1-9, characterized in that, The room temperature detection system for the superconducting device includes at least: a room temperature acquisition module, a low temperature testing module, and a data processing module; The room temperature acquisition module is used to acquire the room temperature resistance value of the reference superconducting device and the room temperature resistance value of the superconducting device under test and transmit them to the data processing module. The low-temperature testing module is used to test the low-temperature operating state of the reference chip; The data processing module is connected to the room temperature acquisition module and the low temperature test module, and compares the room temperature resistance value of the reference superconducting device and the room temperature resistance value of the superconducting device under test based on the low temperature test results.

11. The room-temperature detection system for superconducting devices according to claim 10, characterized in that: The ambient temperature detection system module includes a test circuit and an electrostatic protection circuit. The electrostatic discharge (ESD) protection circuit is connected in parallel across the two ends of the chip; before and after measuring the resistance value at room temperature, the ESD protection circuit is connected in parallel with the chip and then in series with the test circuit; when measuring the resistance value at room temperature, the two ends of the ESD protection circuit are grounded, and the chip is connected in series with the test circuit.

12. The room-temperature detection system for superconducting devices according to claim 11, characterized in that: The electrostatic protection circuit is configured with transient voltage suppression diodes.

13. The room-temperature detection system for superconducting devices according to claim 11, characterized in that: The test circuit is a four-terminal measurement unit; the four-terminal measurement unit includes a constant current source and four probes.

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