Read performance techniques for time reservation

Abstract

This application is directed to techniques for time-retention read performance. A memory system can store data in a block of memory cells and perform a power cycle operation. Based on performing the power cycle operation, the memory system can determine a first voltage offset associated with the block of memory cells by performing a first read command using an auto-read calibration operation. Based on the first voltage offset, and in some instances one or more additional voltage offsets, the memory system can calculate a retention time for the data stored in the block of memory cells. The memory system can adjust a read voltage based on the retention time and perform one or more additional read commands.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 726,255, filed April 21, 2022, entitled “Read Performance Technology for Time Retention”, by Zhou et al., and U.S. Provisional Patent Application No. 63 / 212,462, filed June 18, 2021, entitled “Read Performance Technology for Time Retention”, each of which is assigned to the assignee of this invention, and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to read performance technologies for time retention. Background Technology

[0004] Memory systems (which may include memory devices) are widely used to store information in various electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, and so on. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR and NAND memory devices, and others. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless they are periodically refreshed by an external power supply. Even without an external power supply, non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods of time. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include: a memory device; and a controller coupled to the memory device and configured such that the apparatus: executes a first read command through the memory device to retrieve a page of a memory cell block; determines a first voltage offset associated with the memory cell block based on the execution of the first read command; calculates a retention time for stored information associated with the first read command based on the determined first voltage offset; and executes one or more additional read commands based on the determined first voltage offset and the calculated retention time.

[0007] A non-transitory computer-readable medium storing code is described. The non-transitory computer-readable medium storing code may include instructions that, when executed by a processor of an electronic device, cause the electronic device to: execute a first read command to retrieve a page of a memory cell block; determine a first voltage offset associated with the memory cell block based on the execution of the first read command; calculate a retention time for stored information associated with the first read command based on the determined first voltage offset; and execute one or more additional read commands based on the determined first voltage offset and the calculated retention time.

[0008] Describe a method. The method may include: executing a first read command via a memory system to retrieve pages of a memory cell block; determining a first voltage offset associated with the memory cell block based on the execution of the first read command; calculating a retention time for stored information associated with the first read command based on the determined first voltage offset; and executing one or more additional read commands based on the determined first voltage offset and the calculated retention time. Attached Figure Description

[0009] Figure 1 Examples of systems that support read performance techniques for time retention are illustrated in this article.

[0010] Figure 2 Examples of voltage graphs supporting readability techniques for time retention are illustrated in the examples disclosed herein.

[0011] Figure 3 Examples of processing flows that support read performance techniques for time retention are illustrated in this article.

[0012] Figure 4 A block diagram of a memory system supporting read performance techniques for time retention is illustrated using examples disclosed herein.

[0013] Figure 5The flowcharts illustrating one or more methods supporting read performance techniques for time retention are presented in the examples disclosed herein. Detailed Implementation

[0014] In some memory systems that may contain memory devices, slow charge loss (SCL) can affect read performance over time. For example, due to SCL, the voltage level stored in a block of memory cells can gradually change over time. Therefore, read commands may fail due to changes in data voltage, unnecessarily triggering error handling and increasing read latency. In some situations, a read failure may trigger a series of error handling (EHF) events, where the read voltage is adjusted to attempt to read the data. However, if SCL has significantly altered the voltage level of the block of memory cells, this process may include multiple EHF events to accurately read the data.

[0015] In some situations, a memory system (e.g., a memory device) can determine the voltage offset of a read operation after a power cycle to correct for SCL effects. For example, the memory system (e.g., the memory device) can use an Automatic Read Calibration (ARC) operation to read sample pages of data from a memory cell block and calculate the voltage offset based on or in response to reading the sample pages. Based on or in response to determining the voltage offset, the device can calculate the retention time of the stored data and subsequently calculate the voltage offset for the voltage level corresponding to the stored logic state of the memory cell block. For example, if the memory cell block is a three-level cell (TLC) block, then the memory system (e.g., the memory device) can determine the voltage offset for each of the eight possible logic states of the memory cell block. In a subsequent read command, the memory system (e.g., the memory device) can use the determined voltage offset to adjust the read voltage used when executing the read command, which can be used to more reliably execute subsequent read commands at the device.

[0016] First refer to Figure 1 The features of this disclosure are described in the context of the system. (See references.) Figure 2 and 3 The features of this disclosure are described in the context of voltage diagrams and processing flows. References Figure 4 and 5 These and other features of this disclosure are further illustrated and described in the context of device diagrams and flowcharts for read performance techniques for time retention.

[0017] Figure 1 An example of a system 100 supporting read performance techniques for time retention is illustrated below. System 100 includes a host system 105 coupled to a memory system 110.

[0018] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0019] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other vehicle), Internet of Things (IoT) enabled device, embedded computer (e.g., computer included in a vehicle, industrial equipment or networked commercial device), or any other computing device that includes memory and processing devices.

[0020] System 100 may include a host system 105, which may be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations according to the instances described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more cache memories (e.g., memory local to the host system 105 or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a memory protocol controller (e.g., a Fast Peripheral Component Interconnect (PCIe) controller, a Serial Advanced Technology Bus Attached (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although in Figure 1 The diagram shows a memory system 110, and a host system 105 can be coupled to any number of memory systems 110.

[0021] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., exchanging or otherwise transmitting control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM socket interfaces), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be contained between host system controller 106 of host system 105 and memory system controller 115 of memory system 110, or otherwise supported therebetween. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0022] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although in Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, then the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0023] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130, and other such operations, which are generally referred to as access operations. In some situations, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some situations, the memory system controller 115 may exchange data with the host system 105 and with one or more memory devices 130 (e.g., in response to or otherwise associated with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105.

[0024] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, useless information collection operations, error control operations such as error detection or error correction operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0025] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-coded) logic to perform the operations described herein that pertain to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry system.

[0026] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions belonging to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions belonging to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may be used as a cache memory for the memory system controller 115. For example, data may be stored in local memory 120 when read from or written to memory device 130, and said data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 (e.g., with reduced latency relative to memory device 130) according to a caching strategy.

[0027] although Figure 1 The memory system 110 described herein has been illustrated as including a memory system controller 115, but in some cases, the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135, which may be located within the memory device 130, to perform the functions described herein as belonging to the memory system controller 115. Typically, in some cases, one or more functions described herein as belonging to the memory system controller 115 may alternatively be performed by the host system 105, the local controller 135, or any combination thereof. In some cases, the memory device 130, which is at least partially managed by the memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0028] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0029] In some instances, memory device 130 may include (e.g., on the same die or within the same package) a local controller 135 that can operate on one or more memory cells of the corresponding memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions belonging to memory system controller 115 herein. For example, as in Figure 1 As described herein, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0030] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package including one or more dies 160. In some instances, die 160 may be a single electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0031] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as a multi-level cell (MLC) when configured to store two bits of information, as a three-level cell (TLC) when configured to store three bits of information, as a four-level cell (QLC) when configured to store four bits of information, or more generally as a multi-level memory cell. Multi-level memory cells can provide greater storage density than SLC memory cells, but in some cases may involve narrower read or write tolerances or higher complexity of supporting circuitry.

[0032] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, concurrent operations may be performed within different planes 165. For example, concurrent operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, a single block 170 may be referred to as a physical block, and virtual block 180 may refer to a group of blocks 170 in which concurrent operations can occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual block 180. In some cases, a virtual block may contain blocks 170 from different memory devices 130 (e.g., blocks contained in one or more planes of memory devices 130-a and 130-b). In some situations, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, etc.). In some situations, concurrent operations performed in different planes 165 may be subject to one or more restrictions, such as concurrent operations performed on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., with command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0033] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share (e.g., coupled thereto) a common word line, and memory cells in the same string may share (e.g., coupled thereto) a common digital line (which may alternatively be called a bit line).

[0034] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a group of memory cells) that can be programmed or read individually (e.g., simultaneously programmed or read as part of a single programmable or readmable operation), and block 170 can be the smallest unit of memory (e.g., a group of memory cells) that can be erased individually (e.g., simultaneously erased as part of a single erasemable operation). Furthermore, in some situations, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some situations, page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0035] System 100 may include any number of non-transitory computer-readable media that support read performance techniques for time retention. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) for performing the functions belonging to host system 105, memory system controller 115, or memory device 130 herein. For example, such instructions, when executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0036] Under certain conditions, NAND memory device 130 (which may contain blocks 170 configured to store one or more bits of information (e.g., SLC, MLC, TLC, or QLC blocks 170)) may undergo SCL (Solution-Cooled Reading). That is, the voltage corresponding to the logic state stored in the memory cells of block 170 may decrease over time. Therefore, a read command executed by memory device 130 may fail due to the change in data voltage, which can trigger error handling operations and increase read latency. Under certain conditions, a read failure may trigger a series of EHF (Extended High Frequency) events, where the read voltage can be adjusted to attempt to read the data. However, if SCL has significantly changed the voltage level of the memory cell block, then this process may include multiple EHF events to accurately read the data.

[0037] In some situations, memory device 130 can determine the voltage offset of a read operation after a power cycle to correct for SCL effects. For example, memory device 130 can use an ARC operation to read a sample page 175 of data from block 170 (e.g., block 170-a) and calculate the voltage offset based on or in response to reading the sample page 175. Based on or in response to determining the voltage offset, memory device 130 can calculate the retention time of the stored data and subsequently calculate the voltage offset for the voltage level corresponding to the storage logic state of block 170. For example, if block 170-a is a TLC block 170, then memory device 130 can determine the voltage offset for each of the eight possible logic states of the memory cells in block 170-a. Alternatively, memory device 130 can use the sample page 175 read from block 170-a to calculate the voltage offset for other blocks 170 (e.g., block 170-b). In a subsequent read command, the memory device 130 may use a determined voltage offset to adjust the read voltage used when executing the read command, the read voltage being used to execute subsequent read commands more reliably at the memory device 130.

[0038] Figure 2 An example of voltage graph 200 supporting read performance techniques for time retention is illustrated below. Voltage graph 200 can illustrate the average change of voltage of a memory cell block over time (e.g., as shown in the reference). Figure 1 (As described). The memory cell block may be an instance of a multi-level cell block and may be configured to store multiple data bits per cell (e.g., three data bits). For example, the memory cell block may be an instance of a TLC block and may be configured to store one of eight voltage levels 210, each level corresponding to a possible set of three bits (i.e., 000, 001, 010, 100, 011, 101, 110, and 111).

[0039] The voltage stored in the block can decrease over time, which can cause a change in the voltage difference (e.g., voltage offset) between the levels 210 of the memory cells. That is, the block can experience SCL (Sequential Voltage Shift), which can cause a change in the voltage offset. The effect of SCL on the voltage level of the block can be logarithmically linear over time. In other words, if the voltage level is plotted relative to a logarithmic time scale, then the voltage level can decrease linearly, as in... Figure 2 As explained in the document. In some situations, the length of time a block undergoes the SCL can be categorized into one of a set of time periods 205, such as time period 205-a, time period 205-b, time period 205-c, time period 205-d, time period 205-e, time period 205-f, or time period 205-g. For example, a block in time period 205-b may undergo the SCL for a longer time than a block in time period 205-a.

[0040] In some situations, the effect of SCL (Search Channel Lag) can be accelerated by subjecting the block to high-temperature baking. For example, repeatedly baking at 125 degrees Celsius for four hours can simulate the SCL of a block that has not been baked at high temperatures for a relatively long period. In this simulation, the read performance of the memory device can decrease by up to, for example, 50% due to SCL every four hours of baking. The decrease in read performance can lead to a series of failed reads because time period 205 is not updated in time. In some situations, read failures can trigger EHF (Extended High Frequency), where the memory device may attempt to adjust the read voltage to accurately read the data stored in the block. Triggering multiple EHFs can result in long read latency.

[0041] The change in block level 210 after a power cycle (e.g., after the block experiences the SCL effect) can be determined by performing a read operation on the sample data page after a power cycle event (e.g., performing ARC on the sample page). In some instances, sample pages can be read from open TLC blocks or young TLC blocks (e.g., closed TLC blocks in time period 205-a or time period 205-b).

[0042] In some situations, a change in level 210 can be calculated by determining the voltage offset of one of the levels 210. For example, the voltage offset of level 210-g can be determined by performing an ARC operation on a sample page of data. Based on or in response to the voltage offset of level 210-g, the voltage offsets of the remaining levels (e.g., level 210-a, level 210-b, level 210-c, level 210-d, level 210-e, level 210-f) can be calculated.

[0043] Determining the voltage offset of level 210 may include calculating the retention time. The retention time indicates the length of time the block is in a retention state (e.g., a power-off state) before a power cycle. In some cases, all blocks of the memory device may experience the same retention time and therefore the same SCL. In some instances, the retention time can be used to determine which of the group of time periods 205 a block may be in.

[0044] In some cases, the remaining voltage offset (e.g., voltage offsets of levels 210-a to 210-f) can be determined based on or in response to a determined retention time. For example, each of the group of time periods 205 may correspond to a given set of voltage offsets for each level 210, and thus the block can use the retention time to determine the time period of the block. In such instances, the voltage offset of each of the levels 210 can be determined by mapping the time periods 205 of the block to the corresponding voltage offsets. In some cases, the mapping may be stored in a memory device. Mapping the time periods 205 of the block to voltage offsets can mitigate (e.g., reduce) the use of storage resources and computational resources, since a limited number of time periods 205 (e.g., eight time periods 205) can be stored. Alternatively or additionally, the remaining voltage offset can be calculated based on or in response to a determined retention time. In some cases, a fixed ratio may exist between the voltage offsets of levels 210 in each time period 205. By determining the voltage offset of one of the levels 210 (e.g., level 210-g) and determining the time period 205 of the block, a fixed ratio can be used to calculate the remaining voltage offset of the levels 210 (e.g., from level 210-a to level 210-f).

[0045] Figure 3 An example of a processing flow 300 supporting read performance techniques for time retention is illustrated below, as disclosed in this document. Processing flow 300 may be derived from, for example, references... Figure 1 The memory system 110 described herein is executed by components of the memory system. For example, processing flow 300 may be executed by a controller of the memory system or memory device (e.g., memory system controller 115 or local controller 135), as described in reference Figure 1 As described. Among other benefits, process flow 300 can be implemented to reduce latency and power consumption and increase system performance. Aspects of process flow 300 can be implemented by a controller and other components. Alternatively, aspects of process flow 300 can be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to memory system controller 115 or local controller 135). For example, if the instructions are executed by a controller (e.g., memory system controller 115, local controller 135), then the controller can cause the controller to perform the operations of process flow 300. In the following description of process flow 300, the operations can be performed in a different order than shown. For example, specific operations can be excluded from process flow 300, or other operations can be added to process flow 300.

[0046] At position 305, data can be stored in a memory cell block (e.g., via the controller). In some cases, the data may contain sample pages (e.g., reference pages). Figure 1(See page 175 described). The sample page may contain memory cells programmed into a predetermined state. Subsequently, at 310, the controller may perform a power cycling operation. For example, the controller may perform the power cycling operation after storing data in a block of memory cells.

[0047] At 315, a first read command can be executed (e.g., via the controller). For example, the controller can execute the first read command to retrieve a page of a memory cell block. In some cases, the controller can execute the first read command based on or in response to a power cycling operation performed at 310. The page may be an instance of a sample page (e.g., as referenced). Figure 1 and 2 As described above, executing a read command may involve using ARC or another method to determine the voltage offset to read a sample page (e.g., a read command may be an ARC read).

[0048] At 320, a first voltage offset can be determined (e.g., by the controller). For example, the controller can determine a first voltage offset associated with a memory cell block (e.g., by referencing...). Figure 2 (Voltage offset of one of the described levels 210). In some situations, the controller may determine the first voltage offset based on or in response to performing ARC operations on sample pages of a memory cell block.

[0049] At 325, it can be determined whether a first voltage offset is greater than or equal to a voltage threshold (e.g., by a controller). For example, the controller can determine whether a voltage change associated with the first voltage offset is greater than or equal to the voltage threshold. In some instances, the voltage threshold may be approximately 90 millivolts. In some situations, a first voltage offset that meets the threshold may indicate that ARC operation has not found a valley. That is, ARC operation may be unable to detect a voltage offset greater than the voltage threshold. If the first voltage offset is greater than the voltage threshold, then ARC operation may not find the accurate first voltage offset. In other situations (e.g., when using methods other than ARC to determine the first voltage offset), the voltage threshold may be different, or a single read method may be used to determine the first voltage offset.

[0050] If a first voltage offset is determined to be greater than or equal to a voltage threshold at 325, then steps 330, 335, and 340 can be executed (e.g., via the controller). At 330, persistence parameters associated with executing the read command can be adjusted (e.g., via the controller), for example, based on or in response to determining that the first voltage offset is greater than or equal to the voltage threshold. For example, as part of adjusting persistence parameters, the controller can enter a continuous on-mode in which the read voltage of ARC operation is adjusted (e.g., to more accurately measure the first voltage offset determined at 320).

[0051] At 335, a second read command (e.g., a second ARC operation) can be executed (e.g., via the controller). For example, the controller can execute the second ARC operation based on or in response to adjusting persistence parameters at 330 to retrieve a page associated with a memory cell block (e.g., a sample page read at 315). That is, the second ARC operation can read the sample page while the device is continuously on. Subsequently, at 340, an updated first voltage offset can be determined. For example, the controller can update the first voltage offset based on or in response to reading the sample page, based on or in response to the result of the second ARC operation executed while the device is continuously on. After updating the first voltage offset, the controller can again determine at 325 whether the first voltage offset is greater than or equal to a voltage threshold. If the controller determines at 325 that the first voltage offset is less than the voltage threshold, then the controller can execute one or more of 345, 350, and 355.

[0052] At 345, the retention time can be calculated (e.g., by the controller). The retention time can be associated with the duration after data is stored in the memory cell block at 305 and before the power cycling operation 310 is performed. For example, the retention time can indicate how long the data has been stored before the power cycling operation is performed. In some cases, the retention time can be calculated based on or in response to determining a first voltage offset at 320. Alternatively or alternatively (e.g., if the first voltage offset is greater than or equal to a voltage threshold), then the retention time can be calculated based on or in response to determining an updated first voltage offset at 340. For example, the controller can use a configuration relationship between the first voltage offset and the retention time to calculate the retention time.

[0053] At 350, one or more additional voltage offsets can be calculated (e.g., via the controller). In some cases, the controller can calculate a second voltage offset associated with the second memory cell block based on or in response to a retention time calculated at 345. For example, the controller can use the relationship between retention time and voltage offset (e.g., referring to...) Figure 2 The voltage diagram described in Figure 200 is used to calculate the second voltage offset.

[0054] In some situations, the controller may calculate one or more additional voltage offsets based on or in response to calculating the retention time at 345 and a ratio associated with the first voltage. For example, a proportional relationship may exist between the first voltage offset and one or more additional voltage offsets. Therefore, determining the first voltage offset allows one or more additional voltage offsets to be calculated based on said ratio. Alternatively, the controller may calculate one or more additional voltage offsets based on or in response to calculating the retention time at 345 and a formula associated with the first voltage offset.

[0055] At 355, one or more additional read commands can be executed. For example, the controller can execute a third read command. The third read command may contain instructions to retrieve data from a second memory cell block based on or in response to calculating (e.g., using) a second voltage offset. In some instances, the memory device may execute one or more additional read commands based on or in response to determining a first voltage offset at 320 and calculating a retention time at 345. In some instances, one or more additional read commands may also be executed based on or in response to calculating (e.g., using) one or more voltage offsets calculated at 350. In some situations, the controller may, for example, use a reference... Figure 2 The described voltage diagram 200 determines the time period of a memory cell block based on a first voltage offset and one or more additional voltage offsets. That is, the memory device can operate according to one or more voltage offsets and the determined time period. For example, the memory device can use one or more voltage offsets and the determined time period to read from a memory cell block or other memory cell blocks.

[0056] Figure 4 A block diagram 400 of a memory system 420 supporting read performance techniques for time retention is shown based on examples disclosed herein. The memory system 420 may be as described in the references... Figures 1 to 3 Examples of various aspects of the described memory system. Memory system 420 or its various components may be examples of means for performing various aspects of the read performance techniques for time retention as described herein. For example, memory system 420 may include a read command manager 425, a voltage offset component 430, a retention time manager 435, a data storage component 440, a power cycle manager 445, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0057] The read command manager 425 may be configured or otherwise supported to provide means for executing a first read command through the memory system to retrieve pages of a memory cell block. The voltage offset component 430 may be configured or otherwise supported to provide means for determining a first voltage offset associated with the memory cell block, at least in part based on the execution of the first read command. The retention time manager 435 may be configured or otherwise supported to provide means for calculating a retention time for stored information associated with the first read command, at least in part based on the determination of the first voltage offset. In some instances, the read command manager 425 may be configured or otherwise supported to provide means for executing one or more additional read commands, at least in part based on the determination of the first voltage offset and the calculation of the retention time.

[0058] In some instances, the data storage component 440 may be configured or otherwise support means for storing data in a memory cell block. In some instances, the power cycling manager 445 may be configured or otherwise support means for performing a power cycling operation via the memory system after storing data in a memory cell block, wherein the first read command is executed at least in part based on performing the power cycling operation.

[0059] In some instances, retention time is associated with the duration after data is stored in a memory cell block and before power cycling is performed through the memory system.

[0060] In some instances, the voltage offset component 430 may be configured or otherwise supported to allow for means of calculating a second voltage offset, at least in part, based on a calculated retention time, the second voltage offset being associated with a second memory cell block. In some instances, the read command manager 425 may be configured or otherwise supported to allow for means of executing a second read command to retrieve data from the second memory cell block, at least in part based on the calculated second voltage offset.

[0061] In some instances, the voltage offset component 430 may be configured or otherwise supported for means of calculating one or more additional voltage offsets associated with a memory cell block based at least in part on the calculation of the retention time and the ratio associated with the first voltage offset, wherein one or more additional read commands are executed based at least in part on the calculation of one or more additional voltage offsets.

[0062] In some instances, the voltage offset component 430 may be configured or otherwise supported for means of calculating one or more additional voltage offsets associated with a memory cell block based at least in part on a calculation retention time and a formula associated with a first voltage offset, wherein one or more additional read commands are executed based at least in part on the calculation of one or more additional voltage offsets.

[0063] In some instances, the voltage offset component 430 may be configured or otherwise supported to support means for determining whether a first voltage offset associated with a memory cell block is greater than or equal to a voltage threshold. In some instances, the read command manager 425 may be configured or otherwise supported to support means for adjusting persistence parameters associated with the execution of a read command, at least in part based on determining that the first voltage offset is greater than or equal to a voltage threshold. In some instances, the read command manager 425 may be configured or otherwise supported to support means for executing a second read command to retrieve pages of a memory cell block, at least in part based on adjusting persistence parameters. In some instances, the voltage offset component 430 may be configured or otherwise supported to support means for determining an updated first voltage offset associated with a memory cell block, at least in part based on executing a second read command, wherein a retention time is calculated and one or more additional read commands are executed based at least in part on determining the updated first voltage offset.

[0064] In some instances, the updated first voltage offset is less than the voltage threshold. In some instances, the voltage threshold is approximately 90 millivolts.

[0065] Figure 5 A flowchart illustrating a method 500 supporting read performance techniques for time retention is presented according to examples disclosed herein. The operation of method 500 may be implemented by a memory system or its components as described herein. For example, the operation of method 500 may be performed by a memory system, as referenced... Figures 1 to 4 As described. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0066] At 505, the method may include executing a first read command via the memory system to retrieve a page of a memory cell block. The operation of 505 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 505 may be performed via a read command manager 425, as referenced... Figure 4 As described.

[0067] At 510, the method may include determining a first voltage offset associated with a memory cell block, at least in part based on executing a first read command. The operation of 510 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 510 may be as described in reference... Figure 4 The voltage offset component 430 described herein is used to perform this action.

[0068] At 515, the method may include calculating the retention time of the stored information associated with the first read command based at least in part on determining a first voltage offset. The operation of 515 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 515 may be performed by a retention time manager 435, as referenced... Figure 4 As described.

[0069] At 520, the method may include performing one or more additional read commands, at least in part, based on determining a first voltage offset and calculating a retention time. The operation of 520 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 520 may be performed via a read command manager 425, as referenced... Figure 4 As described.

[0070] In some instances, the device as described herein may perform one or more methods, such as method 500. The device may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following: executing a first read command via a memory system to retrieve a page of a memory cell block; determining a first voltage offset associated with the memory cell block based at least in part on the execution of the first read command; calculating a retention time for stored information associated with the first read command based at least in part on the determination of the first voltage offset; and executing one or more additional read commands based at least in part on the determination of the first voltage offset and the calculated retention time.

[0071] Some examples of the method 500 and apparatus described herein may further include operations, features, circuit systems, logic, means, or instructions for performing the following: storing data in a memory cell block, and after storing the data in the memory cell block, performing a power cycle operation through the memory system, wherein a first read command may be executed at least in part based on performing the power cycle operation.

[0072] In some instances of the method 500 and apparatus described herein, the retention time may be associated with the duration after data can be stored in a memory cell block and before power cycling operations can be performed by the memory system.

[0073] Some examples of the method 500 and apparatus described herein may further include operations, features, circuit systems, logic, means, or instructions for performing the following: calculating a second voltage offset at least in part based on a calculated retention time, the second voltage offset being associated with a second memory cell block; and executing a second read command at least in part based on the calculated second voltage offset to retrieve data from the second memory cell block.

[0074] Some examples of the method 500 and apparatus described herein may further include operations, features, circuit systems, logic, means, or instructions for performing the following: calculating one or more additional voltage offsets associated with a memory cell block based at least in part on a calculation of a retention time and a ratio associated with a first voltage offset, wherein one or more additional read commands are executed based at least in part on the calculation of one or more additional voltage offsets.

[0075] Some examples of the method 500 and apparatus described herein may further include operations, features, circuit systems, logic, means, or instructions for performing the following: calculating one or more additional voltage offsets associated with a memory cell block based at least in part on a formula relating to a retention time and a first voltage offset, wherein one or more additional read commands are executed based at least in part on the calculation of one or more additional voltage offsets.

[0076] Some examples of the method 500 and apparatus described herein may further include operations, features, circuit systems, logic, means, or instructions for performing the following: determining whether a first voltage offset associated with a memory cell block is greater than or equal to a voltage threshold; adjusting a persistence parameter associated with the execution of a read command based at least in part on determining that the first voltage offset is greater than or equal to the voltage threshold; executing a second read command to retrieve a page of the memory cell block based at least in part on adjusting the persistence parameter; and determining an updated first voltage offset associated with the memory cell block based at least in part on executing the second read command, wherein a retention time can be calculated and one or more additional read commands can be executed based at least in part on determining the updated first voltage offset.

[0077] In some instances of the method 500 and device described herein, the updated first voltage offset may be less than a voltage threshold.

[0078] In some instances of the method 500 and device described herein, the voltage threshold may be approximately 90 millivolts.

[0079] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, parts from two or more methods can be combined.

[0080] Describe an apparatus. The apparatus may include a memory device and a controller, the controller being coupled to the memory device and configured such that the apparatus performs the following operations: executing a first read command through the memory device to retrieve a page of a memory cell block; determining a first voltage offset associated with the memory cell block based at least in part on the execution of the first read command; calculating a retention time for stored information associated with the first read command based at least in part on the determination of the first voltage offset; and executing one or more additional read commands based at least in part on the determination of the first voltage offset and the calculated retention time.

[0081] In some instances, the device may include storing data in a memory cell block and, after storing the data in the memory cell block, performing a power cycling operation through the memory device, wherein the first read command is executed at least in part based on the execution of the power cycling operation.

[0082] In some instances of the device, retention time can be associated with the duration after data can be stored in a memory cell block and before power cycling operations can be performed by the memory device.

[0083] In some instances, the device may include calculating a second voltage offset, associated with a second memory cell block, based at least in part on the calculation of the retention time; and executing a second read command to retrieve data from the second memory cell block, based at least in part on the calculation of the second voltage offset.

[0084] In some instances of the device, the controller may be further configured to cause the device to: calculate one or more additional voltage offsets associated with a memory cell block based at least in part on the calculation of the retention time and the ratio associated with the first voltage offset, wherein one or more additional read commands may be executed based at least in part on the calculation of one or more additional voltage offsets.

[0085] In some instances of the device, the controller may be further configured to cause the device to perform the following operations: calculate one or more additional voltage offsets associated with a memory cell block based at least in part on a formula for calculating retention time and associated with a first voltage offset, wherein one or more additional read commands may be executed based at least in part on the calculation of one or more additional voltage offsets.

[0086] In some instances, the device may include the following operations: determining whether a first voltage offset associated with a memory cell block is greater than or equal to a voltage threshold; adjusting persistence parameters associated with the execution of a read command based at least in part on determining that the first voltage offset is greater than or equal to the voltage threshold; executing a second read command to retrieve a page of the memory cell block based at least in part on adjusting the persistence parameters; and determining an updated first voltage offset associated with the memory cell block based at least in part on executing the second read command, wherein a retention time can be calculated and one or more additional read commands can be executed based at least in part on determining the updated first voltage offset.

[0087] In some instances of the device, the first voltage offset for the update may be less than the voltage threshold.

[0088] In some instances of the device, the voltage threshold can be approximately 90 millivolts.

[0089] The information and signals described herein can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced herein can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a bus of signals, where the bus may have various bit widths.

[0090] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that support signal flow between them. Components are considered to be in electronic communication (or electrically connected, connected, or coupled to each other) if there is any conductive path between them that can readily support signal flow. At any given time, the conductive path between components that are in electronic communication (or electrically connected, connected, or coupled to each other) may be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components may be a direct conductive path or an indirect conductive path, which may include intermediate components such as switches, transistors, or other components. In some instances, for example, by using one or more intermediate components such as switches or transistors, the signal flow between connected components can be interrupted for a period of time.

[0091] The term "coupling" refers to a shift from an open-circuit relationship between components (where signals cannot currently communicate between components via conductive paths) to a closed-circuit relationship between components (where signals can communicate between components via conductive paths). When a component (e.g., a controller) couples other components together, that component initiates a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0092] The term "isolation" refers to a relationship between components where signals are currently unable to flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, if a switch is turned off, then two components located between them, separated by the switch, are isolated from each other. If a controller isolates two components, the controller can influence changes that prevent signals from flowing between the components using previously permitted conductive paths.

[0093] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe conditional actions, conditional procedures, or relationships between parts of a procedure.

[0094] The term "in response to" may refer to a condition or action that occurs at least partially (if not entirely) as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of a prior condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions that occur after the first condition or action).

[0095] Additionally, the terms "directly in response to" or "directly responding to" may refer to a condition or action that occurs directly as a result of a preceding condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previously occurring condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previously occurring condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" some other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly responding to" such other conditions or actions.

[0096] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping means.

[0097] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated."

[0098] The descriptions set forth herein, in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description," and not "preferred" or "superior to other instances." Detailed descriptions include specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0099] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral for differentiation among similar components. If only the first reference numeral is used in the specification, then the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0100] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions can be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be located in various locations, including portions distributed such that the functions are implemented at different physical locations.

[0101] For example, the various illustrative blocks and components described herein in conjunction with this disclosure may be implemented or performed using any of the following devices designed to perform the functions described herein: a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0102] As used herein (including in the claims), "or" as used in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be considered a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be considered in the same manner as the phrase "at least partially based on".

[0103] Computer-readable media includes both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact optical disc (CD) ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor.

[0104] Furthermore, any connection may be appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared, radio, and microwave), then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technology (such as infrared, radio, and microwave) is included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0105] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art without departing from its scope, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: Memory devices; and A controller, coupled to and configured to cause the device to: The memory device executes a first read command to retrieve a sample page of a memory cell block; The first voltage offset associated with the memory cell block is determined at least in part based on the execution of the first read command and at least in part based on the sample page; The retention time of the stored information associated with the first read command is calculated at least in part based on determining the first voltage offset, wherein the retention time indicates the duration associated with the power-off state of the memory cell block; and One or more additional read commands may be executed, at least in part, based on determining the first voltage offset and calculating the retention time.

2. The device of claim 1, wherein the controller is further configured such that the device: The data is stored in the memory cell block; and After the data is stored in the memory cell block, a power cycling operation is performed through the memory device, wherein the first read command is executed based at least in part on the execution of the power cycling operation.

3. The device of claim 2, wherein the duration associated with the power-off state of the memory cell block includes a duration after the data is stored in the memory cell block and before the power cycling operation is performed by the memory device.

4. The device of claim 1, wherein the controller is further configured such that the device: A second voltage offset, associated with a second memory cell block, is calculated at least in part based on the retention time; and The second read command is executed at least in part based on the calculation of the second voltage offset to retrieve data from the second memory cell block.

5. The device of claim 1, wherein the controller is further configured such that the device: One or more additional voltage offsets associated with the memory cell block are calculated at least in part based on the retention time and the ratio associated with the first voltage offset, wherein the one or more additional read commands are executed at least in part based on the calculation of the one or more additional voltage offsets.

6. The device of claim 1, wherein the controller is further configured such that the device: One or more additional voltage offsets associated with the memory cell block are calculated, at least in part, based on the calculation of the retention time and a formula associated with the first voltage offset, wherein the one or more additional read commands are executed, at least in part, based on the calculation of the one or more additional voltage offsets.

7. The device of claim 1, wherein the controller is further configured such that the device: Determine whether the first voltage offset associated with the memory cell block is greater than or equal to a voltage threshold; The persistence parameters associated with the execution of the read command are adjusted, at least in part, based on determining that the first voltage offset is greater than or equal to the voltage threshold. The second read command is executed at least in part based on adjusting the persistence parameters to retrieve the sample pages of the memory cell block; and The updated first voltage offset associated with the memory cell block is determined at least in part based on the execution of the second read command, wherein the retention time is calculated and the one or more additional read commands are executed at least in part based on the determination of the updated first voltage offset.

8. The device of claim 7, wherein the updated first voltage offset is less than the voltage threshold.

9. The device of claim 7, wherein the voltage threshold is approximately 90 millivolts.

10. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: The electronic device executes a first read command to retrieve a sample page of a memory cell block; The first voltage offset associated with the memory cell block is determined at least in part based on the execution of the first read command and at least in part based on the sample page; The retention time of the stored information associated with the first read command is calculated at least in part based on determining the first voltage offset, wherein the retention time indicates the duration associated with the power-off state of the memory cell block; and One or more additional read commands may be executed, at least in part, based on determining the first voltage offset and calculating the retention time.

11. The non-transitory computer-readable medium of claim 10, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The data is stored in the memory cell block; and The electronic device performs a power cycling operation after storing the data in the memory cell block, wherein the first read command is executed at least in part based on the execution of the power cycling operation.

12. The non-transitory computer-readable medium of claim 11, wherein the duration associated with the power-off state of the memory cell block includes a duration after the data is stored in the memory cell block and before the power cycling operation is performed by the electronic device.

13. The non-transitory computer-readable medium of claim 10, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: A second voltage offset, associated with a second memory cell block, is calculated at least in part based on the retention time; and The second read command is executed at least in part based on the calculation of the second voltage offset to retrieve data from the second memory cell block.

14. The non-transitory computer-readable medium of claim 10, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: One or more additional voltage offsets associated with the memory cell block are calculated at least in part based on the retention time and the ratio associated with the first voltage offset, wherein the one or more additional read commands are executed at least in part based on the calculation of the one or more additional voltage offsets.

15. The non-transitory computer-readable medium of claim 10, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: One or more additional voltage offsets associated with the memory cell block are calculated, at least in part, based on the calculation of the retention time and a formula associated with the first voltage offset, wherein the one or more additional read commands are executed, at least in part, based on the calculation of the one or more additional voltage offsets.

16. The non-transitory computer-readable medium of claim 10, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Determine whether the first voltage offset associated with the memory cell block is greater than or equal to a voltage threshold; The persistence parameters associated with the execution of the read command are adjusted, at least in part, based on determining that the first voltage offset is greater than or equal to the voltage threshold. The second read command is executed at least in part based on adjusting the persistence parameters to retrieve the sample pages of the memory cell block; and The updated first voltage offset associated with the memory cell block is determined at least in part based on the execution of the second read command, wherein the retention time is calculated and the one or more additional read commands are executed at least in part based on the determination of the updated first voltage offset.

17. The non-transitory computer-readable medium of claim 16, wherein the updated first voltage offset is less than the voltage threshold.

18. A method comprising: The first read command is executed through the memory system to retrieve sample pages of the memory cell block; The first voltage offset associated with the memory cell block is determined at least in part based on the execution of the first read command and at least in part based on the sample page; The retention time of the stored information associated with the first read command is calculated at least in part based on determining the first voltage offset, wherein the retention time indicates the duration associated with the power-off state of the memory cell block; and One or more additional read commands may be executed, at least in part, based on determining the first voltage offset and calculating the retention time.

19. The method of claim 18, further comprising: The data is stored in the memory cell block; and After the data is stored in the memory cell block, a power cycle operation is performed through the memory system, wherein the first read command is executed based at least in part on the execution of the power cycle operation.

20. The method of claim 19, wherein the duration associated with the power-off state of the memory cell block includes a duration after the data is stored in the memory cell block and before the power cycling operation is performed by the memory system.

21. The method of claim 18, further comprising: The second voltage offset is calculated at least in part based on the retention time, and the second voltage offset is associated with the second memory cell block; and The second read command is executed at least in part based on the calculation of the second voltage offset to retrieve data from the second memory cell block.

22. The method of claim 18, further comprising: One or more additional voltage offsets associated with the memory cell block are calculated at least in part based on the retention time and the ratio associated with the first voltage offset, wherein the one or more additional read commands are executed at least in part based on the calculation of the one or more additional voltage offsets.

23. The method of claim 18, further comprising: One or more additional voltage offsets associated with the memory cell block are calculated, at least in part, based on the calculation of the retention time and a formula associated with the first voltage offset, wherein the one or more additional read commands are executed, at least in part, based on the calculation of the one or more additional voltage offsets.

24. The method of claim 18, further comprising: Determine whether the first voltage offset associated with the memory cell block is greater than or equal to a voltage threshold; The persistence parameters associated with the execution of the read command are adjusted, at least in part, based on determining that the first voltage offset is greater than or equal to the voltage threshold. The second read command is executed at least in part based on adjusting the persistence parameters to retrieve the sample pages of the memory cell block; and The updated first voltage offset associated with the memory cell block is determined at least in part based on the execution of the second read command, wherein the retention time is calculated and the one or more additional read commands are executed at least in part based on the determination of the updated first voltage offset.

25. The method of claim 24, wherein the updated first voltage offset is less than the voltage threshold.

Images