Method of manufacturing a nitride semiconductor device

Abstract

A method of manufacturing a nitride semiconductor device includes introducing a p-type impurity into at least a portion of an upper portion of a first nitride semiconductor layer (14) to form a p-type impurity introduction region (16); forming a second nitride semiconductor layer (18) from an upper surface of the first nitride semiconductor layer (14) to include the p-type impurity introduction region (16); and performing an annealing process in a state in which the second nitride semiconductor layer (18) is formed on the first nitride semiconductor layer (14).

Description

Technical Field

[0001] The technology disclosed herein relates to a method of manufacturing a nitride semiconductor device including a nitride semiconductor layer. Background Art

[0002] To manufacture a nitride semiconductor device, a technique is required to introduce p-type impurities into a nitride semiconductor layer and activate the introduced p-type impurities to form a p-type diffusion region. Patent Document 1 discloses an example of a technique for forming a p-type diffusion region in a nitride semiconductor layer.

[0003] Prior art literature

[0004] [Patent Literature]

[0005] Patent Document 1: JP-2019-79930-A Summary of the Invention

[0006] This specification provides a new technique for activating p-type impurities introduced into a nitride semiconductor layer.

[0007] The method for manufacturing a nitride semiconductor device disclosed in this specification includes: a p-type impurity introduction step for introducing p-type impurities into at least a portion of an upper portion of a first nitride semiconductor layer to form a p-type impurity introduction region; a film forming step for forming a second nitride semiconductor layer on an upper surface of the first nitride semiconductor layer to include the p-type impurity introduction region, wherein the second nitride semiconductor layer is formed by coherent growth in the film forming step; and an annealing step for performing annealing treatment under conditions under which the second nitride semiconductor layer is formed on the first nitride semiconductor layer.

[0008] The energy required to activate the p-type impurity depends on the position of the Fermi level in the region where the p-type impurity is introduced. The closer the Fermi level is to the valence band, that is, when the region where the p-type impurity is introduced is n-type, the lower the energy. According to the above-described manufacturing method, the second nitride semiconductor layer is formed by coherent growth on the first nitride semiconductor layer. This generates a two-dimensional electron gas (2DEG) layer due to piezoelectric polarization in the upper portion of the first nitride semiconductor layer, and the upper portion of the first nitride semiconductor layer becomes an n-type region. Therefore, at least a portion of the p-type impurity introduction region formed in the upper layer of the first nitride semiconductor layer can be located in the n-type region. According to the above-described manufacturing method, since the annealing process is performed while the upper portion of the first nitride semiconductor layer is in the n-type region, the p-type impurities in the p-type impurity introduction region are activated with low energy. As a result, the above-described manufacturing method can form a highly active p-type region. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. In the drawings:

[0010] Figure 1 is a flowchart of a part of a method for manufacturing a nitride semiconductor device;

[0011] Figure 2 is a schematic cross-sectional view of a main part of a nitride semiconductor layer in a manufacturing process of a method for manufacturing a nitride semiconductor device;

[0012] Figure 3 is a schematic cross-sectional view of a main part of a nitride semiconductor layer in a manufacturing process of a method for manufacturing a nitride semiconductor device;

[0013] Figure 4 is a schematic cross-sectional view of a main part of a nitride semiconductor layer in a manufacturing process of a method for manufacturing a nitride semiconductor device;

[0014] Figure 5 is a schematic cross-sectional view of a main part of a nitride semiconductor layer in a manufacturing process of a method for manufacturing a nitride semiconductor device; and

[0015] Figure 6 is a schematic cross-sectional view of a main part of a nitride semiconductor layer in a manufacturing process of a method for manufacturing a nitride semiconductor device. Detailed Description

[0016] Hereinafter, a method for manufacturing a nitride semiconductor device including a nitride semiconductor layer will be described with reference to the accompanying drawings. Hereinafter, a process from an ion implantation process to an annealing process for activating implanted p-type impurities in a manufacturing process of a nitride semiconductor device will be described. For steps other than these in the steps of manufacturing a nitride semiconductor device, known manufacturing methods can be used.

[0017] As used herein, "nitride semiconductor" is a compound defined by In Figure 1 , Y , Figure 1 , , 1-X-Y , Figures 2 to 6 ,

[0018] Al Y Ga 1-X-Y N (where 0 ≤ X ≤ 1, 0 ≤ Y ≤ 1). In addition, aluminum gallium nitride (AlGaN) is a nitride semiconductor corresponding to X = 0 and 0 < Y < 1 in the above definition. Indium aluminum nitride (InAlN) is a nitride semiconductor corresponding to X + Y = 1, 0 < X < 1, and 0 < Y < 1 as defined above.

[0018] Figure 1 is a flowchart of a part of a method for manufacturing a nitride semiconductor device. Figures 2 to 6 Schematically shows in conjunction with Figure 11 is a cross-sectional view of a main portion of a nitride semiconductor layer in a manufacturing process corresponding to the flowchart.

[0019] First, if Figure 2 As shown, a semiconductor substrate 12 is prepared, and a first nitride semiconductor layer 14 ( Figure 1 Step S1). Semiconductor substrate 12 can be any material as long as it can grow nitride semiconductor crystals. In this example, the material of semiconductor substrate 12 is gallium nitride (GaN) containing a high concentration of n-type impurities. First nitride semiconductor layer 14 is not particularly limited, but can be formed on semiconductor substrate 12 using, for example, MOCVD (metal organic chemical vapor deposition) technology. In this example, the material of first nitride semiconductor layer 14 is gallium nitride (GaN) containing a low concentration of n-type impurities.

[0020] The first nitride semiconductor layer 14 is formed with various diffusion regions that provide functional structures for implementing electrical functions. Such functional structures include, for example, functional structure types that apply switching functions, such as MISFET (Metal Insulator Semiconductor Field Effect Transistor) and MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or functional structure types that apply rectification functions, such as diodes, which can be exemplified. The first nitride semiconductor layer 14 can correspond to the drift region that constitutes such MISFET and MOSFET, or can correspond to the high resistance region or cathode region that constitutes a diode. Below, a method for forming a p-type diffusion region in the first nitride semiconductor layer 14 is described. Such a p-type diffusion region can be a p-type body region or a p-type body contact region in MISFET and MOSFET, or can be a p-type anode region in a diode.

[0021] Next, if Figure 3 As shown, the p-type impurity is implanted into a portion of the upper surface of the first nitride semiconductor layer 14 using an ion implantation technique, and the p-type impurity is introduced into a portion of the upper layer portion of the first nitride semiconductor layer 14, thereby forming a p-type impurity introduction region 16 ( Figure 1 In step S2 of FIG. 1 , a p-type impurity introduction region 16 is formed at an exposed position on the upper surface of the first nitride semiconductor layer 14. The p-type impurity is not particularly limited, but may be, for example, magnesium (Mg). The p-type impurity may also be beryllium (Be) instead of magnesium. Furthermore, to promote activation, nitrogen (N) may be injected into the p-type impurity introduction region 16 as needed.

[0022] Next, if Figure 4As shown, a second nitride semiconductor layer 18 ( Figure 1 Step S3 in the process). The second nitride semiconductor layer 18 may not be particularly limited, but may be coherently grown and formed on the first nitride semiconductor layer 14 using, for example, MOCVD technology. Here, coherent growth refers to growth that maintains lattice continuity at the interface between the first nitride semiconductor layer 14 and the second nitride semiconductor layer 18 by distorting the lattice of the second nitride semiconductor layer 18 when the second nitride semiconductor layer 18 grows into a crystal, although there is a lattice mismatch between the first nitride semiconductor layer 14 and the second nitride semiconductor layer 18. The second nitride semiconductor layer 18 is a nitride semiconductor having a band gap different from that of the first nitride semiconductor layer 14. Typically, the second nitride semiconductor layer 18 is a nitride semiconductor having a band gap larger than that of the first nitride semiconductor layer 14. In this example, the second nitride semiconductor layer 18 is made of undoped or n-type aluminum gallium nitride (AlGaN).

[0023] Since the second nitride semiconductor layer 18 is coherently grown from the upper surface of the first nitride semiconductor layer 14 to form a film, as shown in FIG. Figure 4 As shown, a two-dimensional electron gas layer (2DEG) is formed on the first nitride semiconductor layer 14 side of the heterojunction surface between the first nitride semiconductor layer 14 and the second nitride semiconductor layer 18 by piezoelectric polarization. EF in the figure represents the Fermi level. As described above, the upper layer portion of the first nitride semiconductor layer 14 is an n-type region, and at least a portion of the p-type impurity introduced region 16 is an n-type region, that is, located in the two-dimensional electron gas layer (2DEG).

[0024] Next, annealing treatment is performed while the second nitride semiconductor layer 18 is formed on the first nitride semiconductor layer 14 ( Figure 1Step S4). The annealing temperature may not be particularly limited, but may be, for example, 1300°C to 1500°C. The formation energy of magnesium (Mg) as a p-type impurity replaced by gallium (Ga), that is, the energy required to activate magnesium, depends on the position of the Fermi level of the p-type impurity introduction region 16. The closer the position of the Fermi level of the p-type impurity introduction region 16 is to the valence band, that is, when the p-type impurity introduction region 16 is n-type, the lower the energy required to activate magnesium. Since the annealing treatment is performed in a state where a two-dimensional electron gas layer (2DEG) is formed on the upper portion of the first nitride semiconductor layer 14, the annealing treatment is performed under the condition that at least a portion of the p-type impurity introduction region 16 is arranged in the n-type region. Therefore, the p-type impurity in the p-type impurity introduction region 16 can be activated with low energy. In addition, the maximum concentration of the p-type impurity introduced into the p-type impurity introduction region 16 is adjusted to be less than the maximum charge density in the two-dimensional electron gas layer (2DEG). Therefore, during the annealing process, the upper layer portion of the first nitride semiconductor layer 14 remains in the n-type region. As a result, the p-type impurity introduced into the p-type impurity introduction region 16 can be activated efficiently.

[0025] Next, if Figure 5 As shown, the second nitride semiconductor layer 18 is removed ( Figure 1 When the second nitride semiconductor layer 18 is removed, the piezoelectric polarization disappears, and the p-type impurity-introduced region 16 becomes a p-type region. Thus, a highly active p-type region can be formed in the upper portion of the first nitride semiconductor layer 14.

[0026] In the above example, the second nitride semiconductor layer 18 is made of one nitride semiconductor layer. Figure 6 As shown, the second nitride semiconductor layer 18 may be made of a plurality of layers. Figure 6 The lower nitride semiconductor layer 18a and the upper nitride semiconductor layer 18b are stacked as shown. The lower nitride semiconductor layer 18a and the upper nitride semiconductor layer 18b are not particularly limited, but can be coherently grown and sequentially formed on the first nitride semiconductor layer 14 using, for example, MOCVD technology.

[0027] For example, the lower nitride semiconductor layer 18a and the upper nitride semiconductor layer 18b may be made of AlGaN, or may be configured such that the composition ratio of aluminum is different from each other. As an example, the lower nitride semiconductor layer 18a may be AlGaN. 0.2 Ga 0.8 N, and the upper nitride semiconductor layer 18b may be Al 0.4 Ga 0.6N. When the aluminum composition ratio in the lower nitride semiconductor layer 18a in contact with the first nitride semiconductor layer 14 is small, the lattice mismatch between the first nitride semiconductor layer 14 and the lower nitride semiconductor layer 18a is suppressed, and the generation of cracks during the annealing process is suppressed. When the aluminum composition ratio in the upper nitride semiconductor layer 18b on the outermost surface is large, the escape of nitrogen from the surface of the upper nitride semiconductor layer 18b is suppressed, thereby improving the heat resistance. In order to ensure practical heat resistance, the aluminum composition ratio in the upper nitride semiconductor layer 18b can be 40% or more. Instead of two different stacked structures of the lower nitride semiconductor layer 18a and the upper nitride semiconductor layer 18b, the second nitride semiconductor layer 18 can have a three-layer or more layer structure so that the aluminum composition ratio increases in a multi-stage manner from the first nitride semiconductor layer 14 side toward the outermost surface. Alternatively, the aluminum composition ratio may increase continuously from the first nitride semiconductor layer 14 side toward the outermost surface. Alternatively, the second nitride semiconductor layer 18 may have a structure having a combination of the above-described configurations. In any case, the aluminum composition ratio in the second nitride semiconductor layer 18 may be configured so that the portion in contact with the first nitride semiconductor layer 14 is the smallest and the outermost surface is the largest. As a result, crack suppression and nitrogen leakage suppression can be excellently achieved.

[0028] For example, the lower nitride semiconductor layer 18a can be indium aluminum nitride (InAlN), and the upper nitride semiconductor layer 18b can be aluminum gallium nitride (AlGaN). The charge density of the two-dimensional electron gas layer (2DEG) formed on the heterojunction surface of InAlN / GaN is higher than the charge density of the two-dimensional electron gas layer (2DEG) formed on the heterojunction surface of AlGaN / GaN. Therefore, when the lower nitride semiconductor layer 18a is made of indium aluminum nitride (InAlN), a high-density two-dimensional electron gas layer (2DEG) is formed on the upper portion of the first nitride semiconductor layer 14. Therefore, even if the p-type impurity concentration of the p-type impurity introduction region 16 is increased, the n-type region can be maintained during the annealing process, thereby forming a p-type high-concentration region in the upper portion of the first nitride semiconductor layer 14.

[0029] The features of the technology disclosed in this disclosure are summarized below. It should be noted that the technical elements described below are independent technical elements and demonstrate technical usefulness alone or in various combinations, and are not limited to the combinations described in this specification at the time of filing.

[0030] The method for manufacturing a nitride semiconductor device disclosed in this specification includes: a p-type impurity introduction step for introducing a p-type impurity into at least a portion of an upper portion of a first nitride semiconductor layer to form a p-type impurity introduction region; a film formation step for forming a second nitride semiconductor layer on an upper surface of the first nitride semiconductor layer to include the p-type impurity introduction region, wherein the second nitride semiconductor layer is formed by coherent growth in the film formation step; and an annealing step for performing an annealing treatment under conditions under which the second nitride semiconductor layer is formed on the first nitride semiconductor layer. The second nitride semiconductor layer can be a nitride semiconductor having a band gap different from that of the first nitride semiconductor layer. Typically, the second nitride semiconductor layer can be a nitride semiconductor having a larger band gap than the first nitride semiconductor layer.

[0031] In the film formation step, the second nitride semiconductor layer can be formed by stacking nitride semiconductors with different composition ratios. For example, the first nitride semiconductor layer can be made of GaN, and the second nitride semiconductor layer can be made of AlGaN. In this case, in the second step, the second nitride semiconductor layer can be formed so that the composition ratio of aluminum increases from the first nitride semiconductor layer side toward the outermost surface. This can suppress the generation of cracks and the release of nitrogen. Alternatively, the first nitride semiconductor layer can be made of GaN, and the second nitride semiconductor layer can be made of a stacked layer of InAlN and AlGaN. A high-concentration p-type region can be formed in the upper portion of the first nitride semiconductor layer.

[0032] When the first nitride semiconductor layer is made of GaN, the annealing temperature in the annealing treatment step may be 1300° C. to 1500° C. This can increase the energy required to activate the p-type impurity.

[0033] In the film forming step, the second nitride semiconductor layer can be formed by using MOCVD technology.

[0034] Although specific examples of the present disclosure have been described in detail above, these are merely examples and do not limit the scope of this specification. The technology described in this specification includes various modifications and variations of the specific examples illustrated above. In addition, the technical elements described in this specification or the drawings demonstrate technical usefulness individually or in various combinations, and are not limited to the combinations described in this specification at the time of filing the application. In addition, the technology illustrated in this specification or the drawings can achieve multiple purposes simultaneously, but achieving one of the purposes itself has technical practicality.

Claims

1. A method for manufacturing a nitride semiconductor device, the method comprising: a p-type impurity introducing step of introducing a p-type impurity into at least a portion of an upper layer portion of the first nitride semiconductor layer to form a p-type impurity introduced region; a film forming step of forming a second nitride semiconductor layer from an upper surface of the first nitride semiconductor layer to include the p-type impurity introduction region, the second nitride semiconductor layer being coherently grown and formed, wherein, in the film forming step, the second nitride semiconductor layer is formed by stacking nitride semiconductor layers having different composition ratios; an annealing step of performing an annealing step in a state where the second nitride semiconductor layer is formed on the first nitride semiconductor layer and the p-type impurity-introduced region, wherein the p-type impurity-introduced region is located in a two-dimensional electron gas layer of the first nitride semiconductor layer; as well as A step of removing the second nitride semiconductor layer after the annealing step.

2. The method for manufacturing a nitride semiconductor device according to claim 1, wherein: The first nitride semiconductor layer is made of GaN; The second nitride semiconductor layer is made of AlGaN; and In the film forming step, the second nitride semiconductor layer is formed so that the composition ratio of aluminum increases from the first nitride semiconductor layer side toward the outermost surface.

3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein: The first nitride semiconductor layer is made of GaN; The second nitride semiconductor layer is composed of a stacked layer of InAlN and AlGaN.

4. The method for manufacturing a nitride semiconductor device according to claim 2, wherein: The annealing temperature in the annealing step is set between 1300°C and 1500°C.

5. The method for manufacturing a nitride semiconductor device according to any one of claims 1 to 4, wherein: In the film forming step, the second nitride semiconductor layer is formed by MOCVD technology.

Images