Method for manufacturing semiconductor structure

Abstract

The present invention discloses a method for manufacturing a semiconductor structure, the method comprising forming a material stack on a substrate and covering its array region and peripheral region; forming a first patterned mask layer on the material stack; transferring the pattern of the first patterned mask layer to the material stack, and forming a first array pattern and a first peripheral pattern in the array region and the peripheral region; providing a second patterned mask layer above the first array pattern and the first peripheral pattern, and the patterns of the second and first patterned mask layers are staggered; transferring the pattern of the second patterned mask layer downward, and forming a first and a second sacrificial pattern in the array region and the peripheral region; and simultaneously transferring the pattern of the first array pattern, the first sacrificial pattern, the first peripheral pattern and the second sacrificial pattern, so as to form a second array pattern and a second peripheral pattern in the array region and the peripheral region, respectively. The method for manufacturing a semiconductor structure proposed by the present invention can simplify the process steps and reduce costs.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor structure, and more particularly to a method for manufacturing a material layer in an array region and a peripheral region of a patterned semiconductor structure. Background Art

[0002] In recent years, as the manufacturing technology of dynamic random access memory (DRAM) devices continues to develop towards the miniaturization of device size, many challenges have arisen. For example, the material layers of the array area and the peripheral area of ​​the semiconductor structure are traditionally patterned separately, and in response to the reduced device size, multiple precision steps are required to produce the pattern, which takes a long process time and is also quite expensive. Therefore, the industry still needs to improve the manufacturing method of dynamic random access memory devices, especially to overcome the various problems that may arise from the patterning process under the reduced device size. Summary of the invention

[0003] The present invention provides a method for manufacturing a semiconductor structure, comprising: forming a first material stack on a substrate, the substrate comprising an array region and a peripheral region, wherein the first material stack covers the array region and the peripheral region, and the first material stack comprises a first pattern transfer layer and a second pattern transfer layer; forming a first patterned mask layer on the first material stack in the array region and the peripheral region, the first patterned mask layer exposing a portion of the top surface of the first material stack; removing a portion of the first material stack using the first patterned mask layer as a mask to transfer the pattern of the first patterned mask layer to the second pattern transfer layer, and forming a first array pattern and a first peripheral pattern in the array region and the peripheral region, respectively. edge pattern; providing a second patterned mask layer above the first array pattern and the first peripheral pattern corresponding to the array area and the peripheral area, wherein the pattern of the second patterned mask layer is staggered with the pattern of the first patterned mask layer (for example, in the first direction); using the second patterned mask layer as a mask to transfer the pattern of the second patterned mask layer downward, and forming a first sacrificial pattern and a second sacrificial pattern in the array area and the peripheral area respectively; and pattern-transferring the first array pattern and the first sacrificial pattern to form a second array pattern in the array area, and pattern-transferring the first peripheral pattern and the second sacrificial pattern to form a second peripheral pattern in the peripheral area.

[0004] In addition, in one embodiment, after forming the second array pattern and the second peripheral pattern, the manufacturing method of the semiconductor structure further includes: forming a second material stack on the second array pattern and the second peripheral pattern; forming a third patterned mask layer on the second material stack in the array area and the peripheral area; and performing a self-aligned double patterning process according to the pattern of the third patterned mask layer to form a patterned material stack layer, wherein the patterned material stack layer includes a third array pattern formed in the array area.

[0005] In addition, in one embodiment, after forming the third array pattern, the manufacturing method of the semiconductor structure further includes: forming a fourth patterned mask layer to cover the peripheral area and expose the third array pattern of the array area; and using the fourth patterned mask layer and the third array pattern as masks to remove the exposed portion of the underlying material layer and the corresponding portion of the second array pattern to convert the second array pattern into a final array pattern.

[0006] The embodiment of the present invention defines a pattern in the array region along the first direction while defining a pattern in the peripheral region. Compared with the conventional process in which the array pattern and the peripheral pattern are separately manufactured, the manufacturing method of the semiconductor structure proposed by the present invention can simplify the process steps and reduce the cost. In addition, since the present invention only needs to use a SADP process once to obtain a high-density array pattern, it only needs to use a high-level immersion lithography technology once, which can significantly reduce the manufacturing cost compared with the conventional method that requires multiple (for example, more than four) complex and expensive SADP processes to obtain an array pattern of the same density. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0008] Figure 1A , Figure 1B , Figure 2-Figure 5 , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Figure 8-Figure 15 , Fig.16A , Fig. 16B , Fig.17 is a schematic diagram of a semiconductor structure at different manufacturing stages according to an embodiment of the present invention, wherein: Figure 1B It is along Figure 1A A cross-sectional schematic diagram obtained along line BB in the top view schematic diagram;

[0009] Figure 6B Along the Fig. 6A A cross-sectional schematic diagram obtained along line BB in the top view schematic diagram;

[0010] Figure 7B Along the Fig. 7A A cross-sectional schematic diagram obtained along line BB in the top view schematic diagram;

[0011] Fig. 16B Along the Fig.16A A cross-sectional schematic diagram obtained along line BB in the top view schematic diagram.

[0012] Reference Numbers

[0013] 10: Substrate

[0014] 11: Cap layer

[0015] 12: Target material layer

[0016] 12-1: Tungsten nitride layer

[0017] 12-2: Tungsten layer

[0018] 120a: target array pattern

[0019] 120b: Target surrounding pattern

[0020] 13: Carbide layer

[0021] 14,18: Dielectric layer

[0022] 15,150: Nitrogen-containing layer

[0023] 16,160,21,210,34,340: Polysilicon layer

[0024] 17,22,220,25,250,31,310,35,350:Carbon layer

[0025] 21a: First array pattern

[0026] 21b: First peripheral pattern

[0027] 211,212,241,242,271,272,291,292,371,372: Open

[0028] 23,230,26,260,36: Anti-reflection layer

[0029] 24,27,37,46: Patterned mask layer

[0030] 24a,24b,27a,27b,37a,37b: Mask pattern

[0031] 25S: Sacrificial pattern layer

[0032] 25S-a: First sacrificial pattern

[0033] 25S-b: Second sacrificial pattern

[0034] 29,290: Polysilicon pattern layer

[0035] 29a: Second array pattern

[0036] 29b: Second peripheral pattern (final peripheral pattern)

[0037] 290a: Final array pattern

[0038] 32,320: Nitride layer

[0039] 32a: first nitridation pattern

[0040] 32b: Second nitride pattern

[0041] 33,330: Silicon oxide layer

[0042] 38: Core pattern layer

[0043] 38a: First core pattern

[0044] 38b: Second core pattern

[0045] 41,410: Spacer material layer

[0046] 42,420,42R: planarization layer

[0047] 43: Patterned stacking layer

[0048] 43a: First stack

[0049] 43b: Second stack

[0050] 43': Patterned material stacking layer

[0051] 43a': first material stack (third array pattern)

[0052] 43b': Second material stack

[0053] A1: Array area

[0054] A2: Surrounding area

[0055] BB:Line

[0056] D1,D2,D3,Dc: Direction

[0057] ML-1: First material stack

[0058] ML-2: Second material layer

[0059] L1, L2, L3: Pattern transfer layer DETAILED DESCRIPTION

[0060] Reference Figure 1A , Figure 1B , providing a substrate 10 and a first material stack ML-1, the substrate 10 includes an array area A1 and a peripheral area A2. In one embodiment, the material of the substrate 10 may include a semiconductor material. In one embodiment, the substrate 10 includes silicon, gallium arsenide, gallium nitride, silicon germanium, other suitable materials or a combination of the foregoing. In one embodiment, the substrate 10 is a silicon on insulator substrate. Various components, such as buried word lines, isolation structures, bit lines, etc., may be formed in and above the substrate 10. To simplify the diagram and description here, these components are omitted in the diagram.

[0061] The first material stack ML-1 is formed above the substrate 10 and covers the array area A1 and the peripheral area A2. The first material stack ML-1 includes a plurality of materials, for example, a dielectric layer 14, a pattern transfer layer L1, a dielectric layer 18, and a pattern transfer layer L2 sequentially formed above the substrate 10. In one embodiment, the formation method of the plurality of material layers included in the first material stack ML-1 may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), spin coating, other suitable processes, or a combination of the foregoing. In one embodiment, the dielectric layer 14 and the dielectric layer 18 include insulating materials, such as silicon nitride (SiN). In one example, the thickness of the dielectric layer 18 is approximately (but not limited to) 30 nm, and the thickness of the dielectric layer 14 is approximately (but not limited to) 70 nm.

[0062] In one embodiment, the pattern transfer layer L1 includes a nitrogen-containing layer 15, a polysilicon layer 16, and a carbon-containing layer 17 formed sequentially above the dielectric layer 14. The nitrogen-containing layer 15, for example, includes a different material from the dielectric layer 14. In this example, the nitrogen-containing layer 15 is an oxygen-rich silicon oxynitride (O-rich SiON). The carbon-containing layer 17 includes a carbide, such as diamond-like carbon, an amorphous carbon film, a highly selective transparent carbon-containing layer, and the thickness can be (but not limited to) about 70nm to about 100nm. In this example, the carbon-containing layer 17 is a highly selective transparent carbon-containing layer. Here, the pattern transfer layer L1 is described as including the nitrogen-containing layer 15, the polysilicon layer 16, and the carbon-containing layer 17, but the present invention is not limited thereto. In other embodiments, the pattern transfer layer L1 can also be a combination of other material layers suitable for pattern transfer.

[0063] In one embodiment, the pattern transfer layer L2 includes a polysilicon layer 21, a carbon-containing layer 22, and an anti-reflection layer 23 formed in sequence above the dielectric layer 18. The carbon-containing layer 22, for example, includes a carbide, such as diamond-like carbon, an amorphous carbon film, and a highly selective transparent carbon-containing layer. In this example, the carbon-containing layer 22 is a spin-on carbon layer. The material of the anti-reflection layer 23, for example, includes an organic polymer, carbon, or silicon oxynitride. Here, the pattern transfer layer L2 is described as including a nitrogen-containing layer 15, a polysilicon layer 16, and a carbon-containing layer 17, but the present invention is not limited thereto. In other embodiments, the pattern transfer layer L2 may also be a combination of other material layers suitable for pattern transfer.

[0064] In one embodiment, a target material layer 12 and other material layers are further provided between the substrate 10 and the first material stack ML-1 to cover the array area A1 and the peripheral area A2. For example, a cap layer 11, a target material layer 12, and a carbide layer 13 are sequentially formed on the substrate 10 between the substrate 10 and the first material stack ML-1. The formation method of the cap layer 11, the target material layer 12, and the carbide layer 13 may include, for example, PVD, CVD, ALD, spin coating, other suitable processes, or a combination of the foregoing.

[0065] The cap layer 11 is, for example, a silicon nitride layer or other suitable insulating material. The target material layer 12 is, for example, a single layer or a multilayer conductive material. In one embodiment, the target material layer 12 may include tungsten, tungsten nitride, copper, aluminum-copper alloy, polysilicon, silicon germanium, other suitable conductive materials, or a combination of the foregoing. In this example, the target material layer 12 may include, for example, a tungsten nitride layer 12-1 and a tungsten layer 12-2. The carbide layer 13 includes, for example, diamond-like carbon, an amorphous carbon film, or a highly selective transparent carbon-containing layer. In this example, the carbide layer 13 is a highly selective transparent carbon-containing layer.

[0066] Please refer to Figure 1A , Figure 1B A patterned mask layer 24 (e.g., a patterned photoresist) is provided above the first material stack ML-1, wherein the patterned mask layer 24 exposes a portion of the top surface of the first material stack ML-1. The patterned mask layer 24 includes a mask pattern 24a and a mask pattern 24b, which are formed on the anti-reflection layer 23 in the array area A1 and the peripheral area A2, respectively, and expose a portion of the top surface of the anti-reflection layer 23. In addition, the mask pattern 24a includes an opening 241, and the mask pattern 24b includes an opening 242.

[0067] Next, please refer to Figure 1A-1B , Figure 2-Figure 5 , Fig. 6A, Figure 6B In the present invention, the final peripheral pattern (eg, Fig. 6A , Figure 6B The second peripheral pattern 29b shown in FIG. 1 is also used to define a linear pattern (eg, Fig. 6A , Figure 6B In brief, the present invention first undergoes a first-stage photolithography process (such as Figure 1A-1B and Figure 2-Figure 3 The first array pattern 21a and the first peripheral pattern 21b (described above) are formed with a larger line width. Figure 3 ), followed by the second stage of photolithography and etching process (such as Figure 4-Figure 5 and Figure 6A-6B The pattern density of the first array pattern 21a and the first peripheral pattern 21b is further increased to form the second array pattern 29a and the second peripheral pattern 29b ( Figure 6A-6B ).

[0068] Please refer to Figure 1A-1B and Figure 2 Then, the patterned mask layer 24 is used as a mask to remove the pattern transfer layer L2 not covered by the patterned mask layer 24. In one embodiment, for example, a dry etching process is used to remove the anti-reflection layer 23 exposed by the openings 241 and 242 and the corresponding carbon-containing layer 22 and polysilicon layer 21 underneath. Figure 2 As shown, after etching, the pattern of the patterned mask layer 24 is transferred to the underlying pattern transfer layer L2 to form an anti-reflective layer 230, a carbon-containing layer 220, and a polysilicon layer 210. In this exemplary step, the dielectric layer 18 may serve as an etching stop layer.

[0069] Afterwards, if Figure 3 As shown, the patterned mask layer 24, the carbon-containing layer 220, and the anti-reflection layer 230 are removed, leaving the polysilicon layer 210. The polysilicon layer 210 includes a first array pattern 21a in the array area A1 and a first peripheral pattern 21b in the peripheral area A2. In addition, the first array pattern 21a includes an opening 211, and the first peripheral pattern 21b includes an opening 212. The openings 211 and 212 expose a portion of the top surface of the dielectric layer 18. In one embodiment, the first array pattern 21a and the first peripheral pattern 21b extend, for example, along a direction D2. In addition, the first array pattern 21a and the first peripheral pattern 21b are separated, for example, in a direction D1.

[0070] Then, if Figure 4As shown, a carbon-containing layer 25 and an anti-reflection layer 26 are sequentially formed above the polysilicon layer 210. The method for forming the carbon-containing layer 25 and the anti-reflection layer 26 may include PVD, CVD, ALD, spin coating, other suitable processes or a combination of the foregoing. The carbon-containing layer 25 completely covers the first array pattern 21a and the first peripheral pattern 21b, and fills the opening 211 and the opening 212. The carbon-containing layer 25, for example, includes a carbide, such as diamond-like carbon, an amorphous carbon film, and a highly selective transparent carbon-containing layer. In this example, the carbon-containing layer 25 is a spin-coated carbon layer. The anti-reflection layer 26, for example, includes an organic polymer, carbon or silicon oxynitride.

[0071] Please refer to Figure 4 , a patterned mask layer 27 (e.g., a patterned photoresist layer) is formed on the anti-reflection layer 26, wherein the patterned mask layer 27 includes a mask pattern 27a and a mask pattern 27b, which are formed on the anti-reflection layer 26 in the array area A1 and the peripheral area A2, respectively, and expose a portion of the top surface of the anti-reflection layer 26. In addition, the mask pattern 27a includes an opening 271, and the mask pattern 27b includes an opening 272. Furthermore, the pattern of the patterned mask layer 27 and the pattern of the polysilicon layer 210 (i.e., the pattern of the patterned mask layer 24) are staggered, for example, staggered in the direction D1. For example Figure 4 As shown, the opening 271 of the mask pattern 27a corresponds to the first array pattern 21a of the underlying polysilicon layer 210, and the opening 272 of the mask pattern 27b corresponds to the first peripheral pattern 21b of the underlying polysilicon layer 210. In one embodiment, the extension direction of the mask pattern 24a is substantially the same as the extension direction of the mask pattern 27a.

[0072] It is worth noting that Figure 4 The mask pattern 27b of the middle peripheral area A2 only shows one example pattern of the portion adjacent to the array area A1. The peripheral area A2 can also increase the density of the peripheral pattern in other areas not shown by using the staggered pattern method like the array area A1. Therefore, the actual pattern of the mask pattern 27b depends on the application design.

[0073] Then, if Figure 5 As shown, the patterned mask layer 27 is used as a mask to remove the anti-reflection layer 26 and the carbon-containing layer 25 not covered by the patterned mask layer 27. In one embodiment, for example, a dry etching process is used to remove the anti-reflection layer 26 exposed by the openings 271 and 272 and the corresponding carbon-containing layer 25 thereunder. Figure 5 As shown, after etching, the pattern of the patterned mask layer 27 is transferred to the bottom to form the carbon-containing layer 250 and the anti-reflection layer 260. In this exemplary step, the dielectric layer 18 can be used as an etch stop layer. Afterwards, the patterned mask layer 27 is removed, for example, by an ashing process.

[0074] like Figure 5 As shown, the stacked carbon-containing layer 250 and the anti-reflection layer 260 constitute a sacrificial pattern layer 25S. The sacrificial pattern layer 25S includes a first sacrificial pattern 25S-a in the array area A1 and a second sacrificial pattern 25S-b in the peripheral area A2. In one embodiment, the first sacrificial pattern 25S-a, for example, extends along the direction D2. Furthermore, the first sacrificial pattern 25S-a and the second sacrificial pattern 25S-b, for example, are separated in the direction D1. In addition, in this example, the first sacrificial pattern 25S-a and the first array pattern 21a in the array area A1 are staggered on the dielectric layer 18. The second sacrificial pattern 25S-b in the peripheral area A2 covers a portion of the first peripheral pattern 21b or is staggered with a portion of the first peripheral pattern 21b depending on the peripheral pattern to be formed in the end, and the present invention does not impose any restrictions on this.

[0075] Then, if Fig. 6A , Figure 6B As shown, the sacrificial pattern layer 25S and the polysilicon layer 210 are used as masks to remove the dielectric layer 18 and the pattern transfer layer L1 that are not covered by the sacrificial pattern layer 25S and the polysilicon layer 210. In one embodiment, for example, a dry etching process is used to remove the dielectric layer 18 exposed by the openings of the sacrificial pattern layer 25S and the polysilicon layer 210 and the corresponding carbon-containing layer 17, polysilicon layer 16 and nitrogen-containing layer 15 thereunder. After etching, the patterns of the sacrificial pattern layer 25S and the polysilicon layer 210 are transferred to the dielectric layer 18 and the pattern transfer layer L1 thereunder to form the remaining dielectric layer (not shown), the remaining carbon-containing layer (not shown), the polysilicon layer 160 and the nitrogen-containing layer 150. In this exemplary step, the dielectric layer 14 serves as an etching stop layer.

[0076] Afterwards, the sacrificial pattern layer 25S, the polysilicon layer 210, the remaining dielectric layer 18 and the remaining carbon-containing layer 17 may be removed by one or more steps including an ashing process, an etching process, etc. Figure 6B As shown, the polysilicon layer 160 and the nitrogen-containing layer 150 constitute a polysilicon pattern layer 29. The polysilicon pattern layer 29 includes a second array pattern 29a in the array area A1 and a second peripheral pattern 29b in the peripheral area A2. In addition, the second array pattern 29a includes an opening 291, and the second peripheral pattern 29b includes an opening 292. The openings 291 and 292 are to expose a portion of the top surface of the dielectric layer 14.

[0077] At this point, the present invention has defined the final peripheral pattern (i.e., the second peripheral pattern 29b) in the peripheral area A2 through the above two-stage photolithography process, and while defining the final peripheral pattern 29b in the peripheral area A2, defines the pattern (the second array pattern 29a) extending along a specific direction in the array area A1. Fig. 7A , Figure 7B , Figure 8-Figure 13 To illustrate, the present invention then defines a pattern extending along another direction in the array region A1 using a self-aligned double patterning (SADP) process (eg Fig.13 The third array pattern 43a').

[0078] Reference Fig. 7A , Figure 7B , a second material stack ML-2 is formed above the polysilicon pattern layer 29. The second material stack ML-2 includes a plurality of materials, for example, a carbon-containing layer 31, a nitride layer 32, a silicon oxide layer 33 and a pattern transfer layer L3 formed in sequence above the polysilicon pattern layer 29. The formation method of the plurality of material layers included in the second material stack ML-2 may include, for example, PVD, CVD, ALD, spin coating, other suitable processes or a combination of the foregoing. The carbon-containing layer 31 completely covers the second array pattern 29a and the second peripheral pattern 29b, and fills the openings 291 and 292. The carbon-containing layer 31 includes, for example, diamond-like carbon, an amorphous carbon film, and a highly selective transparent carbon-containing layer. In this example, the carbon-containing layer 31 is a spin-on carbon layer. The nitride layer 32, for example, includes a different material from the dielectric layer 14. In this example, the nitride layer 32 may include, for example, nitrogen-rich silicon oxynitride (N-rich SiON). The silicon oxide layer 33 may include, for example, a Tetraethyl orthosilicate (TEOS) layer.

[0079] In one embodiment, the pattern transfer layer L3 includes a polysilicon layer 34, a carbon-containing layer 35, and an anti-reflection layer 36 formed in sequence on the silicon oxide layer 33. The carbon-containing layer 35, for example, includes a carbide, such as diamond-like carbon, an amorphous carbon film, and a highly selective transparent carbon-containing layer. In this example, the carbon-containing layer 35 is a spin-on carbon layer. The material of the anti-reflection layer 36, for example, includes an organic polymer, carbon or silicon oxynitride. Here, the pattern transfer layer L3 is described as including a polysilicon layer 34, a carbon-containing layer 35, and an anti-reflection layer 36, but the present invention is not limited thereto. In other embodiments, the pattern transfer layer L3 may also be a combination of other material layers suitable for pattern transfer.

[0080] Please refer to Fig. 7A , Figure 7B, a patterned mask layer 37 (e.g., a patterned photoresist) is formed on the second material stack ML-2, wherein the patterned mask layer 37 exposes a portion of the top surface of the second material stack ML-2. The patterned mask layer 37 includes a mask pattern 37a and a mask pattern 37b, which are formed on the anti-reflection layer 36 in the array area A1 and the peripheral area A2, respectively, and expose a portion of the top surface of the anti-reflection layer 36. In addition, the mask pattern 37a includes an opening 371, and the mask pattern 37b includes an opening 372.

[0081] like Fig. 7A , Figure 7B As shown, the mask pattern 37a includes a linear pattern separated in the direction D1 and extending along the direction Dc. The direction Dc, for example, has an angle greater than 0 degrees and less than 90 degrees with the direction D1, but the present invention is not limited thereto. In other embodiments, the mask pattern 37a may also include a linear pattern separated in the direction D2 and extending substantially along the direction D1.

[0082] Next, please refer to Figure 8 , using the patterned mask layer 37 as an etching mask, the pattern transfer layer L3 not covered by the patterned mask layer 37 is removed. In one embodiment, for example, a dry etching process is used to remove the anti-reflection layer 36 exposed by the openings 371 and 372 and the corresponding carbon-containing layer 35 and polysilicon layer 34 thereunder. After etching, the pattern of the patterned mask layer 37 is transferred to the pattern transfer layer L3 thereunder to form the remaining anti-reflection layer 36 (not shown), the carbon-containing layer 350 and the polysilicon layer 340. In this exemplary step, the silicon oxide layer 33 serves as an etching stop layer.

[0083] Afterwards, the patterned mask layer 37 and the remaining anti-reflection layer 36 may be removed by ashing process, etching process, etc. Figure 8 As shown, the carbon-containing layer 350 and the polysilicon layer 340 constitute a core pattern layer 38. The core pattern layer 38 includes a first core pattern 38a in the array region A1 and a second core pattern 38b in the peripheral region A2.

[0084] Then, if Fig. 9As shown, a spacer material layer 41 is deposited above the silicon oxide layer 33 and the core pattern layer 38. The spacer material layer 41 conformably covers the core pattern layer 38. For example, the spacer material layer 41 covers the top surface and sidewalls of the first core pattern 38a and the second core pattern 38b, and covers the exposed portion of the silicon oxide layer 330. The spacer material layer 41 may, for example, include oxide, and its formation method may include PVD, CVD, ALD, spin coating, other suitable processes or a combination of the foregoing. The spacer material layer 41 may include the same or different materials as the silicon oxide layer 33. In this example, the spacer material layer 41 is a tetraethyl orthosilicate (TEOS) layer.

[0085] Afterwards, if Fig.10 As shown, a planarization layer 42 is formed on the spacer material layer 41. The planarization layer 42 completely covers the spacer material layer 41 and fills the gaps between the spacer material layers 41. The planarization layer 42 includes, for example, an organic dielectric layer, such as diamond-like carbon, an amorphous carbon film, a highly selective transparent carbon-containing layer, or other suitable materials, and its formation method may include PVD, CVD, ALD, spin coating, other suitable processes or a combination of the foregoing. In this example, the planarization layer 42 is a spin-coated carbon layer.

[0086] Then, if Fig.11 As shown, a portion of the planarization layer 42 and a portion of the spacer material layer 41 are removed until the top surface of the core pattern layer 38 is exposed. The method of removing a portion of the planarization layer 42 and a portion of the spacer material layer 41 may include, for example, an etch-back process or a chemical mechanical polishing process. After this removal step, the remaining planarization layer 42R is filled between the remaining spacer material layers 41, and the top surface of the planarization layer 42R is substantially flush with the top surface of the spacer material layer 41.

[0087] Afterwards, please refer to Fig.12 , using the planarization layer 42R and the core pattern layer 38 as masks, the spacer material layer 41 and the silicon oxide layer 33 not covered by the planarization layer 42R and the core pattern layer 38 are removed to form a patterned stacking layer 43. In one embodiment, for example, a dry etching process is used to remove the spacer material layer 41 and the silicon oxide layer 33 not covered by the planarization layer 42R and the core pattern layer 38 until the nitride layer 32 is exposed. In this exemplary step, the nitride layer 32 can be used as an etching stop layer.

[0088] like Fig.12As shown, the patterned stacking layer 43 formed after etching includes two types of three-layer material stacks arranged alternately. Among them, the first three-layer material stack includes a carbon-containing layer 350, a polysilicon layer 340, and a silicon oxide layer 330 from top to bottom; the other three-layer material stack includes a planarization layer 420, a spacer material layer 410, and a silicon oxide layer 330 from top to bottom. Furthermore, if the formation area is distinguished, the patterned stacking layer 43 includes a plurality of first stacks 43a in the array area A1 and a plurality of second stacks 43b in the peripheral area A2.

[0089] Please refer to Fig.13 , then, the carbon-containing layer 350 and the planarization layer 420 are removed to form a patterned material stack layer 43'. The patterned material stack layer 43' includes a first material stack 43a' in the array area A1 and a second material stack 43b' in the peripheral area A2. In this example, the first material stack 43a' can be used as a third array pattern. In this example, the third array pattern 43a' includes being separated in the direction D1 and along the direction Dc (such as Fig. 7A In other embodiments, the mask pattern 37a may also include linear patterns separated in the direction D2 and extending substantially along the direction D1.

[0090] At this point, the present invention defines a pattern extending in another direction (ie, the third array pattern 43a') in the array area A1 by using the above-mentioned SADP process. Figure 13-Figure 15 , Fig.16A , Fig. 16B The present invention then uses an etching process to etch the lower material layer using the third array pattern 43a' as an etching mask to transform the lower second array pattern 29a into a final array pattern (eg Fig.16A , Fig. 16B The final array pattern shown is 290a).

[0091] Refer to Fig.13 , a patterned mask layer 46 (e.g., patterned photoresist) is formed on the second material stack 43b' and the nitride layer 32 in the peripheral area A2. The patterned mask layer 46 covers the second material stack 43b' and fills the opening between the second material stack 43b', thereby exposing the third array pattern 43a' of the array area A1. In one embodiment, the patterned mask layer 46 may further cover a portion of the array area A1 adjacent to the peripheral area A2 (e.g., Fig.13 However, the present invention is not limited thereto, and whether the patterned mask layer 46 covers a portion of the array area A1 adjacent to the aforementioned boundary can be determined based on the target pattern to be formed at the boundary between the array area A1 and the peripheral area A2 in actual applications.

[0092] Next, please refer to Fig.14 , using the patterned mask layer 46 and the third array pattern 43a' as masks, remove the exposed portion of the underlying material layer, for example, remove the exposed portion of the nitride layer 32 by etching until the carbon-containing layer 31 is exposed, and the remaining nitride layer 32 forms a nitride layer 320. Then, the patterned mask layer 46 and the patterned material stack layer 43' can be removed by one or more steps including an ashing process, an etching process, etc. In this example, after removing the patterned mask layer 46, the patterned material stack layer 43' is removed to leave the nitride layer 320. Fig.14 As shown, the nitride layer 320 includes a first nitride pattern 32 a in the array area A1 and a second nitride pattern 32 b in the peripheral area A2 .

[0093] Then, if Fig.15 As shown, the carbon-containing layer 31 and the polysilicon pattern layer 29 not covered by the nitride layer 320 are removed by using the nitride layer 320 as a mask, thereby forming a carbon-containing layer 310 and a polysilicon pattern layer 290. In one embodiment, for example, a dry etching process is used to remove the carbon-containing layer 31 not covered by the first nitride pattern 32a and the corresponding second array pattern 29a thereunder, thereby forming the nitride layer 320, the carbon-containing layer 310 and the final array pattern 290a. In this exemplary step, the dielectric layer 14 can be used as an etching stop layer.

[0094] Afterwards, refer to Fig.16A and Fig. 16B The nitride layer 320 and the carbon-containing layer 310 may be removed by one or more steps including an ashing process, an etching process, etc., to expose the polysilicon pattern layer 290. In one embodiment, a portion of the dielectric layer 14 may also be removed during this removal step. Fig.16A , Fig. 16B As shown, the polysilicon pattern layer 290 includes a final array pattern 290a and a second peripheral pattern (final peripheral pattern) 29b. It is particularly noted that, so far, the present invention has undergone Figure 1A , Figure 1B , Figures 2 to 3 and Figures 4 to 5 , Fig. 6A , Figure 6B The illustrated two-stage photolithography etching step, and Fig. 7A , Figure 7B , Figure 8-Figure 15 After the SADP step, a high-density target array pattern can be defined. Since the present invention only needs to use the SADP step once, it only needs to use the high-level immersion lithography technology once, which can significantly reduce the manufacturing cost.

[0095] Next, please refer to Fig.17, the pattern of the polysilicon pattern layer 290 can be transferred to the target material layer 12 by an etching process. For example, in this example, the polysilicon pattern layer 290 is used as a mask to etch the underlying material layers such as the dielectric layer 14, the carbide layer 13, the target material layer 12, and the cap layer 11. After etching, the final array pattern 290a and the second peripheral pattern 29b of the polysilicon pattern layer 290 are transferred to the target material layer 12, and a target array pattern 120a and a target peripheral pattern 120b are formed in the target material layer 12, respectively. In an application example of a DRAM device, the target array pattern 120a can correspond to the pattern of a capacitor contact pad.

[0096] According to an embodiment of the present invention, a method for manufacturing a semiconductor structure is firstly Figure 1A , Figure 1B , Figures 2 to 3 and Figure 4 , Fig. 6A , Figure 6B The two-stage photolithography process described in the example simultaneously defines the final peripheral pattern of the peripheral area A2 and the linear pattern of the array area A1 along a first direction. Fig. 7A , Figure 7B , Figures 8 to 15 In the SADP process described as an example, after defining a linear pattern in the array area A1 along a second direction, the linear pattern in the array area A1 along a first direction is etched using the linear pattern in the second direction as an etching mask to obtain a final array pattern in the array area A1. Finally, the final array pattern and the final peripheral pattern are simultaneously transferred to the target material layer to form the target array pattern and the target peripheral pattern of the present invention on the target material layer.

[0097] In summary, since the present invention defines the pattern of the array area A1 along the first direction while defining the pattern of the peripheral area A2, compared with the traditional process of separately manufacturing the array pattern and the peripheral pattern, the manufacturing method of the semiconductor structure proposed by the present invention can simplify the process steps and reduce the cost. In addition, since the present invention only needs to use the SADP process once to produce a high-density array pattern, it only needs to use a high-level immersion lithography technology once, which can greatly reduce the manufacturing cost compared with the traditional method of using multiple (for example, more than four times) complex and expensive SADP processes to produce the same density array pattern.

[0098] Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Relevant persons in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be based on the scope defined by the above-attached patent application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Forming a first material stack on a substrate, the substrate comprising an array region and a peripheral region, wherein the first material stack covers the array region and the peripheral region, and the first material stack comprises a first pattern transfer layer and a second pattern transfer layer; Forming a first patterned mask layer on the first material stack in the array region and the peripheral region, wherein the first patterned mask layer exposes a portion of the top surface of the first material stack; Using the first patterned mask layer as a mask to remove a portion of the first material stack, so as to transfer the pattern of the first patterned mask layer to the second pattern transfer layer, and to form a first array pattern and a first peripheral pattern in the array region and the peripheral region, respectively; Providing a second patterned mask layer above the first array pattern and the first peripheral pattern corresponding to the array region and the peripheral region, wherein the pattern of the second patterned mask layer is staggered with the pattern of the first patterned mask layer; Using the second patterned mask layer as a mask to transfer the pattern of the second patterned mask layer downward, and forming a first sacrificial pattern and a second sacrificial pattern in the array region and the peripheral region; as well as The first array pattern and the first sacrificial pattern are pattern-transferred to form a second array pattern in the array region, and the first peripheral pattern and the second sacrificial pattern are pattern-transferred to form a second peripheral pattern in the peripheral region.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: A first dielectric layer is disposed between the substrate and the first pattern transfer layer, and the second array pattern and the second peripheral pattern are formed on the first dielectric layer.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: A second dielectric layer is disposed between the second pattern transfer layer and the first pattern transfer layer, wherein the first array pattern, the first peripheral pattern, the first sacrificial pattern and the second sacrificial pattern are formed on the second dielectric layer.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: After forming the first array pattern and the first peripheral pattern, the method further includes: Depositing a carbon-containing layer on the first array pattern and the first peripheral pattern to completely cover the first array pattern and the first peripheral pattern; and forming an anti-reflection layer on the carbon-containing layer, wherein the second patterned mask layer is formed on the anti-reflection layer, When the second patterned mask layer is used as a mask, the pattern of the second patterned mask layer is transferred to the anti-reflection layer and the carbon-containing layer to form the first sacrificial pattern and the second sacrificial pattern.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: Also includes: forming a second material stack on the second array pattern and the second peripheral pattern; forming a third patterned mask layer on the second material stack in the array region and the peripheral region; and A self-aligned double patterning process is performed according to the pattern of the third patterned mask layer to form a patterned material stacking layer, wherein the patterned material stacking layer includes a third array pattern formed in the array region.

6. The method for manufacturing a semiconductor structure according to claim 5, wherein: The step of forming the second material stack further includes: Depositing a carbon-containing layer on the second array pattern and the second peripheral pattern; depositing a nitride layer on the carbon-containing layer; depositing a silicon monoxide layer on the nitride layer; and forming a third pattern transfer layer on the silicon oxide layer, Wherein, the third patterned mask layer is formed on the third pattern transfer layer.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: The self-aligned double patterning process includes: Transferring the pattern of the third patterned mask layer to the third pattern transfer layer to form a core pattern layer, wherein the core pattern layer includes a first core pattern and a second core pattern formed in the array region and the peripheral region; Depositing a spacer material layer above the silicon oxide layer and the core pattern layer, wherein the spacer material layer conformably covers the core pattern layer; forming a planarization layer to completely cover the spacer material layer; Removing part of the planarization layer and part of the spacer material layer until the top surface of the core pattern layer is exposed, and the remaining planarization layer is filled between the remaining spacer material layers; removing the remaining portion of the spacer material layer to expose the silicon oxide layer; Using the remaining portion of the planarization layer and the core pattern layer as masks, removing the spacer material layer and the silicon oxide layer not covered by the remaining portion of the planarization layer and the core pattern layer until the nitride layer is exposed; and The carbon-containing layer and the remaining planarization layer are removed to form the patterned material stack layer.

8. The method for manufacturing a semiconductor structure according to claim 5, wherein: The pattern extension direction of the third patterned mask layer forms an angle smaller than 90 degrees with the first direction, or the pattern of the third patterned mask layer extends along the first direction.

9. The method for manufacturing a semiconductor structure according to claim 5, wherein: Also includes: forming a fourth patterned mask layer to cover the peripheral region and expose the third array pattern of the array region; and The fourth patterned mask layer and the third array pattern are used as masks to remove the exposed portion of a material layer below and the corresponding portion of the second array pattern, so as to convert the second array pattern into a final array pattern.

10. The method for manufacturing a semiconductor structure according to claim 9, wherein: A target material layer is provided between the substrate and the first material stack layer, covering the array region and the peripheral region.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein: Also includes: The final array pattern of the array region and the second peripheral pattern of the peripheral region are simultaneously transferred to the target material layer to form a target array pattern and a target peripheral pattern in the array region and the peripheral region, respectively.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein: The target array pattern is a capacitor contact pad in the array region of a dynamic random access memory device.

13. The method for manufacturing a semiconductor structure according to claim 11, wherein: The substrate and the first material stack further include: A carbon-containing layer is formed on the target material layer, and the carbon-containing layer covers the array region and the peripheral region. The third array pattern is located above the carbon-containing layer, and the second array pattern and the second peripheral pattern are located in the carbon-containing layer.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein: Also includes: a first dielectric layer is formed on the target material layer, wherein the first dielectric layer is located on the carbon-containing layer, Wherein, after the step of converting the second array pattern into the target array pattern, the final array pattern of the array region and the second peripheral pattern of the peripheral region are formed on the first dielectric layer.

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