A silicon carbide chip packaging structure

Abstract

The present invention relates to the technical field of high-voltage silicon carbide chip packaging, and specifically to a silicon carbide chip packaging structure, comprising: a chip body, comprising a first sub-chip and a second sub-chip arranged in layers, a chip insulation layer being arranged between the first sub-chip and the second sub-chip, the first sub-chip and the second sub-chip being connected in series, and a chip conductive member being arranged through the chip insulation layer; a printed circuit layer being arranged in parallel on one side of the chip body, and an emitter lead terminal being connected between the first sub-chip and the printed circuit layer; a composite insulation layer being arranged in parallel on the side of the chip body away from the printed circuit layer, and a composite conductive layer being arranged on the side of the composite insulation layer facing the chip body, and the second sub-chip being electrically connected to the composite conductive layer. In view of the high insulation and low inductance packaging requirements of silicon carbide chips, a chip insulation board is used to realize the series connection of medium and low voltage silicon carbide chips, and the chip devices after series connection can increase the overall voltage level of the devices, thereby realizing high voltage packaging using existing low voltage chips.

Description

Technical Field

[0001] The present invention relates to the technical field of high-voltage silicon carbide chip packaging, and in particular to a silicon carbide chip packaging structure. Background Art

[0002] In order to meet the large-scale development and utilization of renewable energy, the traditional power grid is developing towards the direction of smart grid represented by the widespread application of power electronics technology. Power electronic devices play an important role in various fields such as smart grid construction, high-voltage transmission of flexible AC transmission system, and access to new energy. This undoubtedly puts forward higher requirements for high-voltage, large-capacity, high-frequency, and high-temperature resistant power electronic devices. At present, most of the high-power power electronic devices in the power system use silicon power electronic devices, such as insulated gate bipolar transistors, thyristors, turn-off thyristors, etc., to achieve the control and conversion of electric energy. Since silicon power electronic devices are subject to the limitations of the material itself in terms of physical properties such as withstand voltage and operating temperature, in order to fundamentally improve the reliability and stability of high-power power electronic equipment, reduce the overall loss of the system, and improve the control and conversion efficiency of energy, it is necessary to research and develop new power electronic devices with higher withstand voltage, lower power consumption, and high temperature resistance.

[0003] Silicon carbide devices can break the physical limits of traditional silicon-based devices. They have the advantages of high voltage level, large current capacity, low loss, and fast heat dissipation. They can be widely used in new power electronic equipment such as solid-state transformers and solid-state circuit breakers, as well as traditional flexible AC transmission systems and DC transmission equipment.

[0004] The packaging structure of silicon carbide chips in the prior art still uses the welding packaging type of silicon-based chips, and its packaging parameters cannot match the high insulation, high shutdown speed, and low loss characteristics of silicon carbide chips, resulting in limited performance of silicon carbide chips. Summary of the invention

[0005] Therefore, the technical problem to be solved by the present invention is to overcome the defect of the packaging structure of the silicon carbide chip in the prior art that its performance is limited, thereby providing a silicon carbide chip packaging structure.

[0006] In order to solve the above technical problems, the present invention provides a silicon carbide chip packaging structure, comprising:

[0007] The chip body comprises a first sub-chip and a second sub-chip which are stacked, a chip insulating layer is arranged between the first sub-chip and the second sub-chip, the first sub-chip and the second sub-chip are connected in series via a chip conductive member, and the chip conductive member is arranged through the chip insulating layer;

[0008] The printed circuit layer is arranged parallel to one side of the chip body, an emitter lead-out terminal is connected between the first sub-chip and the printed circuit layer, and an emitter terminal is connected to the printed circuit layer;

[0009] The composite insulating layer is arranged parallel to the side of the chip body away from the printed circuit layer. The composite insulating layer is provided with a composite conductive layer on the side facing the chip body. A connecting conductive part is connected between the second sub-chip and the composite conductive layer. The composite conductive layer is connected to a collector terminal.

[0010] Optionally, at least two first equalizing rings are provided on the side of the chip insulation layer facing the first sub-chip, and all the first equalizing rings are sequentially arranged from the inside to the outside, and there is a spacing between any two adjacent first equalizing rings. A first conductive plate is arranged in the innermost first equalizing ring, and equalizing capacitors are connected between multiple first equalizing rings and between the innermost first equalizing ring and the first conductive plate. A first mounting hole is provided on the first conductive plate, and the first sub-chip is arranged in the first mounting hole, and the first sub-chip is electrically connected to the first conductive plate. By arranging the first equalizing rings around the chip, connecting the first conductive plate and multiple first equalizing capacitors using equalizing capacitors, dispersing the voltage to multiple first equalizing rings, forcibly introducing an intermediate potential, reducing the voltage borne by the chip insulation layer, and reducing the difficulty of packaging.

[0011] Optionally, at least one second equalizing ring is provided on the surface of the chip insulation layer facing the second sub-chip, the second equalizing ring is staggered with the first equalizing ring in a direction perpendicular to the chip body, a second conductive plate is provided in the innermost second equalizing ring, and the chip conductive part is arranged through the second conductive plate.

[0012] Optionally, the composite insulating layer comprises

[0013] A first insulating layer, wherein a first composite conductive layer is provided on one side facing the printed circuit layer, and a second composite conductive layer is provided on the other side thereof, wherein the first composite conductive layer comprises a third voltage-equalizing ring and a third conductive plate arranged in the third voltage-equalizing ring, wherein the third voltage-equalizing ring is arranged in alignment with the second voltage-equalizing ring, a second mounting hole is provided on the third conductive plate, and the second sub-chip is arranged in the second mounting hole, and a first grid lead-out terminal is connected between the first composite conductive layer and the printed circuit layer;

[0014] The second insulating layer has a third composite conductive layer on one side facing the first insulating layer, and the third composite conductive layer is electrically connected to the first grading ring.

[0015] The third composite conductive layer is electrically connected to the first grading ring. During the test, the third composite conductive layer is grounded to achieve zero potential of the first grading ring and the first conductive plate.

[0016] Optionally, the printed circuit layer includes:

[0017] A first circuit body is provided with a gate connection site, and a second gate lead-out terminal is connected between the gate connection site and the first sub-chip;

[0018] A second circuit body is provided with an emitter connection site, and an emitter lead-out terminal is provided between the emitter connection site and the first sub-chip;

[0019] A third circuit body is provided with a gate lead-out plate, the second gate lead-out terminal is electrically connected in series with the gate lead-out plate, and the gate terminal is connected to the gate lead-out plate;

[0020] The fourth circuit body is provided with an emitter lead-out plate, the emitter connection point is electrically connected in series with the emitter lead-out plate, the emitter terminal is connected to the emitter lead-out plate, and the gate terminal is arranged through the fourth circuit body.

[0021] By arranging the circuits on the printed circuit layer in layers, the probability of short circuits between the circuits is reduced, and different drive circuits of the chip are arranged in layers, which can improve the reliability of the device and the consistency of the drive circuits of each chip.

[0022] Optionally, the first circuit body, the second circuit body, the third circuit body and the fourth circuit body are stacked in sequence.

[0023] Optionally, the emitter lead terminal is threadedly connected to the emitter connection site.

[0024] Optionally, the emitter terminal includes a power emitter terminal and an auxiliary emitter terminal.

[0025] Optionally, it also includes an insulating shell, which is buckled and connected to the composite insulating layer, and the chip body and the printed circuit layer are both arranged in the cavity of the insulating shell.

[0026] Optionally, the collector terminal and the emitter terminal both penetrate the insulating housing and extend outside the insulating housing.

[0027] The technical solution of the present invention has the following advantages:

[0028] 1. The silicon carbide chip packaging structure provided by the present invention comprises: a chip body, comprising a first sub-chip and a second sub-chip arranged in a stacked manner, a chip insulating layer is arranged between the first sub-chip and the second sub-chip, the first sub-chip and the second sub-chip are connected in series through a chip conductive member, and the chip conductive member is arranged through the chip insulating layer; a printed circuit layer is arranged in parallel to one side of the chip body, an emitter lead terminal is connected between the first sub-chip and the printed circuit layer, and an emitter terminal is connected on the printed circuit layer; a composite insulating layer is arranged in parallel to the side of the chip body away from the printed circuit layer, a composite conductive layer is arranged on a side of the composite insulating layer facing the chip body, a connecting conductive member is connected between the second sub-chip and the composite conductive layer, and a collector terminal is connected on the composite conductive layer.

[0029] In response to the high insulation and low inductance packaging requirements of silicon carbide chips, chip insulation boards are used to connect medium and low voltage silicon carbide chips in series. The chip devices connected in series can improve the overall voltage level of the device. The silicon carbide chip is divided into two layers, the first sub-chip and the second sub-chip. The chips at corresponding positions in the upper and lower layers are electrically connected through chip conductive parts, so that the upper and lower chips are connected in series. The overall total voltage of the chip body is the sum of the voltage of the first sub-chip and the second sub-chip in series, thereby realizing high-voltage packaging using existing low-voltage chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 It is a schematic structural diagram of a silicon carbide chip packaging structure provided in an embodiment of the present invention.

[0032] Figure 2 It is a schematic structural diagram of a chip body provided in an embodiment of the present invention.

[0033] Figure 3 It is a schematic structural diagram of the chip body and the composite insulating layer provided in an embodiment of the present invention.

[0034] Figure 4 It is a schematic diagram of the front structure of the chip body provided in an embodiment of the present invention.

[0035] Figure 5 It is a schematic diagram of the back structure of the chip body provided in an embodiment of the present invention.

[0036] Figure 6 It is a schematic structural diagram of the first composite conductive layer provided in an embodiment of the present invention.

[0037] Figure 7 It is a schematic structural diagram of the second composite conductive layer provided in an embodiment of the present invention.

[0038] Figure 8 It is a schematic structural diagram of the third composite conductive layer provided in an embodiment of the present invention.

[0039] Fig. 9 It is a schematic structural diagram of a first circuit body provided in an embodiment of the present invention.

[0040] Fig.10It is a schematic structural diagram of a second circuit body provided in an embodiment of the present invention.

[0041] Fig.11 It is a schematic structural diagram of a third circuit body provided in an embodiment of the present invention.

[0042] Fig.12 It is a schematic structural diagram of a fourth circuit body provided in an embodiment of the present invention.

[0043] Explanation of the accompanying drawings: 1. first sub-chip; 2. second sub-chip; 3. chip insulating layer; 4. chip conductive part; 5. first equalizing ring; 6. first conductive plate; 7. equalizing capacitor; 8. first mounting hole; 9. second equalizing ring; 10. second conductive plate; 11. second mounting hole; 12. emitter lead terminal; 13. power emitter terminal; 14. first insulating layer; 15. second insulating layer; 16. third equalizing ring; 17. first gate lead terminal; 18. second composite conductive layer; 19. third composite conductive layer; 20. gate connection site; 21. second gate lead terminal; 22. emitter connection site; 23. gate lead plate; 24. gate terminal; 25. emitter lead plate; 26. auxiliary emitter terminal; 27. collector terminal; 28. insulating shell. DETAILED DESCRIPTION

[0044] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0046] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0047] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0048] Example

[0049] like Figures 1 to 12 The figure shows a silicon carbide chip packaging structure provided by this embodiment, including: a stacked chip body, a printed circuit layer, a composite insulating layer and an insulating shell connected to the composite insulating layer, the chip body and the printed circuit layer are both arranged in the cavity of the insulating shell 28. The insulating shell and the composite insulating layer are bonded by silicone gel and epoxy glue.

[0050] The chip body includes a first sub-chip 1 and a second sub-chip 2 which are stacked, and a chip insulating layer 3 is provided between the first sub-chip 1 and the second sub-chip 2. In this embodiment, four first sub-chips 1 are provided, and four second sub-chips 2 are provided. The first sub-chip 1 and the second sub-chip 2 are connected in series through a connecting metal column as a chip conductive member 4, and the first sub-chip 1 and the second sub-chip 2 are electrically connected to the chip conductive member 4 through a sintering process. The chip conductive member 4 is provided through the chip insulating layer 3 and extends to connect with the composite insulating layer.

[0051] Two first equalizing rings 5 ​​are provided on the surface of the chip insulation layer 3 facing the first sub-chip 1. The two first equalizing rings are arranged in sequence from the inside to the outside, and the two first equalizing rings are arranged at intervals. A first conductive plate 6 is arranged in the innermost first equalizing ring 5. An equalizing capacitor 7 is connected between the two first equalizing rings 5 ​​and between the inner first equalizing ring 5 and the first conductive plate 6. A first mounting hole 8 is provided on the first conductive plate 6. The first sub-chip 1 is arranged in the first mounting hole 8, and the first sub-chip 1 is electrically connected to the first conductive plate 6.

[0052] A second equalizing ring 9 is provided on the side of the chip insulation layer 3 facing the second sub-chip 2. The second equalizing ring 9 and the first equalizing ring 5 are staggered in a direction perpendicular to the chip body. A second conductive plate 10 is provided in the second equalizing ring 9, and the chip conductive member is arranged through the second conductive plate. In this embodiment, four chip conductive member tube perforations are provided on the second conductive plate 10. The projection of the emitter lead terminal on the second conductive plate 10 is located at the four corners of the second conductive plate 10. The second sub-chip 2 is electrically connected to the emitter lead terminal one by one. The projections of the interconnected second sub-chip 2 and the emitter lead terminal on the second conductive plate are respectively located at the two corners on the diagonal line of the second conductive plate 10, so that the four conductive line paths run crosswise.

[0053] The printed circuit layer is arranged parallel to one side of the chip body, an emitter lead-out terminal 12 is connected between the first sub-chip 1 and the printed circuit layer, and an emitter terminal is connected to the printed circuit layer. The emitter terminal penetrates the insulating housing and extends outside the insulating housing.

[0054] The composite insulating layer is arranged parallel to the side of the chip body away from the printed circuit layer, and the composite insulating layer is provided with a composite conductive layer on the side facing the chip body. A connecting conductive member is connected between the second sub-chip 2 and the composite conductive layer to connect the second sub-chip 2 with the composite conductive layer, and a collector terminal 27 is connected to the composite conductive layer. The collector terminal 27 penetrates the insulating shell and extends outside the insulating shell. The composite insulating layer includes a first insulating layer 14 and a second insulating layer 15. The first insulating layer 14 is provided with a first composite conductive layer on the side facing the printed circuit layer, and the second insulating layer 15 is provided with a second composite conductive layer 18 on the other side. A third grading ring 16 and a third conductive plate arranged in the third grading ring are provided on the first composite conductive layer. The third grading ring 16 is arranged in alignment with the second grading ring 9. A second mounting hole 11 is provided on the third conductive plate. The second sub-chip is arranged in the second mounting hole 11 and is connected to the first insulating layer 14 through a sintering process. A conductive wire as a connecting conductive member is provided between the second sub-chip and the third grading ring 16 on the third conductive plate. A first gate lead terminal 17 is connected between the first composite conductive layer and the printed circuit layer. A third composite conductive layer 19 is provided on the side of the second insulating layer 15 facing the first insulating layer 14. The third composite conductive layer 19 is electrically connected to the first grading ring 5 through a metal column. The third composite conductive layer 19 is provided with a connection hole for connecting to the metal column and a zero potential connection point for grounding. The first grading ring 5, the grading capacitor 7, the first conductive plate 6, the second grading ring 9, the second conductive plate 10, the first composite conductive layer, and the second composite conductive layer 18 are all copper-plated silver coatings. The chip insulating layer 3, the first insulating layer 14, and the second insulating layer 15 are all high-insulation, high-thermal-conductivity aluminum nitride insulating plates. The first sub-chip 1 and the second sub-chip 2 are interconnected with the chip insulating plate through a sintering process.

[0055] The printed circuit layer includes a first circuit body, a second circuit body, a third circuit body and a fourth circuit body which are stacked in sequence. A gate connection site 20 is provided on the first circuit body, and a second gate lead terminal 21 is connected between the gate connection site 20 and the first sub-chip 1; an emitter connection site 22 is provided on the second circuit body, and the emitter lead terminal 12 is provided between the emitter connection site 22 and the first sub-chip 1; a gate lead plate 23 is provided on the third circuit body, and the second gate lead terminal 21 is electrically connected in series with the gate lead plate 23, and a gate terminal 24 is connected to the gate lead plate 23; an emitter lead plate 25 is provided on the fourth circuit body, and the emitter connection site 22 is electrically connected in series with the emitter lead plate 25, and an emitter terminal is connected to the emitter lead plate 25, and the gate terminal 24 is arranged through the fourth circuit body. In this embodiment, the emitter terminal includes a power emitter terminal 13 and an auxiliary emitter terminal 26. During testing, a power circuit is formed between the power emitter terminal 13 and the collector terminal 27, and a drive circuit is formed between the auxiliary emitter terminal 26 and the gate terminal 24. The drive circuit and the power circuit are dispersedly arranged and operated separately, which can eliminate the influence of the drive circuit signal on the power circuit signal during testing.

[0056] As an alternative implementation, the emitter lead-out terminal 12 is a copper column, a connecting through hole is provided on the emitter connection site 22, and the emitter lead-out terminal 12 is threadedly connected to the emitter connection site 22.

[0057] As an alternative implementation, the first circuit body, the second circuit body, the third circuit body and the fourth circuit body are disposed on the same circuit board by etching.

[0058] As an alternative implementation, the third grading ring is not provided on the first composite conductive layer, and the second grading ring is directly connected to the second sub-chip through a conductive wire.

[0059] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A silicon carbide chip packaging structure, characterized in that: include: A chip body comprises a first sub-chip (1) and a second sub-chip (2) which are stacked, a chip insulating layer (3) being provided between the first sub-chip (1) and the second sub-chip (2), the first sub-chip (1) and the second sub-chip (2) being connected in series via a chip conductive member (4), and the chip conductive member (4) being provided through the chip insulating layer (3); A printed circuit layer is arranged parallel to one side of the chip body, an emitter lead terminal (12) is connected between the first sub-chip (1) and the printed circuit layer, and an emitter terminal is connected to the printed circuit layer; a composite insulating layer, arranged in parallel on a side of the chip body away from the printed circuit layer, a composite conductive layer being arranged on a side of the composite insulating layer facing the chip body, a connecting conductive member being connected between the second sub-chip (2) and the composite conductive layer, and a collector terminal (27) being connected to the composite conductive layer; The chip insulation layer (3) is provided with at least two first equalizing rings (5) arranged in a sleeve on one surface of the first sub-chip (1); a first conductive plate (6) is arranged inside the innermost first equalizing ring (5); equalizing capacitors (7) are connected between the plurality of first equalizing rings (5) and between the innermost first equalizing ring (5) and the first conductive plate (6); a first mounting hole (8) is provided on the first conductive plate (6); the first sub-chip (1) is arranged in the first mounting hole (8), and the first sub-chip (1) is electrically connected to the first conductive plate (6).

2. The silicon carbide chip packaging structure according to claim 1, characterized in that: The chip insulating layer (3) is provided with at least one second voltage-equalizing ring (9) sleeved on one surface of the second sub-chip (2); the second voltage-equalizing ring (9) is aligned with the gap between the adjacent first voltage-equalizing ring (5); a second conductive plate (10) is provided inside the innermost second voltage-equalizing ring (9); and the chip conductive part is provided through the second conductive plate (10).

3. The silicon carbide chip packaging structure according to claim 2, characterized in that: The composite insulating layer comprises A first insulating layer (14), wherein a first composite conductive layer is provided on one side facing the printed circuit layer, and a second composite conductive layer (18) is provided on the other side, wherein the first composite conductive layer comprises a third voltage-equalizing ring (16) and a third conductive plate arranged in the third voltage-equalizing ring, wherein the third voltage-equalizing ring (16) and the second voltage-equalizing ring (9) are arranged in one-to-one alignment, a second mounting hole (11) is provided on the third conductive plate, the second sub-chip (2) is arranged in the second mounting hole (11), and a first gate lead terminal (17) is connected between the first composite conductive layer and the printed circuit layer; The second insulating layer (15) has a third composite conductive layer (19) on one side thereof facing the first insulating layer (14), and the third composite conductive layer (19) is electrically connected to the first grading ring (5).

4. The silicon carbide chip packaging structure according to any one of claims 1 to 3, characterized in that: The printed circuit layer includes: A first circuit body, which is provided with a gate connection site (20), and a second gate lead-out terminal (21) is connected between the gate connection site (20) and the first sub-chip (1); A second circuit body, which is provided with an emitter connection site (22), wherein the emitter lead-out terminal (12) is provided between the emitter connection site (22) and the first sub-chip (1); A third circuit body, which is provided with a gate lead-out plate (23), the second gate lead-out terminal (21) is electrically connected in series with the gate lead-out plate (23), and the gate lead-out plate (23) is connected to a gate terminal (24); The fourth circuit body is provided with an emitter lead-out plate (25), the emitter connection point (22) is electrically connected in series with the emitter lead-out plate (25), the emitter terminal is connected to the emitter lead-out plate (25), and the gate terminal (24) is arranged through the fourth circuit body.

5. The silicon carbide chip packaging structure according to claim 4, characterized in that: The first circuit body, the second circuit body, the third circuit body and the fourth circuit body are stacked in sequence.

6. The silicon carbide chip packaging structure according to claim 4, characterized in that: The emitter lead-out terminal (12) is threadedly connected to the emitter connection point (22).

7. The silicon carbide chip packaging structure according to claim 4, characterized in that: The emitter terminal includes a power emitter terminal (13) and an auxiliary emitter terminal (26).

8. The silicon carbide chip packaging structure according to any one of claims 1 to 3, characterized in that: It also includes an insulating shell, which is buckled and connected with the composite insulating layer. The chip body and the printed circuit layer are both arranged in the cavity of the insulating shell.

9. The silicon carbide chip packaging structure according to claim 8, characterized in that: The collector terminal and the emitter terminal both penetrate the insulating housing and extend outside the insulating housing.

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