A charge pump for a phase-locked loop

Abstract

This invention discloses a charge pump for a phase-locked loop (PLL), relating to next-generation information technology. This solution addresses the high power consumption of existing charge pumps. This technology is achieved by ensuring that the control signal of the transmission gate in the balancing circuit precedes the control signal of the transmission gate in the charging and discharging branch. This further improves current mismatch by controlling the charging branch and the charging portion of the balancing circuit via the positive-phase output of a differential output operational amplifier, and controlling the discharging branch and the discharging portion of the balancing circuit via the negative-phase output of the differential output operational amplifier. This advantageously allows the entire circuit to remain in an off state for most of the signal cycle, saving power. The output current matching performance of the charge pump is also improved.

Description

Technical Field

[0001] The present invention relates to new generation information technology, and in particular to a charge pump for a phase-locked loop. Background Art

[0002] Common PLL charge pump architectures such as Figure 1 As shown, a bias circuit provides bias voltage to the charge and discharge branches. The switches in these branches utilize transmission gates, which offset clock collapse effects introduced by the switching transistors. The first PMOS transistor P1 and the first transmission gate G1 form the charge branch, while the first NMOS transistor N1 and the third transmission gate G3 form the discharge branch. An op amp connected between the four transmission gates, along with the second and fourth transmission gates G2 and G4, forms a balancing circuit to balance the charge and discharge voltages.

[0003] In the charge-discharge voltage balancing circuit, when the first and third transmission gates G1 and G3 are closed, the second and fourth transmission gates G2 and G4 are open. Conversely, when the second and fourth transmission gates G2 and G4 are closed, the first and third transmission gates G1 and G3 are open. Because the corresponding transmission gate control signals in the balancing circuit and the charge-discharge circuit are in opposite phases, the entire path formed by the first PMOS transistor P1 and the first NMOS transistor N1 remains in the on state throughout the entire cycle, consuming a large amount of power. Furthermore, due to the transistor channel length modulation effect, the charge-discharge branch cannot accurately replicate the current of the bias circuit, resulting in a mismatch between the charging and discharging circuits.

[0004] The technical solutions close to the present invention are provided as follows:

[0005] A high-performance charge pump for phase-locked loops, CN110830036A;

[0006] A single operational amplifier charge pump circuit CN113708621A for a phase-locked loop;

[0007] Charge pump circuit for phase-locked loop, CN114978158A. Summary of the Invention

[0008] The present invention aims to provide a charge pump for a phase-locked loop to solve the problem of high power consumption.

[0009] In the charge pump for a phase-locked loop described in the present invention, the control signal of the transmission gate in the balancing circuit is ahead of the control signal of the transmission gate in the charging and discharging branch.

[0010] Optionally, the control signal of the transmission gate in the balancing circuit and the control signal of the transmission gate in the charge and discharge branch are both pulse signals.

[0011] Furthermore, in order to solve the mismatch problem, the charging branch and the charging part of the balancing circuit are controlled by the positive output terminal of the differential output operational amplifier; the discharging branch and the discharging part of the balancing circuit are controlled by the negative output terminal of the differential output operational amplifier.

[0012] Specifically, the charge pump for a phase-locked loop includes a bias circuit, a matching circuit, a charging branch, a discharging branch, and a balancing circuit;

[0013] The bias circuit is used to output a charging bias voltage and a discharging bias voltage respectively;

[0014] The matching circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a first operational amplifier, a fifth NMOS transistor, and a fourth NMOS transistor; the source of the fourth PMOS transistor is connected to VDD, the gate of the fourth PMOS transistor is connected to a charging bias voltage, and the drain of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor; the gate of the fifth PMOS transistor is connected to the non-inverting output terminal of the first operational amplifier, the drain of the fifth PMOS transistor is connected to the non-inverting input terminal of the first operational amplifier and the drain of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the inverting output terminal of the first operational amplifier, the source of the fifth NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to a discharging bias voltage, and the source of the fourth NMOS transistor is grounded;

[0015] The charging branch includes a first PMOS transistor, a first transmission gate, and a second PMOS transistor; the source of the first PMOS transistor is connected to VDD, the gate of the first PMOS transistor is connected to a charging bias voltage, the drain of the first PMOS transistor is connected in series with the first transmission gate and then connected to the source of the second PMOS transistor, the gate of the second PMOS transistor is connected to the non-inverting output terminal of the first operational amplifier, the drain of the second PMOS transistor is connected to the inverting input terminal of the first operational amplifier, and the drain of the second PMOS transistor is also connected to the output terminal of the charge pump;

[0016] The discharge branch includes a first NMOS transistor, a third transmission gate, and a second NMOS transistor; the drain of the second NMOS transistor is connected to the inverting input terminal of the first operational amplifier, the gate of the second NMOS transistor is connected to the inverting output terminal of the first operational amplifier, the drain of the second NMOS transistor is connected in series with the third transmission gate and then connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor is connected to the discharge bias voltage, and the source of the first NMOS transistor is grounded;

[0017] The balancing circuit includes a second transmission gate, a third PMOS transistor, a second operational amplifier, a third NMOS transistor, and a fourth transmission gate; the source of the third PMOS transistor is connected in series with the second transmission gate and then connected to the drain of the first PMOS transistor; the gate of the third PMOS transistor is connected to the non-inverting output of the first operational amplifier; the drain of the third PMOS transistor is connected to the output of the second operational amplifier; the non-inverting input of the second operational amplifier is connected to the drain of the second PMOS transistor; the inverting input of the second operational amplifier and the output of the second operational amplifier are connected at a common point to the drain of the third NMOS transistor; the gate of the third NMOS transistor is connected to the inverting output of the first operational amplifier; the source of the third NMOS transistor is connected in series with the fourth transmission gate and then connected to the drain of the first NMOS transistor;

[0018] The first transmission gate is controlled by a charging control signal and its inverted signal to control the switching state, the second transmission gate is controlled by a leading signal of the charging control signal and its inverted signal to control the switching state, the third transmission gate is controlled by a discharging control signal and its inverted signal to control the switching state, and the fourth transmission gate is controlled by a leading signal of the discharging control signal and its inverted signal to control the switching state.

[0019] The charge pump for a phase-locked loop described in the present invention has the advantage that the entire circuit is in a closed state during most of the signal cycle, saving power consumption and improving the output current matching performance of the charge pump. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a structural diagram of a charge pump in the prior art.

[0021] Figure 2 It is a structural diagram of the charge pump described in the present invention.

[0022] Figure 3 Schematic diagram of the signal timing of the charge pump in the present invention.

[0023] Figure 4 It is a structural diagram of the advance circuit in the present invention.

[0024] Reference numerals:

[0025] G1 to G4 - first transmission gate to fourth transmission gate;

[0026] P1 to P5 - first to fifth PMOS transistors;

[0027] N1 to N5 - first NMOS transistor to fifth NMOS transistor;

[0028] OPA1-first operational amplifier, OPA2-second operational amplifier;

[0029] UP-charging control signal, UPF-leading signal of charging control signal,

[0030] DN-discharge control signal, DNF-discharge control signal leading signal,

[0031] V1 is the charging bias voltage output by the bias circuit, and V2 is the discharging bias voltage output by the bias circuit. DETAILED DESCRIPTION

[0032] like Figure 2 As shown, the charge pump for a phase-locked loop described in the present invention includes a bias circuit, a matching circuit, a charging branch, a discharging branch, and a balancing circuit.

[0033] The bias circuit is used to output a charging bias voltage and a discharging bias voltage respectively.

[0034] The matching circuit includes a fourth PMOS transistor P4, a fifth PMOS transistor P5, a first operational amplifier OPA1, a fifth NMOS transistor N5, and a fourth NMOS transistor N4. The source of the fourth PMOS transistor P4 is connected to VDD, the gate of the fourth PMOS transistor P4 is connected to a charging bias voltage, and the drain of the fourth PMOS transistor P4 is connected to the source of the fifth PMOS transistor P5. The gate of the fifth PMOS transistor P5 is connected to the non-inverting output terminal of the first operational amplifier OPA1, the drain of the fifth PMOS transistor P5 is connected to the non-inverting input terminal of the first operational amplifier OPA1 and the drain of the fifth NMOS transistor N5, the gate of the fifth NMOS transistor N5 is connected to the inverting output terminal of the first operational amplifier OPA1, the source of the fifth NMOS transistor N5 is connected to the drain of the fourth NMOS transistor N4, the gate of the fourth NMOS transistor N4 is connected to a discharging bias voltage, and the source of the fourth NMOS transistor N4 is grounded.

[0035] The charging branch includes a first PMOS transistor P1, a first transmission gate G1, and a second PMOS transistor P2. The source of the first PMOS transistor P1 is connected to VDD, the gate of the first PMOS transistor P1 is connected to a charging bias voltage, the drain of the first PMOS transistor P1 is connected in series with the first transmission gate G1, and then to the source of the second PMOS transistor P2. The gate of the second PMOS transistor P2 is connected to the non-inverting output terminal of the first operational amplifier OPA1, and the drain of the second PMOS transistor P2 is connected to the inverting input terminal of the first operational amplifier OPA1. The drain of the second PMOS transistor P2 also serves as the output terminal of the charge pump.

[0036] The discharge branch includes a first NMOS transistor N1, a third transmission gate G3, and a second NMOS transistor N2. The drain of the second NMOS transistor N2 is connected to the inverting input terminal of the first operational amplifier OPA1, the gate of the second NMOS transistor N2 is connected to the inverting output terminal of the first operational amplifier OPA1, the drain of the second NMOS transistor N2 is connected in series with the third transmission gate G3, and then connected to the drain of the first NMOS transistor N1. The gate of the first NMOS transistor N1 is connected to a discharge bias voltage, and the source of the first NMOS transistor N1 is grounded.

[0037] The balancing circuit includes a second transmission gate G2, a third PMOS transistor P3, a second operational amplifier OPA2, a third NMOS transistor N3, and a fourth transmission gate G4. The source of the third PMOS transistor P3 is connected in series with the second transmission gate G2 and then connected to the drain of the first PMOS transistor P1. The gate of the third PMOS transistor P3 is connected to the non-inverting output of the first operational amplifier OPA1. The drain of the third PMOS transistor P3 is connected to the output of the second operational amplifier OPA2. The non-inverting input of the second operational amplifier OPA2 is connected to the drain of the second PMOS transistor P2. The inverting input of the second operational amplifier OPA2 and the output of the second operational amplifier OPA2 are connected to the drain of the third NMOS transistor N3 at a common point. The gate of the third NMOS transistor N3 is connected to the inverting output of the first operational amplifier OPA1. The source of the third NMOS transistor N3 is connected in series with the fourth transmission gate G4 and then connected to the drain of the first NMOS transistor N1. The second transmission gate G2 and the third PMOS transistor P3 form a charging portion, and the fourth transmission gate G4 and the third NMOS transistor N3 form a discharging portion.

[0038] The switching state of the first transmission gate G1 is controlled by the charging control signal and its inverted signal, the switching state of the second transmission gate G2 is controlled by the leading signal of the charging control signal and the inverted signal of the leading signal, the switching state of the third transmission gate G3 is controlled by the discharging control signal and its inverted signal, and the switching state of the fourth transmission gate G4 is controlled by the leading signal of the discharging control signal and the inverted signal of the leading signal.

[0039] The bias circuit is a conventional structure and is common knowledge. The advance signal can be generated by a conventional advance circuit. In this embodiment, a conventional advance circuit structure is provided, such as Figure 4 As shown in the figure, the signal input terminal in is connected to the output of the phase frequency detector at the front end of the charge pump. If the input terminal in receives the signal UP, the output terminal out will output the delayed signal UP, while the other output terminal outF will output the signal UPF. Similarly, the principle of generating the leading signal for other signals is the same.

[0040] In this embodiment, the charge pump in a stable state has the same timing sequence of the signal UP and the signal DN. The timing sequence states of other signals are as follows: Figure 3 shown.

[0041] The working principle of the charge pump for phase-locked loop described in the present invention is as follows: the charging branch is connected to the UP signal and Under the action of the charge pump output, the charge pump output is charged; the discharge branch is connected to the signal DN and Under the action of , the charge pump output is discharged. In the matching circuit, the first operational amplifier OPA1 uses the virtual short effect to clamp the voltage between the charge pump output and the bias circuit node, making the two potentials equal. This effectively eliminates the mismatch problem caused by the channel length modulation effect of the transistors in the charge and discharge branches, and achieves accurate replication of the bias current by the charge and discharge branch circuit. At the same time, the first operational amplifier OPA1 controls the charge and discharge branches, ensuring the precise output of the charge pump during both the charging and discharging phases of the charge pump. This improves the output current matching performance of the charge pump. This bias circuit node is the connection point between the drain of the fifth PMOS transistor P5 and the drain of the fifth NMOS transistor N5.

[0042] In the balancing circuit, the second operational amplifier OPA2 similarly utilizes the virtual short effect to clamp the voltage between the charge pump output and the auxiliary reference node. This auxiliary reference node is the connection point between the drain of the third PMOS transistor P3 and the drain of the third NMOS transistor N3, so that the potential of the bias circuit node and the auxiliary reference node remain consistent. The control signals of the transmission gates in the balancing circuit are all ahead of those of the charge and discharge branches. Therefore, they can be turned on before the transmission gates of the charge and discharge branches are turned on to eliminate the charge sharing effect. Ultimately, the first transmission gate G1, the second transmission gate G2, the third transmission gate G3, and the fourth transmission gate G4 are in the closed state for most of the signal cycle, ensuring that the first PMOS transistor P1 and the first NMOS transistor N1 are not always on, effectively saving power. Based on the existence of the advance signal, the signals UP and DN can both be set as pulse signals, greatly reducing the opening time of the transmission gates.

[0043] Those skilled in the art can make various other corresponding changes and deformations based on the technical solutions and concepts described above, and all of these changes and deformations should fall within the scope of protection of the claims of the present invention.

Claims

1. A charge pump for a phase-locked loop, characterized in that: The control signal of the transmission gate in the balancing circuit is ahead of the control signal of the transmission gate in the charging and discharging branch; The control signal of the transmission gate in the balancing circuit and the control signal of the transmission gate in the charging and discharging branch are both pulse signals; The charging branch and the charging part of the balancing circuit are controlled by the positive output terminal of the differential output operational amplifier; the discharging branch and the discharging part of the balancing circuit are controlled by the negative output terminal of the differential output operational amplifier; It includes a bias circuit, a matching circuit, a charging branch, a discharging branch and a balancing circuit; The bias circuit is used to output a charging bias voltage and a discharging bias voltage respectively; The matching circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a first operational amplifier, a fifth NMOS transistor and a fourth NMOS transistor; the source of the fourth PMOS transistor is connected to VDD, the gate of the fourth PMOS transistor is connected to the charging bias voltage, and the drain of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor; The gate of the fifth PMOS transistor is connected to the non-inverting output terminal of the first operational amplifier, the drain of the fifth PMOS transistor is connected to the non-inverting input terminal of the first operational amplifier and the drain of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the inverting output terminal of the first operational amplifier, the source of the fifth NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the discharge bias voltage, and the source of the fourth NMOS transistor is grounded; The charging branch includes a first PMOS transistor, a first transmission gate, and a second PMOS transistor; the source of the first PMOS transistor is connected to VDD, the gate of the first PMOS transistor is connected to a charging bias voltage, the drain of the first PMOS transistor is connected in series with the first transmission gate and then connected to the source of the second PMOS transistor, the gate of the second PMOS transistor is connected to the non-inverting output terminal of the first operational amplifier, the drain of the second PMOS transistor is connected to the inverting input terminal of the first operational amplifier, and the drain of the second PMOS transistor is also connected to the output terminal of the charge pump; The discharge branch includes a first NMOS transistor, a third transmission gate, and a second NMOS transistor; the drain of the second NMOS transistor is connected to the inverting input terminal of the first operational amplifier, the gate of the second NMOS transistor is connected to the inverting output terminal of the first operational amplifier, the drain of the second NMOS transistor is connected in series with the third transmission gate and then connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor is connected to the discharge bias voltage, and the source of the first NMOS transistor is grounded; The balancing circuit includes a second transmission gate, a third PMOS transistor, a second operational amplifier, a third NMOS transistor, and a fourth transmission gate; the source of the third PMOS transistor is connected in series with the second transmission gate and then connected to the drain of the first PMOS transistor; the gate of the third PMOS transistor is connected to the non-inverting output of the first operational amplifier; the drain of the third PMOS transistor is connected to the output of the second operational amplifier; the non-inverting input of the second operational amplifier is connected to the drain of the second PMOS transistor; the inverting input of the second operational amplifier and the output of the second operational amplifier are connected at a common point to the drain of the third NMOS transistor; the gate of the third NMOS transistor is connected to the inverting output of the first operational amplifier; the source of the third NMOS transistor is connected in series with the fourth transmission gate and then connected to the drain of the first NMOS transistor; The first transmission gate is controlled by a charging control signal and its inverted signal to control the switching state, the second transmission gate is controlled by a leading signal of the charging control signal and its inverted signal to control the switching state, the third transmission gate is controlled by a discharging control signal and its inverted signal to control the switching state, and the fourth transmission gate is controlled by a leading signal of the discharging control signal and its inverted signal to control the switching state.

Images