Method, apparatus, device and readable medium for preparing a superconducting quantum parametric amplifier

Abstract

The present invention provides a method, device, equipment and readable medium for preparing a superconducting quantum parametric amplifier. The method includes: fabricating a transmission line and a Josephson junction on a parametric amplifier chip, and exposing and etching a space with a preset size at a preset position on the transmission line; placing a patch capacitor in the space with the preset size, and fixing the patch capacitor in the space with the preset size using cryogenic glue; connecting both ends of the patch capacitor to both sides of the Josephson junction. By using the solution of the present invention, the fabrication yield of the parametric amplifier can be improved, and the use of commercial patch capacitors can make the parametric amplifier no longer rely on the insulating layer, so that the performance of the parametric amplifier remains stable.

Description

Technical Field

[0001] The present invention relates to the field of computers, and more particularly to a method, apparatus, device, and readable medium for preparing a superconducting quantum parametric amplifier. Background Art

[0002] A Josephson junction parametric amplifier can compress noise to the quantum level and is currently an essential key device in the measurement process of superconducting quantum chips. The flux-driven type of bandwidth parametric amplifier is the mainstream solution for the current mainstream Josephson junction parametric amplifier. Half-wavelength and quarter-wavelength transmission lines can convert the input impedance of the parametric amplifier, increasing its bandwidth to several hundred megahertz. For the flux-driven type of parametric amplifier, the frequency of the pump signal is generally close to twice the frequency of the input signal. Due to the large frequency difference, the noise generated by the pump signal for the bit read signal is small. The pump microwave signal of the Josephson junction and the current on the SQUID (superconducting quantum interference) are applied through the flux bias line, and the read signal of the quantum bit is input and output from the bonding point on the left side of the parametric amplifier.

[0003] Currently, the parametric amplifier has problems of low preparation yield and unstable performance. To adjust the operating frequency of the parametric amplifier, the current mainstream solution is to connect a parallel-plate capacitor in parallel with the Josephson junction. The dielectric constant of the insulating layer in the parallel-plate capacitor is much larger than that of vacuum, which can keep the size of the parametric amplifier chip small. The parallel-plate capacitor is one of the main difficulties in the processing of the parametric amplifier. Firstly, the growth and stripping processes of the insulating dielectric layer are relatively difficult, and it is easy to introduce impurities into the superconducting chip. Leakage and unstable dielectric constant are likely to occur in the insulating layer stripping or the parallel-plate capacitor, resulting in unstable performance of the parametric amplifier. Moreover, the dielectric constants of insulating layers such as silicon dioxide grown by many experimental groups are unstable and prone to leakage. Summary of the Invention

[0004] In view of this, an object of the embodiments of the present invention is to provide a method, apparatus, device, and readable medium for preparing a superconducting quantum parametric amplifier. By using the technical solution of the present invention, the preparation yield of the parametric amplifier can be improved, and the use of commercial patch capacitors can make the parametric amplifier no longer rely on the insulating layer, keeping the performance of the parametric amplifier stable.

[0005] Based on the above object, an aspect of the embodiments of the present invention provides a method for preparing a superconducting quantum parametric amplifier, including the following steps:

[0006] Fabricate a transmission line and a Josephson junction on a parametric amplifier chip, and expose and etch a space of a preset size at a preset position on the transmission line;

[0007] Place the chip capacitor in a space of a preset size and fix the chip capacitor in the space of the preset size using cryogenic glue;

[0008] Connect both ends of the chip capacitor to both sides of the Josephson junction.

[0009] According to an embodiment of the present invention, preparing a transmission line and a Josephson junction on a parametric amplifier chip, and exposing and etching a space of a preset size at a preset position on the transmission line includes:

[0010] Expose and etch a space of a preset size at a position on the transmission line close to the Josephson junction. The length of the space of the preset size is 1 mm, the width is 1 mm, and the depth is 100 nm.

[0011] According to an embodiment of the present invention, connecting both ends of the chip capacitor to both sides of the Josephson junction includes:

[0012] Connect both ends of the chip capacitor to both sides of the Josephson junction using a superconducting aluminum wire with a diameter of 25 microns on a spot welder.

[0013] According to an embodiment of the present invention, connecting both ends of the chip capacitor to both sides of the Josephson junction includes:

[0014] Connect both ends of the chip capacitor to both sides of the Josephson junction by plating a layer of superconducting aluminum wire on the parametric amplifier chip through photolithography technology.

[0015] Another aspect of the embodiment of the present invention also provides a device for preparing a superconducting quantum parametric amplifier. The device includes:

[0016] A preparation module configured to prepare a transmission line and a Josephson junction on a parametric amplifier chip, and expose and etch a space of a preset size at a preset position on the transmission line;

[0017] A fixing module configured to place the chip capacitor in the space of the preset size and fix the chip capacitor in the space of the preset size using cryogenic glue;

[0018] A connection module configured to connect both ends of the chip capacitor to both sides of the Josephson junction.

[0019] According to an embodiment of the present invention, the preparation module is further configured to:

[0020] Expose and etch a space of a preset size at a position on the transmission line close to the Josephson junction. The length of the space of the preset size is 1 mm, the width is 1 mm, and the depth is 100 nm.

[0021] According to an embodiment of the present invention, the connection module is further configured to:

[0022] Connect both ends of the chip capacitor to both sides of the Josephson junction using a 25-micron superconducting aluminum wire on the spot welder.

[0023] According to an embodiment of the present invention, the connection module is further configured to:

[0024] Deposit a layer of superconducting aluminum wire on the parametric amplifier chip through lithography technology to connect both ends of the chip capacitor to both sides of the Josephson junction.

[0025] Another aspect of the embodiments of the present invention further provides a computer device, which includes:

[0026] At least one processor; and

[0027] A memory storing computer instructions that can be run on the processor, and when the instructions are executed by the processor, the steps of any one of the above methods are implemented.

[0028] Another aspect of the embodiments of the present invention further provides a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the steps of any one of the above methods are implemented.

[0029] The present invention has the following beneficial technical effects: The method for preparing a superconducting quantum parametric amplifier provided by the embodiments of the present invention prepares a transmission line and a Josephson junction on a parametric amplifier chip, and exposes and etches a space of a preset size at a preset position on the transmission line; places the chip capacitor in the space of the preset size, and uses a cryogenic adhesive to fix the chip capacitor in the space of the preset size; connects both ends of the chip capacitor to both sides of the Josephson junction, which can improve the preparation yield of the parametric amplifier. Using a commercial chip capacitor can make the parametric amplifier no longer rely on an insulating layer and keep the performance of the parametric amplifier stable. Description of the Drawings

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other embodiments can be obtained based on these drawings without creative efforts.

[0031] Figure 1 It is a schematic flowchart of a method for preparing a superconducting quantum parametric amplifier according to an embodiment of the present invention;

[0032] Figure 2 It is a schematic diagram of a device for preparing a superconducting quantum parametric amplifier according to an embodiment of the present invention;

[0033] Figure 3 Schematic diagram of a computer device according to an embodiment of the present invention;

[0034] Figure 4 Schematic diagram of a computer-readable storage medium according to an embodiment of the present invention. Detailed implementation manners

[0035] To make the objectives, technical solutions and advantages of the present invention more clear and understandable, the following further elaborates on the embodiments of the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0036] Based on the above objectives, in the first aspect of the embodiments of the present invention, an embodiment of a method for preparing a superconducting quantum parametric amplifier is proposed. Figure 1 The shown is a schematic flowchart of the method.

[0037] As Figure 1 shown, the method may include the following steps:

[0038] S1 Fabricate a transmission line and Josephson junctions on a parametric amplifier chip, and expose and etch a space of a preset size at a preset position on the transmission line. First, structures such as a transmission line, Josephson junctions, air bridges, and flux bias lines are fabricated on the parametric amplifier chip through photolithography. During the fabrication of the transmission line, a space of a preset size is exposed and etched on the aluminum mold of the transmission line through photolithography and etching processes to place a commercial chip capacitor. The length of the space of the preset size is 1 mm, the width is 1 mm, and the depth is 100 nm. A 4 pF commercial chip capacitor can be used, with a length of about 1 mm and a thickness of about 0.5 mm.

[0039] S2 Place the chip capacitor in the space of the preset size and fix the chip capacitor in the space of the preset size using cryogenic glue. The chip capacitor can be placed at the position of the preset space on the chip using tweezers and then fixed with cryogenic glue, which can effectively reduce the risk of the chip capacitor falling off the chip during cooling or movement.

[0040] S3 Connect both ends of the chip capacitor to both sides of the Josephson junction. The two ends of the chip capacitor and the two ends of the Josephson junction can be connected using a 25-micron-diameter superconducting aluminum wire on a spot welder to connect the chip capacitor and the SQUID in parallel, thereby forming a complete parametric amplifier chip. This connection method is relatively simple, but there is a possibility of breakdown of the Josephson junction during the operation process. Another relatively safe method is a microfabrication solution. After placing the chip capacitor at the position of the preset space on the parametric amplifier chip, a layer of superconducting aluminum wire is plated on the chip through photolithography technology, and the two ends of the chip capacitor and the two ends of the Josephson junction are connected after the lift-off process.

[0041] By using the technical solution of the present invention, the manufacturing yield of the parametric amplifier can be improved. The use of commercial patch capacitors enables the parametric amplifier to no longer rely on the insulating layer, keeping the performance of the parametric amplifier stable.

[0042] In a preferred embodiment of the present invention, a transmission line and a Josephson junction are fabricated on the parametric amplifier chip, and exposing and etching a space with a preset size at a preset position on the transmission line includes:

[0043] Exposing and etching a space with a preset size at a position on the transmission line close to the Josephson junction. The length of the space with the preset size is 1 mm, the width is 1 mm, and the depth is 100 nm. The commercial patch capacitor used in the present invention is a 4 pF commercial patch capacitor, with a length of about 1 mm and a thickness of about 0.5 mm. Therefore, a space of the above size is reserved. If patch capacitors of other sizes or models are used, the size of the preset space can be adjusted as needed.

[0044] In a preferred embodiment of the present invention, connecting the two ends of the patch capacitor to both sides of the Josephson junction includes:

[0045] Using a superconducting aluminum wire with a diameter of 25 microns on a spot welder to connect the two ends of the patch capacitor to both sides of the Josephson junction.

[0046] In a preferred embodiment of the present invention, connecting the two ends of the patch capacitor to both sides of the Josephson junction includes:

[0047] Coating a layer of superconducting aluminum wire on the parametric amplifier chip through lithography technology to connect the two ends of the patch capacitor to both sides of the Josephson junction.

[0048] By using the technical solution of the present invention, the manufacturing yield of the parametric amplifier can be improved. The use of commercial patch capacitors enables the parametric amplifier to no longer rely on the insulating layer, keeping the performance of the parametric amplifier stable.

[0049] It should be noted that those of ordinary skill in the art can understand that all or part of the processes in the above method embodiments can be completed by instructing relevant hardware through a computer program. The above program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the above method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc. The embodiments of the above computer program can achieve the same or similar effects as the corresponding foregoing method embodiments.

[0050] In addition, the method disclosed according to the embodiments of the present invention can also be implemented as a computer program executed by a CPU, and this computer program can be stored in a computer-readable storage medium. When this computer program is executed by the CPU, the above-mentioned functions defined in the method disclosed according to the embodiments of the present invention are executed.

[0051] Based on the above object, in the second aspect of the embodiments of the present invention, a device for preparing a superconducting quantum parametric amplifier is proposed. As Figure 2 shown, the device 200 includes:

[0052] A preparation module configured to prepare a transmission line and a Josephson junction on a parametric amplifier chip, and expose and etch a space with a preset size at a preset position on the transmission line;

[0053] A fixing module configured to place a patch capacitor in the space with the preset size and fix the patch capacitor in the space with the preset size using cryogenic glue;

[0054] A connection module configured to connect both ends of the patch capacitor to both sides of the Josephson junction.

[0055] In a preferred embodiment of the present invention, the preparation module is further configured to:

[0056] Expose and etch a space with a preset size at a position on the transmission line close to the Josephson junction. The length of the space with the preset size is 1 mm, the width is 1 mm, and the depth is 100 nm.

[0057] In a preferred embodiment of the present invention, the connection module is further configured to:

[0058] Connect both ends of the patch capacitor to both sides of the Josephson junction using a superconducting aluminum wire with a diameter of 25 microns on a spot welder.

[0059] In a preferred embodiment of the present invention, the connection module is further configured to:

[0060] Connect both ends of the patch capacitor to both sides of the Josephson junction by plating a layer of superconducting aluminum wire on the parametric amplifier chip through a photolithography technique.

[0061] Based on the above object, in the third aspect of the embodiments of the present invention, a computer device is proposed. Figure 3 Shown is a schematic diagram of an embodiment of the computer device provided by the present invention. As Figure 3 shown, the embodiments of the present invention include the following devices: at least one processor 21; and a memory 22, where the memory 22 stores computer instructions 23 that can run on the processor. When the instructions are executed by the processor, the following method is implemented:

[0062] A transmission line and a Josephson junction are fabricated on a parametric amplifier chip, and a space with a preset size is exposed and etched at a preset position on the transmission line;

[0063] The patch capacitor is placed in the space with the preset size and fixed in the space with the preset size using cryogenic glue;

[0064] Both ends of the patch capacitor are connected to both sides of the Josephson junction.

[0065] In a preferred embodiment of the present invention, fabricating a transmission line and a Josephson junction on a parametric amplifier chip, and exposing and etching a space with a preset size at a preset position on the transmission line includes:

[0066] A space with a preset size is exposed and etched at a position on the transmission line close to the Josephson junction. The length of the space with the preset size is 1 mm, the width is 1 mm, and the depth is 100 nm.

[0067] In a preferred embodiment of the present invention, connecting both ends of the patch capacitor to both sides of the Josephson junction includes:

[0068] Both ends of the patch capacitor are connected to both sides of the Josephson junction using a superconducting aluminum wire with a diameter of 25 microns on a spot welder.

[0069] In a preferred embodiment of the present invention, connecting both ends of the patch capacitor to both sides of the Josephson junction includes:

[0070] Both ends of the patch capacitor are connected to both sides of the Josephson junction by plating a layer of superconducting aluminum wire on the parametric amplifier chip through photolithography technology.

[0071] Based on the above objectives, a fourth aspect of the embodiments of the present invention proposes a computer-readable storage medium. Figure 4 Shown is a schematic diagram of an embodiment of the computer-readable storage medium provided by the present invention. As Figure 4 shown, the computer-readable storage medium 31 stores a computer program 32 that, when executed by a processor, executes the following method:

[0072] A transmission line and a Josephson junction are fabricated on a parametric amplifier chip, and a space with a preset size is exposed and etched at a preset position on the transmission line;

[0073] The patch capacitor is placed in the space with the preset size and fixed in the space with the preset size using cryogenic glue;

[0074] Both ends of the patch capacitor are connected to both sides of the Josephson junction.

[0075] In a preferred embodiment of the present invention, a transmission line and a Josephson junction are fabricated on a parametric amplifier chip, and a space with a preset size is exposed and etched at a preset position on the transmission line, including:

[0076] A space with a preset size is exposed and etched at a position on the transmission line close to the Josephson junction. The length of the space with the preset size is 1 mm, the width is 1 mm, and the depth is 100 nm.

[0077] In a preferred embodiment of the present invention, connecting the two ends of the patch capacitor to both sides of the Josephson junction includes:

[0078] Using a superconducting aluminum wire with a diameter of 25 microns on a spot welder to connect the two ends of the patch capacitor to both sides of the Josephson junction.

[0079] In a preferred embodiment of the present invention, connecting the two ends of the patch capacitor to both sides of the Josephson junction includes:

[0080] Connecting the two ends of the patch capacitor to both sides of the Josephson junction by plating a layer of superconducting aluminum wire on the parametric amplifier chip through lithography technology.

[0081] In addition, the method disclosed according to the embodiments of the present invention can also be implemented as a computer program executed by a processor, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the above functions defined in the method disclosed in the embodiments of the present invention are executed.

[0082] In addition, the above method steps and system units can also be implemented by using a controller and a computer-readable storage medium for storing a computer program that enables the controller to implement the functions of the above steps or units.

[0083] Those skilled in the art will also understand that the various exemplary logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, a general description has been given of the functions of the various illustrative components, blocks, modules, circuits, and steps. Whether this function is implemented as software or hardware depends on the specific application and the design constraints imposed on the overall system. The functions that can be implemented in various ways by those skilled in the art for each specific application, but this implementation decision should not be construed as causing a departure from the scope of the disclosure of the embodiments of the present invention.

[0084] In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another. The storage media may be any available media that can be accessed by a general-purpose or special-purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0085] The above are exemplary embodiments disclosed by the present invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed by the present invention as defined by the claims. The functions, steps, and / or actions of the method claims according to the disclosed embodiments herein need not be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or claimed in individual form, they may also be understood as plural unless explicitly limited to the singular.

[0086] It should be understood that, as used herein, unless the context clearly supports exceptions, the singular forms "a", "an" are also intended to include the plural forms. It should also be understood that the term "and / or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0087] The serial numbers of the disclosed embodiments of the present invention above are merely for description and do not represent the superiority or inferiority of the embodiments.

[0088] Those of ordinary skill in the art can understand that all or part of the steps to implement the above embodiments can be completed by hardware, or can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disc, etc.

[0089] Those of ordinary skill in the art should understand that the discussion of any above embodiment is only exemplary, and is not intended to imply that the scope (including the claims) disclosed by the embodiments of the present invention is limited to these examples; under the idea of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other variations in different aspects of the above embodiments of the present invention, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present invention shall be included in the protection scope of the embodiments of the present invention.

Claims

1. A method for preparing a superconducting quantum parametric amplifier, characterized in that, Including the following steps: Fabricate a transmission line and a Josephson junction on a parametric amplifier chip, and expose and etch a space with a preset size at a preset position on the transmission line; Place a chip capacitor in the space with the preset size, and fix the chip capacitor in the space with the preset size using cryogenic glue; Connect both ends of the chip capacitor to both sides of the Josephson junction; Among them, connecting both ends of the chip capacitor to both sides of the Josephson junction includes: plating a layer of superconducting aluminum wire on the parametric amplifier chip through photolithography technology, and connecting both ends of the chip capacitor to both sides of the Josephson junction through a lift-off process.

2. The method according to claim 1, wherein Fabricating a transmission line and a Josephson junction on a parametric amplifier chip, and exposing and etching a space with a preset size at a preset position on the transmission line includes: Expose and etch a space with a preset size at a position on the transmission line close to the Josephson junction, where the length of the space with the preset size is 1 mm, the width is 1 mm, and the depth is 100 nm.

3. The method according to claim 1, wherein Connecting both ends of the chip capacitor to both sides of the Josephson junction includes: Connect both ends of the chip capacitor to both sides of the Josephson junction using a superconducting aluminum wire with a diameter of 25 microns on a spot welder.

4. A device for preparing a superconducting quantum parametric amplifier, characterized in that, The device includes: A preparation module configured to fabricate a transmission line and a Josephson junction on a parametric amplifier chip, and expose and etch a space with a preset size at a preset position on the transmission line; A fixing module configured to place a chip capacitor in the space with the preset size, and fix the chip capacitor in the space with the preset size using cryogenic glue; A connection module configured to connect both ends of the chip capacitor to both sides of the Josephson junction; Among them, the connection module is further configured to plate a layer of superconducting aluminum wire on the parametric amplifier chip through photolithography technology, and connect both ends of the chip capacitor to both sides of the Josephson junction through a lift-off process.

5. The device according to claim 4, characterized in that, The preparation module is further configured to: Expose and etch a space with a preset size at a position on the transmission line close to the Josephson junction, where the length of the space with the preset size is 1 mm, the width is 1 mm, and the depth is 100 nm.

6. The device according to claim 4, characterized in that The connection module is further configured to: Connect both ends of the chip capacitor to both sides of the Josephson junction using a superconducting aluminum wire with a diameter of 25 microns on a spot welder.

7. A computer device, characterized in that, Including: At least one processor; And A memory storing computer instructions executable on the processor, and when the instructions are executed by the processor, the steps of the method according to any one of claims 1-3 are implemented.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, the steps of the method according to any one of claims 1-3 are implemented.

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