A power-on reset circuit

Abstract

The application discloses a power-on reset circuit, which is characterized in that the circuit comprises an analog power judgment unit, a digital power judgment unit, a current conversion unit and a logic unit; wherein the analog power judgment unit and the digital power judgment unit respectively determine the power-on state of an analog power supply and a digital power supply through an under-voltage lockout logic, and output an analog power-on judgment voltage and a digital power-on judgment voltage; the current conversion unit is connected with the digital power judgment unit, receives the digital power-on judgment voltage and generates a digital power-on judgment current; the logic unit is respectively connected with the current conversion unit and the analog power judgment unit, and realizes the output of a chip power-on reset signal based on the digital power-on judgment current and the analog power-on judgment voltage.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically, to a power-on reset circuit for a chip. Background Technology

[0002] Currently, power-on reset circuits are commonly used in integrated circuits. During the stage when the chip is not fully powered on and the power supply voltage is slowly rising, a control signal is provided to the subsequent circuits in the chip to ensure that the chip executes the normal circuit program only after the power supply is fully powered on and the power supply voltage is stable, and to prevent chip logic errors caused by low power supply.

[0003] In chips with multiple voltage domains, such as those with both analog and digital power supplies, the power-on reset circuit needs to simultaneously detect the power-on status of multiple different power supplies. Only after all power supplies are fully powered on should the chip's normal logic be executed. In existing technology, undervoltage lockout logic is typically used to determine whether the digital power supply is powered on. The power-on determination signal for the digital power supply is input to a level shifter controlled by the analog power supply to ensure that a chip power-on reset signal is output after the analog circuit is also powered on.

[0004] However, this type of power-on reset circuit still has some problems. For example, when the digital power supply is powered on but the analog power supply is not yet powered on, the level shifter will generate an unpredictable output after receiving the power-on signal from the digital power supply, which may lead to the issuance of an incorrect power-on reset signal. This may cause the chip to enter the normal working state prematurely during the power-on process, resulting in various errors or malfunctions.

[0005] To address the above problems, this invention proposes a novel power-on reset circuit. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a power-on reset circuit that acquires the power-on status of both the digital power supply and the analog power supply, converts the digital power-on judgment voltage into a digital power-on judgment current, and then outputs the chip power-on reset signal through a logic module.

[0007] The present invention adopts the following technical solution.

[0008] The first aspect of this invention relates to a power-on reset circuit, comprising an analog power supply judgment unit, a digital power supply judgment unit, a current conversion unit, and a logic unit; wherein the analog power supply judgment unit and the digital power supply judgment unit determine the power-on state of the analog power supply and the digital power supply respectively through undervoltage lockout logic, and output an analog power-on judgment voltage and a digital power-on judgment voltage; the current conversion unit is connected to the digital power supply judgment unit, receives the digital power-on judgment voltage, and generates a digital power-on judgment current; the logic unit is connected to the current conversion unit and the analog power supply judgment unit respectively, and outputs a chip power-on reset signal based on the digital power-on judgment current and the analog power-on judgment voltage.

[0009] Preferably, the analog power supply judgment unit and the digital power supply judgment unit have the same circuit structure; and the circuit structure includes a bandgap reference source, a voltage divider branch, a comparator, and an inverter; wherein, the bandgap reference source generates a reference voltage Vref under the drive of the digital power supply or analog power supply, the voltage divider branch divides the digital power supply or analog power supply and generates a divided voltage Vdiv; the comparator compares the reference voltage Vref and the divided voltage Vdiv and outputs the comparison voltage to the inverter; the inverter outputs an analog power-on judgment voltage or a digital power-on judgment voltage.

[0010] Preferably, the power conversion unit includes first to third current sources, a first switching transistor, a second switching transistor, a first image transistor, a second image transistor, and a capacitor; wherein, one end of the first current source is connected to a digital power supply voltage, and the other end is connected to the first image transistor through the first switching transistor, and the gate of the first switching transistor is connected to the output terminal of the digital power supply judgment unit; the gate and drain of the first image transistor are respectively connected to one end of the second current source and the gate of the second image transistor; the source of the first image transistor, the source of the second image transistor, and the other end of the second current source are all connected to analog ground; one end of the third current source is connected to an analog power supply voltage, and the other end is connected to the drain of the second image transistor, the source and drain of the second switching transistor are connected in parallel across the three ends of the third current source, and the gate is connected to the reverse signal of the output terminal of the analog power supply judgment unit; the capacitor is connected in parallel across the drain and source of the second image transistor.

[0011] Preferably, the logic unit includes a NOT gate and an AND gate; wherein, one end of the NOT gate is connected to the digital power-on judgment current, and the other end is connected to the first input terminal of the AND gate; the second input terminal of the AND gate is connected to the analog power-on judgment voltage, and the output terminal generates a chip power-on reset signal.

[0012] Preferably, when the analog power supply has not yet completed power-on, regardless of whether the digital power supply has completed power-on, the analog power-on judgment voltage is low and the chip power-on reset signal is low.

[0013] Preferably, when the analog power supply is powered on, if the digital power supply is not yet powered on, the first switch is turned off, the digital power-on judgment current charges the capacitor and provides a high-level signal to the input terminal of the NOT gate in the logic unit, and the chip power-on reset signal is low-level; if the digital power supply is powered on, the first switch is turned on, the digital power-on judgment current discharges the capacitor and provides a low-level signal to the input terminal of the NOT gate in the logic unit, and the chip power-on reset signal is high-level.

[0014] Preferably, when the analog power supply has finished powering on but the digital power supply has not yet finished powering on, the digital power-on judgment current is I1; when both the analog and digital power supplies have finished powering on, the digital power-on judgment current is N*(I pord -I0)-I1; where I pord I0 and I1 are the current values ​​of the first current source, the second current source, and the third current source, respectively, and N is the current mirroring multiple of the first and second image transistors.

[0015] The beneficial effect of this invention is that, compared with the prior art, the power-on reset circuit of this invention can separately acquire the power-on state of digital power supply and analog power supply, convert the digital power-on judgment voltage into digital power-on judgment current, and then output the chip power-on reset signal through a logic module. This invention is simple in method and ingenious in approach, effectively avoiding the use of level shifters, allowing the circuit to achieve joint verification of the power-on state of multiple power supply voltage ranges by interchangeping voltage and current.

[0016] The beneficial effects of the present invention also include:

[0017] 1. Due to the addition of a current conversion unit, this invention no longer requires a level shifter to convert the voltage range of the digital power supply to the voltage range of the analog power supply, thus avoiding the output error problem of the level shifter. Furthermore, because this invention converts the digital power-on judgment voltage into a corresponding current, and then uses this current to charge and discharge the capacitor, the logic unit can acquire the capacitor voltage that is completely related to this current, thereby achieving accurate logic output.

[0018] 2. In this invention, in order to prevent possible abnormalities in the current mirror in the current conversion unit, a small current source is connected to the gate of the two mirror MOS transistors in the current mirror. Without affecting the basic logic of the current conversion unit, the gate voltage Vx of the two mirror MOS transistors is limited so that Vx will not be in a floating state under any circumstances, thus further ensuring the accuracy of the logic. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the power-on reset circuit in a multi-power supply chip in the prior art;

[0020] Figure 2 This is a schematic diagram of the circuit structure of the digital power supply judgment unit in a power-on reset circuit according to the present invention.

[0021] Figure 3 This is a schematic diagram of the circuit structure of the analog power supply judgment unit, power conversion unit and logic unit in a power-on reset circuit of the present invention;

[0022] Figure 4 This is a schematic diagram of the current conversion unit generating a digital power-on judgment current when the chip power-on is completed in a power-on reset circuit of the present invention;

[0023] Figure 5 This is a schematic diagram of a current conversion unit generating a digital power-on judgment current when the chip power-on is not complete in a power-on reset circuit according to the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The embodiments described in this application are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, other embodiments obtained by those skilled in the art without creative effort are all within the protection scope of this invention.

[0025] Figure 1 This is a schematic diagram of the power-on reset circuit in a multi-power supply chip in the prior art. Figure 1 As shown, in the prior art, in order to simultaneously determine whether each power supply in the chip has completed power-on, a level shifter is connected after the undervoltage lockout circuit used to determine the digital power supply DVDD (Digital VDD). Since this level shifter is controlled by the analog power supply AVDD (Analog VDD), ideally, the circuit will only provide the chip power-on reset signal apoorb when the analog power supply is powered on.

[0026] However, in practice, when the digital power supply has been fully powered on but the analog power supply has not been fully powered on, the circuit will provide a high-level dporb signal. This signal, when input to the level shifter, may cause the output of the level shifter to become unpredictable.

[0027] To overcome this problem, the present invention provides a new power-on reset circuit.

[0028] Figure 2 This is a schematic diagram of the circuit structure of the digital power supply judgment unit in a power-on reset circuit according to the present invention. Figure 2As shown, a power-on reset circuit includes an analog power supply judgment unit, a digital power supply judgment unit, a current conversion unit, and a logic unit. The analog power supply judgment unit and the digital power supply judgment unit determine the power-on state of the analog power supply and the digital power supply respectively through undervoltage lockout logic, and output an analog power-on judgment voltage and a digital power-on judgment voltage. The current conversion unit is connected to the digital power supply judgment unit, receives the digital power-on judgment voltage, and generates a digital power-on judgment current. The logic unit is connected to both the current conversion unit and the analog power supply judgment unit, and outputs a chip power-on reset signal based on the digital power-on judgment current and the analog power-on judgment voltage.

[0029] It is understood that the analog power supply judgment unit and digital power supply judgment unit in this invention can adopt the undervoltage lockout logic commonly used in the prior art. Since the undervoltage lockout logic circuit in the prior art is not unique, the structure and mode of the circuit can be reasonably selected according to the specific situation of the chip in this invention. The undervoltage lockout logic circuit provided in this embodiment essentially generates a relatively stable bandgap reference voltage at one end of the comparator using the DVDD voltage, while at the other end of the comparator, the size of the DVDD is sensed by dividing the DVDD voltage. After comparing the DVDD voltage Vdiv with the constant reference voltage Vref, the comparator obtains a high level or a low level. A high level indicates that Vref is relatively large compared to Vdiv, therefore the DVDD power-on is not complete, while a low level indicates that Vref is relatively small compared to Vdiv, and the DVDD power-on is complete. The comparison signal cmp generated by the comparator is then passed through an inverter and used as the digital power-on judgment voltage dporb in this invention.

[0030] Preferably, the analog power supply judgment unit and the digital power supply judgment unit have the same circuit structure; and the circuit structure includes a bandgap reference source, a voltage divider branch, a comparator, and an inverter; wherein, the bandgap reference source generates a reference voltage Vref under the drive of the digital power supply or analog power supply, the voltage divider branch divides the digital power supply or analog power supply and generates a divided voltage Vdiv; the comparator compares the reference voltage Vref and the divided voltage Vdiv and outputs the comparison voltage to the inverter; the inverter outputs an analog power-on judgment voltage or a digital power-on judgment voltage.

[0031] It is understood that the structure of the undervoltage lockout logic circuit for determining DVDD and AVDD in this invention can be exactly the same, or it can be adjusted to a certain extent according to the actual situation of the chip, such as the voltage range of DVDD and AVDD. However, the idea of ​​using undervoltage lockout logic to determine whether power-on is complete remains unchanged.

[0032] Figure 3This is a schematic diagram of the circuit structure of the analog power supply judgment unit, power conversion unit, and logic unit in a power-on reset circuit according to the present invention. Figure 3 As shown, preferably, the power conversion unit includes first to third current sources, a first switching transistor, a second switching transistor, a first image transistor, a second image transistor, and a capacitor; wherein, one end of the first current source is connected to the digital power supply voltage, and the other end is connected to the first image transistor through the first switching transistor, and the gate of the first switching transistor is connected to the output terminal of the digital power supply judgment unit; the gate and drain of the first image transistor are respectively connected to one end of the second current source and the gate of the second image transistor; the source of the first image transistor, the source of the second image transistor, and the other end of the second current source are all connected to analog ground; one end of the third current source is connected to the analog power supply voltage, and the other end is connected to the drain of the second image transistor, the source and drain of the second switching transistor are connected in parallel across the three ends of the third current source, and the gate is connected to the reverse signal of the output terminal of the analog power supply judgment unit; the capacitor is connected in parallel across the drain and source of the second image transistor.

[0033] It is understood that, although the analog power-on judgment voltage and the digital power-on judgment voltage can be obtained separately in this invention, the two voltages do not remain at the same value when they are in a high-level state. In other words, due to the different voltage ranges of DVDD and AVDD, two voltage signals of different magnitudes cannot be directly compared through the logic unit. Furthermore, as described above, level shifters should be avoided in this invention as much as possible to prevent errors in the output logic.

[0034] In this case, the present invention converts one of the voltages of DVDD or AVDD into a reasonable current magnitude, then converts it back to a voltage with the same range as the other voltage through the charging and discharging of a capacitor, and then performs logical transformation of the signal through a logic unit.

[0035] Therefore, this invention adds a new current conversion unit to the existing circuit. In this unit, the first switching transistor can sense the magnitude of the digital power-on judgment voltage and determine whether to output the corresponding digital power-on judgment current. After passing through a current mirror, the other end of the current conversion unit can mirror the digital power-on judgment current and simultaneously influence the charging and discharging of the capacitor through this current.

[0036] On the other hand, if the first switch in the unit is in the off state, then the third current source will be connected to the circuit. At this time, the current mirror itself will not output any current, and the current of the third current source will modify the charging and discharging state of the capacitor by flowing in the opposite direction to the mirror current.

[0037] Under the combined effect of the aforementioned currents, the capacitor can be charged or discharged according to the power-on state of the circuit, thereby providing a reasonable capacitor voltage Vc for the logic circuit.

[0038] Preferably, the logic unit includes a NOT gate and an AND gate; wherein, one end of the NOT gate is connected to the digital power-on judgment current, and the other end is connected to the first input terminal of the AND gate; the second input terminal of the AND gate is connected to the analog power-on judgment voltage, and the output terminal generates a chip power-on reset signal.

[0039] It is understood that the circuit of the logic unit in this invention can perform corresponding logical conversion on the converted digital power-on judgment voltage and the unconverted analog power-on judgment voltage, thereby generating an accurate chip power-on reset signal based on the above two voltage signals.

[0040] Preferably, when the analog power supply has not yet completed power-on, regardless of whether the digital power supply has completed power-on, the analog power-on judgment voltage is low and the chip power-on reset signal is low.

[0041] right Figure 2 and Figure 3 Analysis of the circuit shows that when the analog power supply is not fully powered on, even if Ipord can input current into the current mirror through S1, the cmpa signal is still at a high level, which causes the aporb_mid signal to be at a low level. After passing through the AND gate, the aporb signal is output at a low level.

[0042] Figure 4 This is a schematic diagram of the current conversion unit generating a digital power-on judgment current when the chip completes power-on in a power-on reset circuit according to the present invention. Figure 5 This is a schematic diagram illustrating how a current conversion unit generates a digital power-on judgment current when the chip's power-on process is incomplete in a power-on reset circuit according to the present invention. Figure 4 and Figure 5 As shown, preferably, when the analog power supply is powered on, if the digital power supply has not yet been powered on, the first and second switching transistors are turned off, the digital power-on judgment current charges the capacitor and provides a high-level signal to the input terminal of the NOT gate in the logic unit, and the chip power-on reset signal is low-level; if the digital power supply is powered on, the first and second switching transistors are turned on, the digital power-on judgment current discharges the capacitor and provides a low-level signal to the input terminal of the NOT gate in the logic unit, and the chip power-on reset signal is high-level.

[0043] Preferably, when the analog power supply has finished powering on but the digital power supply has not yet finished powering on, the digital power-on judgment current is I1; when both the analog and digital power supplies have finished powering on, the digital power-on judgment current is N*(I pord -I0)-I1; where I pord I0 and I1 are the current values ​​of the first current source, the second current source, and the third current source, respectively, and N is the current mirroring multiple of the first and second image transistors.

[0044] Understandably, if the AVDD has been fully powered on, then based on the DVDD's power-on state, the circuit output can be categorized into two different states. First, as... Figure 4 As shown, when DVDD is also powered on, switch S1 is in the on state, inputting the current Ipord from the first current source into the current mirror. In this invention, considering the stability of the current mirror under various conditions, a second current source I0 is added between the gates of the two current mirrors and the simulated ground potential. Under the action of this current source, not all of the current Ipord is input into the current mirror; the current generated by the current mirror is only Ipord - I0. When AVDD is fully powered on, cmpa is at a low level, therefore the second switch is always in the off state, and the third current source can continuously provide current I1 to the current mirror.

[0045] Therefore, when the DVDD is powered on, the discharge current received on the capacitor side is N*(I pord -I0)-I1. It's easy to see that, to ensure the capacitor fully discharges under these conditions, Ipord-I0 should be set to a suitable value greater than I1. Due to the capacitor's discharge, the voltage at point Vc decreases, causing the aporb signal output by the logic unit to go high.

[0046] On the other hand, if the DVDD has not yet been powered on, the current mirror will not receive any input and will not provide an output current I2. Therefore, the discharge current received by the capacitor side should be equal to I1. At this time, the capacitor will charge under the action of I1, raising the voltage at point Vc. At this time, the apoorb signal is in a low level state.

[0047] In this way, the present invention effectively achieves accurate circuit output, enabling the chip to provide accurate execution logic based on the state of the chip power-on reset signal.

[0048] The beneficial effect of the present invention is that, compared with the prior art, the power-on reset circuit of the present invention obtains the power-on state of the digital power supply and the analog power supply respectively, converts the digital power-on judgment voltage into the digital power-on judgment current, and then realizes the output of the chip power-on reset signal through the logic module.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A power-on reset circuit, characterized in that: The circuit includes an analog power supply judgment unit, a digital power supply judgment unit, a current conversion unit, and a logic unit; wherein... The analog power supply judgment unit and the digital power supply judgment unit determine the power-on state of the analog power supply and the digital power supply respectively through undervoltage lockout logic, and output analog power-on judgment voltage and digital power-on judgment voltage. The circuit structure of the analog power supply judgment unit and the digital power supply judgment unit is the same. The circuit structure includes a bandgap reference source, a voltage divider branch, a comparator, and an inverter. The bandgap reference source generates a reference voltage Vref under the drive of the digital power supply or the analog power supply. The voltage divider branch divides the digital power supply or the analog power supply to generate a divided voltage Vdiv. The comparator compares the reference voltage Vref and the divided voltage Vdiv and outputs the comparison voltage to the inverter. The inverter outputs the analog power-on judgment voltage or the digital power-on judgment voltage. The current conversion unit is connected to the digital power supply judgment unit, receives the digital power-on judgment voltage and generates the digital power-on judgment current; The logic unit is connected to the current conversion unit and the analog power supply judgment unit respectively, and outputs the chip power-on reset signal based on the digital power-on judgment current and the analog power-on judgment voltage.

2. The power-on reset circuit according to claim 1, characterized in that: The current conversion unit includes first to third current sources, a first switching transistor, a second switching transistor, a first image transistor, a second image transistor, and a capacitor; wherein, One end of the first current source is connected to the digital power supply voltage, and the other end is connected to the first mirror transistor through the first switching transistor. The gate of the first switching transistor is connected to the output terminal of the digital power supply judgment unit. The gate and drain of the first mirror transistor are respectively connected to one end of the second current source and the gate of the second mirror transistor; The source of the first mirror transistor, the source of the second mirror transistor, and the other end of the second current source are all connected to analog ground; One end of the third current source is connected to the analog power supply voltage, and the other end is connected to the drain of the second mirror transistor. The source and drain of the second switching transistor are connected in parallel across the three ends of the third current source, and the gate is connected to the reverse signal of the output of the analog power supply judgment unit. The capacitor is connected in parallel across the drain and source terminals of the second mirror transistor.

3. The power-on reset circuit according to claim 2, characterized in that: The logic unit includes NOT gates and AND gates; Wherein, one end of the NOT gate is connected to the digital power-on judgment current, and the other end is connected to the first input terminal of the AND gate; The second input of the AND gate is connected to the analog power-on judgment voltage, and the output generates a chip power-on reset signal.

4. The power-on reset circuit according to claim 3, characterized in that: When the analog power supply has not yet completed power-on, regardless of whether the digital power supply has completed power-on, the analog power-on judgment voltage is low and the chip power-on reset signal is low.

5. A power-on reset circuit according to claim 3, characterized in that: When the analog power supply is powered on, if the digital power supply has not yet been powered on, the first switch is turned off, the digital power-on judgment current causes the capacitor to charge and provides a high-level signal to the NOT gate input terminal in the logic unit, and the chip power-on reset signal is low. If the digital power supply is powered on, the first switch is turned on, the digital power-on judgment current causes the capacitor to discharge, and provides a low-level signal to the NOT gate input terminal in the logic unit, while the chip power-on reset signal is high.

6. A power-on reset circuit according to claim 4, characterized in that: When the analog power supply has finished powering on but the digital power supply has not yet finished powering on, the digital power-on judgment current is... ; When both the analog power supply and the digital power supply have completed power-on, the digital power-on judgment current is: ; in, , and These are the current values ​​of the first current source, the second current source, and the third current source, respectively. The current mirroring factor between the first and second image transistors is denoted as .

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