Interface short-time drive implementation method, device, transmitter and receiver

Abstract

The present application relates to a method and device for implementing short-time interface driving, including a transmitter driving a data line to a high level, releasing the data line, maintaining the high level of the data line through a pull-up resistor, the receiver checking the parity check bit of the received character frame and finding an error, taking over the data line, driving the data line to a low level for a second time slice, driving the data line to a high level, releasing the data line, and the transmitter detecting the state of the data line at a first preset time, and determining to send the next character frame or resend the character frame according to the state of the data line. The present application avoids the communication error caused by the failure of the data line to be pulled up to a preset level in time when the interface is configured as a transmitter or a receiver in the prior art by driving the data line for a short time. At the same time, the present application enables the interface to achieve better performance, without the need for an external pull-up resistor component, and can be compatible with smaller F / D parameters, so that the performance of the interface is improved. The present application also relates to a receiver and a transmitter.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, device, transmitter and receiver for implementing short-time interface driving. Background Art

[0002] Smart cards and their reader systems are widely used in mobile communications, financial payments, transportation, public utilities, etc. Usually, contact smart cards and their information exchange with card readers are based on the ISO7816 protocol, including PSAM cards, SAM cards, SIM cards, etc., all of which comply with the ISO7816 protocol.

[0003] In the traditional interface design scheme that complies with the ISO7816 protocol, when the chip is configured as a transmitter, when the data reception error occurs and the data line is not pulled up to a high level at the specified time, the transmitter makes a misjudgment and cannot communicate normally. When the chip is configured as a receiver, when a data reception error is detected and the data line is not pulled up to a high level at the specified time, and the start bit of the data frame sent by the transmitter is low, the receiver cannot detect the correct frame structure, resulting in communication errors, which causes low interface communication performance of the smart card. Summary of the invention

[0004] The embodiment of the present application provides a method, device, transmitter and receiver for implementing short-time interface driving. The technical solution is as follows:

[0005] In a first aspect, an embodiment of the present application provides a method for implementing a short-time interface drive, wherein a transmitter and a receiver perform data transmission based on the same data line, and the method includes:

[0006] When the transmitter detects that the value of the parity bit of the transmitted character frame is logic 0, the transmitter drives the data line to a high level state from the protection bit start position of the character frame and maintains the high level state for a first time slice, then releases the data line and maintains the high level state of the data line through a pull-up resistor;

[0007] The receiver checks the parity bit of the received character frame, and if the check result is an error, takes over the data line from the second preset time, first drives the data line to a low level state for a second time slice or a third time slice, then drives the data line to a high level state for a fourth time slice, and then releases the data line;

[0008] The transmitter detects the state of the data line at a first preset time, and determines to send a next character frame or resend the character frame according to the state of the data line.

[0009] In a second aspect, an embodiment of the present application provides a method for implementing short-time interface driving, the method comprising:

[0010] When the transmitter detects that the value of the parity check bit of the transmitted character frame is logic 0, the transmitter drives the data line to a high level state from the protection bit of the character frame and maintains the state for a first time slice, then releases the data line and maintains the high level state of the data line through a pull-up resistor, so that the receiver checks the received character frame and changes the state of the data line according to the check result;

[0011] The transmitter detects the state of the data line at a first preset time, and determines to send a next character frame or resend the character frame according to the state of the data line.

[0012] In a third aspect, an embodiment of the present application provides a method for implementing short-time interface driving, the method comprising:

[0013] When a falling edge appears on the data line, the receiver starts to receive a character frame;

[0014] The receiver checks the parity bit of the received character frame. If the check result is an error, it takes over the data line from the second preset moment, first drives the data line to a low level state and continues for a second time slice or a third time slice, then drives the data line to a high level state and continues for a fourth time slice, and then releases the data line to enable the transmitter to resend the character frame.

[0015] In a fourth aspect, an embodiment of the present application provides a device for implementing short-time interface driving, comprising a first processing unit and a second processing unit;

[0016] The first processing unit is used to detect that the value of the parity check bit of the transmitted character frame is logic 0, drive the data line to a high level state from the protection bit starting position of the character frame and maintain it for a first time slice, release the data line, and maintain the high level state of the data line through a pull-up resistor, so that the receiver checks the received character frame and changes the state of the data line according to the check result;

[0017] The second processing unit is used to detect the state of the data line at a first preset time, and determine to send a next character frame or resend the character frame according to the state of the data line.

[0018] In a fifth aspect, an embodiment of the present application provides a device for implementing short-time interface driving, comprising a third processing unit and a fourth processing unit;

[0019] The third processing unit is used for causing the receiver to start receiving character frames when a falling edge appears on the data line;

[0020] The fourth processing unit is used for the receiver to check the parity bit of the received character frame. If the check result is an error, it takes over the data line from the second preset time, first drives the data line to a low level state and continues for a second time slice or a third time slice, then drives the data line to a high level state and continues for a fourth time slice, and then releases the data line to enable the transmitter to resend the character frame.

[0021] In the sixth aspect, an embodiment of the present application provides a transmitter, comprising at least a memory and a processor; wherein the processor is used to execute the interface short-time drive implementation method as described in the second aspect above; and the memory is used to store the program required for the processor to perform the operation.

[0022] In the seventh aspect, an embodiment of the present application provides a receiver, comprising at least a memory and a processor; wherein the processor is used to execute the interface short-time drive implementation method as described in the third aspect above; and the memory is used to store the program required for the processor to perform the operation.

[0023] In the seventh aspect, an embodiment of the present application provides a chip system, wherein the first chip in the chip system is configured as a receiver, the second chip in the chip system is configured as a transmitter, the transmitter and the receiver perform data transmission based on the same data line, and the chip system executes the interface short-time drive implementation method described in the first aspect above.

[0024] The beneficial effects brought about by the technical solutions provided by some embodiments of the present application include at least:

[0025] The embodiment of the present application provides a method for implementing short-time interface driving, which avoids the communication error caused by the failure of the data line to be pulled up to the preset level in time when the interface is configured as a transmitter or a receiver in the prior art by short-time driving the data line. At the same time, the present application enables the interface to achieve better performance, without the need for external pull-up resistor elements, and can be compatible with smaller F / D parameters, so that the performance of the interface is further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 It is a flowchart of a method for implementing short-time interface driving provided by an embodiment of the present application;

[0028] Figure 2It is a flowchart of a method for implementing short-time interface driving provided by another embodiment of the present application;

[0029] Figure 3 is a schematic diagram of a character frame structure provided by another embodiment of the present application;

[0030] Figure 4 is a schematic diagram of a method for implementing short-time interface driving provided by another embodiment of the present application;

[0031] Figure 5 This is a schematic diagram of the result of another embodiment of the present application using a method for implementing a short-time interface drive;

[0032] Figure 6 It is a flowchart of a method for implementing short-time interface driving provided by another embodiment of the present application;

[0033] Figure 7 It is a flowchart of a method for implementing short-time interface driving provided by another embodiment of the present application;

[0034] Figure 8 is a module schematic diagram of a transmitter provided by another embodiment of the present application;

[0035] Fig. 9 It is a module schematic diagram of a receiver provided in another embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to make the objectives, technical solutions and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0037] When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims.

[0038] In the description of the present application, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances. In addition, in the description of the present application, unless otherwise specified, "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0039] Embodiment 1:

[0040] The following will be combined with the attached Figure 1 , a method for implementing short-time interface driving provided in an embodiment of the present application is introduced in detail.

[0041] An embodiment of the present application provides a method for implementing short-time driving of an interface, wherein a transmitter and a receiver perform data transmission based on the same data line, including the following steps:

[0042] S1. The transmitter detects that the value of the parity bit of the transmitted character frame is logic 0, and drives the data line to a high level from the start position of the protection bit of the character frame and maintains it for the first time slice.

[0043] S2, release the data line and keep the data line at a high level through the pull-up resistor.

[0044] S3. The receiver checks the parity bit of the received character frame. If the check result is an error, the receiver takes over the data line from the second preset time, first drives the data line to a low level state and lasts for a second time slice or a third time slice.

[0045] S4: The receiver drives the data line again to maintain a high level state for a fourth time slice, and then releases the data line.

[0046] S5. The transmitter detects the state of the data line at a first preset time, and determines to send the next character frame or resend the character frame according to the state of the data line.

[0047] Based on the above embodiment, further, step S5 specifically includes:

[0048] S51. The transmitter detects the data line at a first preset time. If it is a high level, execute step S52; otherwise, execute step S53.

[0049] S52: If the data line is in a high level state, the receiver receives the data correctly and is ready to send the next character frame at a third preset time.

[0050] S53. If the data line is in a low level state, the receiver receives the data incorrectly, and the transmitter resends the character frame until the receiver receives the data correctly or the transmitter repeats the transmission times greater than a preset upper limit.

[0051] Based on the above embodiment, further, step S6 is included:

[0052] S6. If the check result of the receiver on the parity bit of the received character frame is correct, the receiver continues to monitor the data line at the start position of the protection bit of the received character frame until the data line is detected to be at a low level, and then starts to receive the next character frame.

[0053] Based on the above embodiment, further, the method further includes S7:

[0054] S7. When the transmitter detects that the value of the parity bit of the character frame is logic 1, the transmitter releases the data line from the start position of the protection bit of the character frame and maintains the high level state of the data line through the pull-up resistor.

[0055] Based on the above embodiment, further, step S1 specifically includes:

[0056] When the transmitter detects that the value of the parity bit of the transmitted character frame is logic 0, the hardware logic unit of the transmitter sets the first output enable signal to a high level and sets the value of the first output data signal. After driving the data line to a high level from the starting position of the protection bit of the character frame and maintaining it for the first time slice, the hardware logic unit of the transmitter sets the first output enable signal to a low level.

[0057] Based on the above embodiment, further, step S3 specifically includes:

[0058] When the receiver finds that the parity check result of the received character frame is wrong, the hardware logic unit of the receiver sets the second output enable signal to a high level, takes over the data line from a second preset moment, sets the value of the second output data signal, drives the data line to a low level state and lasts for a second time slice or a third time slice.

[0059] Based on the above embodiment, further, step S4 specifically includes:

[0060] The value of the second output data signal is set again, and after driving the data line to be in a high level state for a fourth time slice, the hardware logic unit of the receiver sets the second output enable signal to be a low level, and releases the data line.

[0061] Based on the above embodiment, further, the transmitter drives the data line to a high level state, including:

[0062] When the transmitter detects that the first output enable signal is at a high level, the data line is controlled, and the pin of the transmitter outputs a preset voltage value according to the value of the first output data signal to drive the data line to a high level state.

[0063] The transmitter keeps the data line high through a pull-up resistor, including:

[0064] When the first output enable signal is at a low level, the transmitter releases the data line, and the pin of the transmitter is kept at a high level through a pull-up function, so that the data line remains in a high level state.

[0065] The receiver drives the data line high, including:

[0066] When the second output enable signal is at a high level, the receiver controls the data line, and the pin of the receiver outputs a preset voltage value according to the value of the second output data signal, and the data line goes to a high level;

[0067] The receiver drives the data line low and includes:

[0068] When the second output enable signal is at a high level, the receiver controls the data line, and the pin of the receiver outputs a voltage according to the value of the second output data signal to drive the data line to a low level.

[0069] Based on the above embodiment, further comprising:

[0070] The first preset time is the 11th time of the character frame, the second preset time is the 10.5th time of the character frame, and the third preset time is the 12th time of the character frame;

[0071] The first time slice is one communication clock cycle, the second time slice is one ETU, the third time slice is 2 ETUs, and the fourth time slice is one communication clock cycle.

[0072] The embodiment of the present application provides a method for implementing short-time interface driving, which avoids the communication error caused by the failure of the data line to be pulled up to the preset level in time when the interface is configured as a transmitter or a receiver in the prior art by short-time driving the data line. At the same time, the present application enables the interface to achieve better performance, without the need for external pull-up resistor elements, and can be compatible with smaller F / D parameters, so that the performance of the interface is further improved.

[0073] Embodiment 2:

[0074] The following will be combined with the attached Figure 2 , a method for implementing an interface provided in an embodiment of the present application is introduced in detail.

[0075] Embodiment 2 of the present application is applicable to a chip system, which includes a first chip and a second chip, wherein the first chip is configured as a receiver, and the second chip is configured as a transmitter, and the transmitter and the receiver perform data transmission based on the same data line, including the following steps:

[0076] 110. When the transmitter detects that the value of the parity bit of the transmitted character frame is logic 0, the hardware logic unit of the transmitter sets the first output enable signal to a high level and sets the value of the first output data signal.

[0077] For example, according to the frame structure of the 7816 forward protocol, if the data 0x03 is sent, 0_11000000_0_11 will appear on the data line in sequence, where the first stage is the start bit logic 0, the second stage is the low-bit first data 0x03, the third stage is the check bit logic 0, and the fourth stage is the protection bit.

[0078] If the data 0x01 is sent, 0_10000000_1_11 will appear on the data line in sequence, where the first stage is the start bit logic 0, the second stage is the low-bit first data 0x01, the third stage is the check bit logic 1, and the fourth stage is the protection bit.

[0079] 120. When the first output enable signal is at a high level, the transmitter first controls the data line, and the pin of the transmitter outputs a voltage according to the value of the first output data signal, drives the data line from the starting position of the protection bit of the character frame to a high level and maintains the first time slice.

[0080] 130. The hardware logic unit of the transmitter sets the first output enable signal to a low level again, releases the data line, and the pin of the transmitter is kept at a high level through a pull-up function, so that the data line remains in a high level state.

[0081] 140. When the falling edge appears on the data line, the receiver starts receiving the character frame.

[0082] 150. The receiver checks the parity bit of the received character frame. If the check result is an error, execute step 160; otherwise, execute step 240.

[0083] For example, according to the frame structure of the 7816 forward protocol, if 0_11000000_1_XXXX appears on the data line in sequence, where the first stage is the start bit logic 0, the second stage is the low-order data 0x03 sent first, and the third stage is the check bit logic 1, the check result is an error.

[0084] If 0_11000000_0_XXXX appears on the data line in sequence, where the first stage is the start bit logic 0, the second stage is the low-order data 0x03 sent first, and the third stage is the check bit logic 0, the check result is correct.

[0085] 160. If the check result is an error, the receiver takes over the data line from the second preset time, and the hardware logic unit of the receiver sets the second output enable signal to a high level and sets the value of the second output data signal.

[0086] 170. When the second output enable signal is at a high level, the receiver controls the data line, and the pin of the receiver outputs a voltage according to the value of the second output data signal, driving the data line to a low level for a second time slice or a third time slice.

[0087] For example, if the host in the chip system provides a 10M clock, then one communication clock cycle is 100ns, and the ETU depends on the communication protocol between the master and the slave. Its power-on reset value is 1 ETU, which is equal to 372 communication clock cycles, or 37200ns.

[0088] 180. The hardware logic unit of the receiver sets the value of the second output data signal again.

[0089] 190. When the second output enable signal is at a high level, the receiver controls the data line, and the pin of the receiver outputs a preset voltage value according to the value of the second output data signal, drives the data line to a high level for a fourth time slice, and then releases the data line.

[0090] 200 . The transmitter detects the state of the data line at a first preset time. If the data line is in a high level state, execute step 210 ; otherwise, execute step 220 .

[0091] For example, according to the frame structure of the 7816 forward protocol, if the data 0x03 is sent, 0_11000000_0_1S1 will appear on the data line in sequence, where the moment when the middle symbol S of the protection bit is located is the moment 11 of the character frame. The transmitter samples the data line at this moment, determines the level, and executes the corresponding steps.

[0092] 210. If the data line is in a high level state, the receiver receives correctly and is ready to send the next character frame at a third preset time.

[0093] For example, if the data to be sent is 0x01, 0x02, 0x03, etc., the transmitter detects that the data line is at a high level at the 11th moment of the frame structure of sending data 0x01, then the data 0x02 will be sent at the 12th moment.

[0094] 220. If the data line is in a low level state, the receiver receives incorrectly and the transmitter resends the character frame until the receiver receives correctly or the transmitter repeats sending more times than the preset upper limit.

[0095] For example, if the data to be sent is 0x01, 0x02, 0x03, etc., and the transmitter detects that the data line is low at the 11th moment of the frame structure of sending data 0x01, then the data 0x01 will be resent at the 13th moment. If the preset upper limit of the number of repeated transmissions is 4, and the receiver keeps receiving errors, the data actually sent by the transmitter is 0x01, 0x01, 0x01, 0x01, 0x02, 0x03, etc.

[0096] 230. The receiver continues to monitor the data line until it detects that the data line is at a low level and starts receiving the next character frame.

[0097] It should be understood that Figure 3-4 As shown, this application is applicable to the T=0 and T=1 protocols in the ISO7816 protocol. Taking the T=0 protocol as an example, the ISO7816 protocol stipulates that the duration of a bit on the data line is the elementary time unit (ETU). Based on the formula 1ETU is equal to the duration of F / D communication clock cycles, where F is the clock frequency conversion factor, D is the bit rate adjustment factor, and f is the frequency of the communication clock.

[0098] The character frame structure in the T=0 protocol consists of 12 ETU time periods, in which the start bit 1 is a low level, 2-9 are data bits, 10 is a check bit, and protection bits 11-12 are high levels.

[0099] Specifically, the receiver judges the check bit of the character frame received from the data line. If the check bit is wrong, it takes over the 7816 interface data line from the 10th moment, keeps the low level for 1 or 2 ETUs, and releases the data line at the 11th moment or 12th moment; if the check bit is correct, it waits to receive the next character frame structure. The transmitter detects the data line at the 11th moment. If the data line is high, it will send a new character frame structure at the 12th moment or the 0th moment. If the data line is low, it is considered that the receiver has received it wrong this time, and will resend the character frame structure at the 13th moment or the 0th moment until the receiver receives it correctly or reaches the upper limit of repeated transmission.

[0100] It should be understood that according to the traditional interface design, if the chip is configured as a transmitter and the transmission parity bit is logic 0, the transmitter will release the data line, rely on the pull-up resistor to pull the data line high to enter the protection position, and detect the data line at the 11th moment of the character frame to determine whether the receiver has received it correctly and whether it needs to resend the current frame structure. The receiver pull-up resistor is required to pull the data line high within 1 ETU time from the 10th moment to the 11th moment, otherwise the transmitter will mistakenly detect the data line that has not been pulled high at the 11th moment, and thus continuously resend the current frame structure due to wrong judgment, and cannot communicate normally.

[0101] If the chip is configured as a receiver, and detects a check bit error in the character frame, and sets the error signal to 2 ETUs, the receiver will take over the data line at the 10.5th moment of the character frame, drive the data line to a low level, and release the data line at the 12.5th moment of the character frame, and pull the data line to a high level by means of a pull-up resistor. After the transmitter detects that the data line is at a low level at the 11th moment of the character frame, it will resend the start bit of this frame structure at a low level at the 13th moment. In this case, the receiver pull-up resistor is required to pull the data line from a low level to a high level within 0.5 ETUs. Otherwise, when the transmitter resends the start bit at a low level at the 13th moment, there is no falling edge change from a high level to a low level on the data line, and the receiver cannot detect the new character frame structure, resulting in a communication error.

[0102] By formula It can be seen that the duration of one ETU is equal to the period of F / D communication clocks, and in a large number of practical applications, the F / D parameter of the initial ETU is 372, that is, the duration of one ETU is 372 communication clock cycles; the F / D parameter of the minimum ETU is 8, that is, the duration of one ETU is 8 communication clock cycles. The minimum duration required for the transmitter or receiver to change the data line from low level to high level is 0.5 ETU time, that is, 4 communication clock cycles, which cannot be achieved by the pull-up resistor in the traditional solution.

[0103] In this application, when the duration of the short-time drive is 1 communication clock cycle, it can not only achieve the effect of shortening the time of the data line level conversion, but also will not affect the communication and cause problems such as bidirectional driving. The following will take the minimum value of the F / D parameter as an example for a specific description. If the minimum value of the parameter can be met, a larger parameter will inevitably allow normal communication. The minimum value of the F / D parameter is 8, that is, the duration of 1 ETU is 8 communication clock cycles, and the duration of 0.5 ETU is 4 communication clock cycles.

[0104] When the chip is configured as a transmitter, if the check bit sent is a logical 0, and then it is about to enter the protection bit, at the 10th moment of the character frame, the transmitter continues to control the data line, drives the data line to a high level, and maintains 1 communication cycle, and then releases the data line, and the pull-up resistor continues to maintain the high level on the protection bit data line. This design realizes the conversion of the data line from a low level to a high level in a very short time, which can ensure that the low level detected by the transmitter at the 11th moment must be the low level driven by the receiver, rather than the low level that is still transitioning to the high level of the protection bit due to too slow level conversion. In this application, even if the check bit received by the receiver is wrong, and it wants to control the data line at the 10.5th moment and drive it to a low level, there will be no situation where the bidirectional drive affects the communication, because the transmitter drives the high level from the 10th moment, releases the data line after 1 communication clock, and there are still 3 communication clocks left from the 10.5th moment.

[0105] When the chip is configured as a receiver, if a check bit error is detected and the error signal is set to 2 ETU time, the interface will take over the data line at the 10.5th moment of the character frame and drive it to a low level until the 12.5th moment of the character frame, drive the data line to a high level, and maintain 1 communication clock, then release the data line, and rely on the pull-up resistor to maintain the high level on the data line until the transmitter takes over the data line at the 13th moment of the character frame and resends the current frame structure. This ensures that when the transmitter takes charge of the data line at the 13th moment of the character frame that is resent due to an error, the data line must be at a high level. Subsequently, when the transmitter sends the start bit at a low level, it also ensures that the receiver can correctly detect the falling edge of the start bit due to a sufficient high level and start receiving the new frame structure. At the same time, because the transmitter only drives 1 communication clock from the 12.5th moment of the character frame, which is less than 4 communication clocks and has not reached the 13th moment, when the transmitter resends due to an error, there will be no situation where bidirectional driving affects communication.

[0106] Figure 5 The figure is a comparison diagram of the time required to drive the data line from a low level to a high level and the time required for the pull-up resistor to pull the data line from a low level to a high level. By testing the conventional 7816 interface, the values ​​shown in the figure are obtained. The time required for the pull-up resistor to pull the data line from a low level to 3.3V is about 3.422us; the time required to drive the data line from a low level to 3.3V is about 3.778ns. Therefore, the time required for driving is extremely short, which is about one nine-hundredth of the time required for the pull-up resistor. On this basis, in order to obtain higher performance, the traditionally designed 7816 interface often welds an additional pull-up resistor element at the end of the data line. Even so, when the F / D parameter is 12, the normal communication clock frequency is only 10M. If the F / D parameter is 8, the performance is lower. The present application adopts the above-mentioned short-time drive data line design, and no external pull-up resistor element is required to achieve better performance. Even under the condition of an F / D parameter of 8, the clock frequency that can communicate normally is still as high as 60M. If the F / D parameter is larger, the performance is higher. Taking the ETU rate as the standard, the performance of the interface using the method in this application is 9 times that of the traditional design.

[0107] The embodiment of the present application provides a method for implementing short-time interface driving, which avoids the communication error caused by the failure of the data line to be pulled up to the preset level in time when the interface is configured as a transmitter or a receiver in the prior art by short-time driving the data line. At the same time, the present application enables the interface to achieve better performance, without the need for external pull-up resistor elements, and can be compatible with smaller F / D parameters, so that the performance of the interface is further improved.

[0108] Embodiment three:

[0109] Combine the following Figure 6A method for implementing a short-time interface drive provided in an embodiment of the present application is described in detail, comprising the following steps:

[0110] 310. When the transmitter detects that the value of the parity bit of the transmitted character frame is logic 0, the hardware logic unit of the transmitter sets the first output enable signal to a high level and sets the value of the first output data signal.

[0111] 320. When the transmitter detects that the first output enable signal is at a high level, it controls the data line, and the pin of the transmitter outputs a preset voltage value according to the value of the first output data signal, drives the data line from the starting position of the protection bit of the character frame to a high level and maintains the first time slice.

[0112] 330. The hardware logic unit of the transmitter sets the first output enable signal to a low level, releases the data line, and the pin of the transmitter is kept at a high level through the pull-up function, and the data line is kept at a high level, so that the receiver checks the received character frame and changes the state of the data line according to the check result.

[0113] 340. The transmitter detects the state of the data line at a first preset time. If the data line is in a high level state, execute step 350; otherwise, execute step 360.

[0114] 350. If the data line is in a high level state, the receiver receives correctly and the transmitter is ready to send the next character frame at a third preset time.

[0115] 360. If the data line is in a low level state, the receiver receives incorrectly and the transmitter resends the character frame until the receiver receives correctly or the transmitter repeats sending more times than the preset upper limit.

[0116] The embodiment of the present application provides a method for implementing short-time interface driving, which avoids the communication error caused by the failure of the data line to be pulled up to the preset level in time when the interface is configured as a transmitter or a receiver in the prior art by short-time driving the data line. At the same time, the present application enables the interface to achieve better performance, without the need for external pull-up resistor elements, and can be compatible with smaller F / D parameters, so that the performance of the interface is further improved.

[0117] Embodiment 4:

[0118] Combine the following Figure 7 A method for implementing a short-time interface drive provided in an embodiment of the present application is described in detail, comprising the following steps:

[0119] 410. When the receiver detects a falling edge on the data line, it starts receiving the character frame.

[0120] 420. The receiver checks the parity bit of the received character frame. If the check result is an error, execute step 430; otherwise, execute step 470.

[0121] 430. If the check result is an error, the hardware logic unit of the receiver sets the second output enable signal to a high level, the receiver takes over the data line from the second preset time, and sets the value of the second output data signal.

[0122] 440. When the second output enable signal is at a high level, the receiver controls the data line, and the pin of the receiver outputs a voltage according to the value of the second output data signal, driving the data line to a low level and lasting for a second time slice or a third time slice.

[0123] 450. Set the value of the second output data signal again.

[0124] 460. When the receiver detects that the second output enable signal is at a high level, it controls the data line, and the pin of the receiver outputs a preset voltage value according to the value of the second output data signal. After driving the data line to a high level for a fourth time slice, the data line is released to enable the transmitter to resend the character frame.

[0125] 470. Continue to monitor the data line at the start position of the protection bit of the received character frame until the data line is detected to be at a low level and start receiving the next character frame.

[0126] The embodiment of the present application provides a method for implementing short-time interface driving, which avoids the communication error caused by the failure of the data line to be pulled up to the preset level in time when the interface is configured as a transmitter or a receiver in the prior art by short-time driving the data line. At the same time, the present application enables the interface to achieve better performance, without the need for external pull-up resistor elements, and can be compatible with smaller F / D parameters, so that the performance of the interface is further improved.

[0127] Embodiment five:

[0128] Combine the following Figure 8 An interface short-time drive implementation device provided in an embodiment of the present application is introduced in detail. The interface short-time drive implementation device includes a first processing unit and a second processing unit.

[0129] A first processing unit, configured to, when detecting that the value of the parity check bit of the transmitted character frame is logic 0, drive the data line to a high level state from the start position of the protection bit of the character frame and maintain it for a first time slice, release the data line, and maintain the high level state of the data line through a pull-up resistor, so that the receiver checks the received character frame and changes the state of the data line according to the check result;

[0130] The second processing unit is used to detect the state of the data line at a first preset time, and determine to send the next character frame or resend the character frame according to the state of the data line.

[0131] The embodiment of the present application provides a device for realizing short-time driving of an interface, which avoids the communication error caused by the failure of the data line to be pulled up to the preset level in time when the interface is configured as a transmitter or a receiver in the prior art by driving the data line in a short time. At the same time, the present application enables the interface to achieve better performance, without the need for an external pull-up resistor element, and can be compatible with smaller F / D parameters, so that the performance of the interface is further improved.

[0132] Embodiment six:

[0133] Combine the following Fig. 9 A device for implementing short-time interface driving provided by an embodiment of the present application is introduced in detail. The device for implementing short-time interface driving includes a third processing unit and a fourth processing unit.

[0134] A third processing unit, configured to cause the receiver to start receiving a character frame when a falling edge appears on the data line;

[0135] The fourth processing unit is used for the receiver to check the parity bit of the received character frame. If the check result is an error, it takes over the data line from the second preset moment, first drives the data line to a low level state and continues for a second time slice or a third time slice, then drives the data line to a high level state and continues for a fourth time slice, and then releases the data line to enable the transmitter to resend the character frame.

[0136] The embodiment of the present application provides a device for realizing short-time driving of an interface, which avoids the communication error caused by the failure of the data line to be pulled up to the preset level in time when the interface is configured as a transmitter or a receiver in the prior art by driving the data line in a short time. At the same time, the present application enables the interface to achieve better performance, without the need for an external pull-up resistor element, and can be compatible with smaller F / D parameters, so that the performance of the interface is further improved.

[0137] The present application provides a transmitter, comprising at least a memory and a processor; wherein the processor is used to execute the interface short-time drive implementation method as described in any one of the above technical solutions; and the memory is used to store the program required for the processor to perform the operation.

[0138] The present application provides a receiver, comprising at least a memory and a processor; wherein the processor is used to execute the interface short-time drive implementation method as described in the above technical solution; and the memory is used to store the program required for the processor to perform the operation.

[0139] The present application also provides a chip system, wherein the first chip in the chip system is configured as a receiver, the second chip in the chip system is configured as a transmitter, the transmitter and the receiver perform data transmission based on the same data line, and the chip system executes the interface short-time drive implementation method described in any one of the above technical solutions.

[0140] Those skilled in the art will appreciate that each block in these structure diagrams and / or block diagrams and / or flow charts and combinations of blocks in these structure diagrams and / or block diagrams and / or flow charts can be implemented using computer program instructions. Those skilled in the art will appreciate that these computer program instructions can be provided to a general-purpose computer, a professional computer, or a processor of other programmable data processing methods to implement, thereby executing the scheme specified in the block or multiple blocks of the structure diagrams and / or block diagrams and / or flow charts disclosed in this application through the processor of the computer or other programmable data processing method.

[0141] The modules of the device of the present application may be integrated into one or deployed separately. The modules may be combined into one module or further divided into multiple sub-modules.

[0142] Those skilled in the art will appreciate that the accompanying drawings are merely schematic diagrams of a preferred embodiment, and the modules or processes in the accompanying drawings are not necessarily required for implementing the present application.

[0143] Those skilled in the art can understand that the modules in the device in the embodiment can be distributed in the device in the embodiment according to the description of the embodiment, or can be changed accordingly and located in one or more devices different from the present embodiment. The modules in the above embodiment can be combined into one module, or can be further divided into multiple sub-modules.

[0144] The above serial numbers of this application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0145] The above disclosures are only a few specific embodiments of the present application; however, the present application is not limited thereto, and any changes that can be conceived by those skilled in the art should fall within the protection scope of the present application.

Claims

1. A method for implementing short-time interface driving, characterized in that: The transmitter and the receiver perform data transmission based on the same data line, and the method includes: When the transmitter detects that the value of the parity bit of the transmitted character frame is logic 0, the transmitter drives the data line to a high level state from the protection bit start position of the character frame and maintains the high level state for a first time slice, then releases the data line and maintains the high level state of the data line through a pull-up resistor; The receiver checks the parity bit of the received character frame, and if the check result is an error, takes over the data line from the second preset time, first drives the data line to a low level state for a second time slice or a third time slice, then drives the data line to a high level state for a fourth time slice, and then releases the data line; The transmitter detects the state of the data line at a first preset time, and determines to send a next character frame or resend the character frame according to the state of the data line.

2. The method according to claim 1, characterized in that The transmitter detects the state of the data line at a first preset time, and determines to send a next character frame or resend the character frame according to the state of the data line, specifically including: The transmitter detects the data line at the first preset time; If the data line is in a high level state, the receiver receives correctly and is ready to send the next character frame at a third preset time; If the data line is in a low level state, the receiver receives the data in error, and the transmitter resends the character frame until the receiver receives the data correctly or the transmitter repeats the transmission times greater than a preset upper limit.

3. The method according to claim 1, characterized in that The method further comprises: When the transmitter detects that the value of the parity bit of the character frame is logic 1, the transmitter releases the data line from the start position of the protection bit of the character frame and maintains the high level state of the data line through a pull-up resistor.

4. The method according to claim 1, characterized in that: When the transmitter detects that the value of the parity bit of the transmitted character frame is logic 0, the data line is driven to a high level state from the protection bit start position of the character frame and maintained for a first time slice, and then the data line is released, specifically comprising: When the transmitter detects that the value of the parity bit of the transmitted character frame is logic 0, the hardware logic unit of the transmitter sets the first output enable signal to a high level and sets the value of the first output data signal. After driving the data line to a high level from the starting position of the protection bit of the character frame and maintaining it for a first time slice, the hardware logic unit of the transmitter sets the first output enable signal to a low level and releases the data line.

5. The method according to claim 1, characterized in that The receiver checks the parity bit of the received character frame, and if the check result is an error, takes over the data line from the second preset time, first drives the data line to a low level state for a second time slice or a third time slice, and then drives the data line to a high level state for a fourth time slice, and then releases the data line, specifically including: When the receiver finds that the check result of the parity check bit of the received character frame is an error, the hardware logic unit of the receiver sets the second output enable signal to be a high level, takes over the data line from the second preset moment, sets the value of the second output data signal, drives the data line to be in a low level state for a second time slice or a third time slice, sets the value of the second output data signal again, drives the data line to be in a high level state for a fourth time slice, and the hardware logic unit of the receiver sets the second output enable signal to be a low level, and releases the data line.

6. The method according to claim 4, characterized in that The transmitter drives the data line to a high level state, comprising: When the transmitter detects that the first output enable signal is at a high level, the transmitter controls the data line, and the pin of the transmitter outputs a preset voltage value according to the value of the first output data signal to drive the data line to a high level state.

7. The method according to claim 4, characterized in that The transmitter maintains a high level of the data line through a pull-up resistor, comprising: When the first output enable signal is at a low level, the transmitter releases the data line, and the pin of the transmitter is kept at a high level through a pull-up function, so that the data line is kept at a high level state.

8. The method according to claim 5, characterized in that The receiver drives the data line to a high level, comprising: When the second output enable signal is at a high level, the receiver controls the data line, and the pin of the receiver outputs a voltage according to the value of the second output data signal to drive the data line to a high level; The receiver drives the data line to a low level, comprising: When the second output enable signal is at a high level, the receiver controls the data line, and the pin of the receiver outputs a voltage according to the value of the second output data signal to drive the data line to a low level.

9. A method for implementing short-time interface driving, characterized in that: The method comprises: When the transmitter detects that the value of the parity check bit of the transmitted character frame is logic 0, the transmitter drives the data line to a high level state from the protection bit starting position of the character frame and maintains it for a first time slice, then releases the data line and maintains the high level state of the data line through a pull-up resistor, so that the receiver checks the received character frame and changes the state of the data line according to the check result; The transmitter detects the state of the data line at a first preset time, and determines to send a next character frame or resend the character frame according to the state of the data line.

10. The method according to claim 9, characterized in that The transmitter detects the state of the data line at a first preset time, and determines to send a next character frame or resend the character frame according to the state of the data line, specifically including: The transmitter detects the data line at the first preset time; If the data line is in a high level state, the receiver receives correctly, and the transmitter is ready to send the next character frame at a third preset time; If the data line is in a low level state, the receiver receives the data in error, and the transmitter resends the character frame until the receiver receives the data correctly or the transmitter repeats the transmission times greater than a preset upper limit.

11. The method according to claim 9, characterized in that The method further comprises: When the transmitter detects that the value of the parity bit of the character frame is logic 1, the transmitter releases the data line from the start position of the protection bit of the character frame and maintains the high level state of the data line through a pull-up resistor.

12. The method according to claim 9, characterized in that When the transmitter detects that the value of the parity bit of the transmitted character frame is logic 0, the data line is driven to a high level state from the protection bit start position of the character frame and maintained for a first time slice, and then the data line is released, specifically comprising: When the transmitter detects that the value of the parity bit of the transmitted character frame is logic 0, the hardware logic unit of the transmitter sets the first output enable signal to a high level and sets the value of the first output data signal. After driving the data line to a high level from the starting position of the protection bit of the character frame and maintaining it for a first time slice, the hardware logic unit of the transmitter sets the first output enable signal to a low level and releases the data line.

13. A method for implementing short-time interface driving, characterized in that: The method comprises: When a falling edge appears on the data line, the receiver starts receiving the character frame; The receiver checks the parity bit of the received character frame. If the check result is an error, it takes over the data line from the second preset moment, first drives the data line to a low level state and continues for a second time slice or a third time slice, then drives the data line to a high level state and continues for a fourth time slice, and then releases the data line to enable the transmitter to resend the character frame.

14. The method according to claim 13, characterized in that The receiver checks the parity bit of the received character frame, and if the check result is an error, takes over the data line from the second preset time, first drives the data line to a low level state for a second time slice or a third time slice, and then drives the data line to a high level state for a fourth time slice, and then releases the data line, specifically including: When the receiver finds that the check result of the parity check bit of the received character frame is an error, the hardware logic unit of the receiver sets the second output enable signal to be a high level, takes over the data line from the second preset moment, sets the value of the second output data signal, drives the data line to be in a low level state for a second time slice or a third time slice, sets the value of the second output data signal again, drives the data line to be in a high level state for a fourth time slice, and the hardware logic unit of the receiver sets the second output enable signal to be a low level, and releases the data line.

15. An interface short-time drive implementation device, characterized in that: comprising a first processing unit and a second processing unit; The first processing unit is used to detect that the value of the parity check bit of the transmitted character frame is logic 0, drive the data line to a high level state from the protection bit starting position of the character frame and maintain it for a first time slice, release the data line, and maintain the high level state of the data line through a pull-up resistor, so that the receiver checks the received character frame and changes the state of the data line according to the check result; The second processing unit is used to detect the state of the data line at a first preset time, and determine to send a next character frame or resend the character frame according to the state of the data line.

16. An interface short-time drive implementation device, characterized in that: comprising a third processing unit and a fourth processing unit; The third processing unit is used for the receiver to start receiving the character frame when a falling edge appears on the data line; The fourth processing unit is used for the receiver to check the parity bit of the received character frame. If the check result is an error, it takes over the data line from the second preset time, first drives the data line to a low level state and continues for a second time slice or a third time slice, then drives the data line to a high level state and continues for a fourth time slice, and then releases the data line to enable the transmitter to resend the character frame.

17. A transmitter, characterized in that: At least includes a memory and a processor; wherein the processor is used to execute the interface short-time drive implementation method as described in any one of claims 9 to 13; the memory is used to store the program required for the processor to perform the operation.

18. A receiver, characterized in that: At least includes a memory and a processor; wherein the processor is used to execute the interface short-time drive implementation method as described in claim 13 or 14; the memory is used to store the program required for the processor to perform the operation.

19. A chip system, characterized in that: The first chip in the chip system is configured as a receiver, the second chip in the chip system is configured as a transmitter, the transmitter and the receiver perform data transmission based on the same data line, and the chip system executes the interface short-time drive implementation method described in any one of claims 1-8.

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