Out-of-order execution computing device

Abstract

The present invention provides a computing device, including an execution circuit, a reorder queue (ROQ) circuit, and a physical register file (PRF) circuit. The ROQ circuit is used to issue a plurality of instructions to the execution circuit in an out-of-order manner. The execution circuit includes a plurality of execution units, and the ROQ circuit includes a plurality of ROQ banks, wherein these ROQ banks are respectively bound to these execution units in a one-to-one manner. Any one of these ROQ banks issues an instruction to a dedicated execution unit among these execution units. The PRF circuit is used to provide source operands to the ROQ circuit. The PRF circuit includes a plurality of PRFs, wherein these PRFs are respectively bound to these ROQ banks in a one-to-one manner, and these PRFs are respectively bound to these execution units in a one-to-one manner. Any one of these execution units writes back an execution result to a dedicated PRF among these PRFs.

Description

Technical Field

[0001] The present invention relates to an electronic device, and more particularly to a computing device with out-of-order execution. Background Art

[0002] Generally, the execution of multiple instructions in a program is in order. For example, after a previous calculation instruction generates a calculation result, a store instruction can store the calculation result of the processor in memory, and then a load instruction can extract the calculation result from memory to the processor for use by the next calculation instruction. During the execution of a computing program by a processor, the processor may be idle for some reason waiting for the next instruction. To improve the performance of the processor, out-of-order execution (OoOE or OOE for short) technology has been applied in the field of calculator engineering. In out-of-order execution technology, the order in which the processor executes instructions is determined by the availability of input data, rather than by the original order of the computing program. Out-of-order execution can avoid the idling / delay caused by the processor waiting for the next instruction, and thus can avoid specific types of latency consumption.

[0003] A superscalar Central Processing Unit (CPU) architecture can be implemented in a processor to execute multiple instructions in parallel. The superscalar architecture refers to a circuit architecture that implements instruction-level parallelism in a single processor core. K-wide superscalar means that the processor core can process K instructions at a time (i.e., has the ability to issue K instructions simultaneously). To execute instructions out of order and restore the order of the execution results of out-of-order executed instructions to the original order of the computation program, a reorder queue (ROQ) circuit is configured inside the processor. The ROQ circuit can issue K instructions at a time. Different functional execution units are configured inside the processor to facilitate the simultaneous processing of multiple different types of instructions issued by the ROQ circuit. To save execution units, in existing processor cores, the number of execution units does not match (is not equal to) the K width (the number of simultaneously issued instructions K). Depending on the currently issued instruction quantity and type, some or all of these execution units will be dynamically allocated to the ROQ circuit to process the instructions issued by the ROQ circuit. That is to say, the mapping relationship between the multiple reorder queue banks of the ROQ circuit and these execution units is not fixed. To achieve the dynamic allocation (dynamic mapping) of these execution units, complex circuits such as a dispatch queue, a schedule queue, and a cross-bar (XBAR) circuit are configured between the ROQ circuit and these execution units.

[0004] The XBAR circuit can solve the problem of inconsistent input and output bandwidths of each level of circuit in the pipeline of existing processor cores, but the XBAR circuit is not conducive to performance and cost. Moreover, on the path from the ROQ circuit to the execution unit, it is necessary to selectively copy some ROQ instructions to the dispatch queue and copy ROQ instructions from the dispatch queue to the schedule queue. Obviously, the operations of the dispatch queue and the schedule queue also degrade performance and increase cost. In addition, to save execution units, the number of each type of execution unit is limited, resulting in a disorderly number of schedule queues. Often, the number of instructions issued by the ROQ circuit per cycle does not match the number of execution units, causing some types of execution units to be overloaded while some types of execution units are idle, resulting in poor hardware utilization efficiency. In addition, the number of ROQ circuits and physical register files (PRFs) usually does not match, so that the mapping relationship between the ROQ circuit and the PRF is not fixed, resulting in dynamic mapping logic overhead. How to make the processor core efficiently process / execute instructions is one of the many technical issues in this field. Summary of the Invention

[0005] The present invention provides a computing device for efficiently processing / executing instructions.

[0006] In an embodiment according to the present invention, the computing device includes an execution circuit, a reorder queue (ROQ) circuit, and a physical register file (PRF) circuit. The reorder queue circuit is coupled to the execution circuit. The reorder queue circuit is configured to issue multiple instructions to the execution circuit in an out-of-order manner. The execution circuit includes multiple execution units, and the reorder queue circuit includes multiple reorder queue banks, wherein the multiple reorder queue banks are respectively bound to the multiple execution units in a one-to-one manner. Any one of the multiple reorder queue banks issues an instruction to a dedicated execution unit among the multiple execution units. The physical register file circuit is coupled to the execution circuit and the reorder queue circuit. The physical register file circuit is configured to provide source operands to the reorder queue circuit. The physical register file circuit includes multiple physical register files, wherein the multiple physical register files are respectively bound to the multiple reorder queue banks in a one-to-one manner, and the multiple physical register files are respectively bound to the multiple execution units in a one-to-one manner. Any one of the multiple execution units writes an execution result back to a dedicated physical register file among the multiple physical register files.

[0007] Based on the above, in the computing device, the multiple reorder queue banks of the reorder queue circuit are respectively bound to the multiple execution units of the execution circuit in a one-to-one manner. That is, the mapping relationship between the reorder queue bank and the execution unit is fixed. Therefore, there is no need to configure complex circuits such as a dispatch queue, a schedule queue, and a cross-bar (XBAR) circuit between these reorder queue banks and these execution units. Instructions can be directly sent from these reorder queue banks to their respective dedicated execution units. In addition, the multiple physical register files of the physical register file circuit are respectively bound to the multiple execution units of the execution circuit in a one-to-one manner. That is, the mapping relationship between the physical register file and the execution unit is fixed. Therefore, there is no need to configure a complex circuit such as a cross-bar (XBAR) circuit between these physical register files and these execution units. Any one of the execution units can directly write the execution result back to its respective dedicated physical register file. Therefore, the computing device can reduce the pipeline depth and thus efficiently process / executing instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a circuit block of a computing device according to an embodiment of the present invention.

[0009] Figure 2 It is a schematic circuit diagram of an arithmetic core shown according to an embodiment of the present invention.

[0010] Figure 3 It is a schematic circuit diagram of an instruction fetch and decode circuit, an ROQ circuit, an execution circuit, and a PRF circuit shown according to an embodiment of the present invention.

[0011] Figure 4 A data flow diagram of a general physical register file (PRF-U) shown according to an embodiment of the present invention.

[0012] Description of reference numerals

[0013] 100: Computing device

[0014] 110: Memory

[0015] 120: Arithmetic core

[0016] 121: Instruction fetch and decode circuit

[0017] 122: Reorder queue (ROQ) circuit

[0018] 123: Execution circuit

[0019] 124: Physical register file (PRF) circuit

[0020] 125: Load store queue (LSQ) circuit

[0021] EXE_1, EXE_2, EXE_K: Execution units

[0022] F&D_1, F&D_2, F&D_K: Instruction fetch and decoders

[0023] RF_1, RF_2, RF_K: Physical register file (PRF)

[0024] ROQ_1, ROQ_2, ROQ_K: Reorder queue (ROQ) banks

[0025] SLICE_1, SLICE_2, …, SLICE_K: Execution slices Detailed implementation manners

[0026] Now, reference will be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the drawings. Whenever possible, the same component symbols are used in the drawings and the description to represent the same or similar parts.

[0027] As used throughout the specification (including the claims) of this case, the term "coupled (or connected)" can refer to any direct or indirect connection means. For example, if it is described in the text that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or certain connection means. The terms "first", "second", etc. mentioned throughout the specification (including the claims) of this case are used to name elements, rather than to limit the upper or lower limit of the number of elements, nor to limit the order of the elements. Additionally, wherever possible, components / structures / steps with the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / structures / steps with the same reference numerals or the same terms used in different embodiments can be referred to each other for relevant descriptions.

[0028] Figure 1 is a schematic diagram of a circuit block of a computing device 100 according to an embodiment of the present invention. Figure 1 The illustrated computing device 100 includes a memory 110 and an arithmetic core 120. The memory 110 is used to store computing programs, operands, and other data. The present embodiment does not limit the specific data structures of the operands / data. For example, in the application of neural networks, the operands can be vectors, matrices, tensors, or other data. The arithmetic core 120 is coupled to the memory 110. In different application examples, the arithmetic core 120 includes tensor cores, general matrix multiply (GEMM) cores, arithmetic logic units (ALUs), and / or other arithmetic units. According to different design requirements, in some embodiments, the above arithmetic core 120 can be implemented as a hardware circuit. In other embodiments, the arithmetic core 120 can be implemented as firmware, software (i.e., programs), or a combination of the foregoing two. In still other embodiments, the arithmetic core 120 can be implemented as a combination of multiple of hardware, firmware, and software.

[0029] In terms of hardware, the above-mentioned arithmetic core 120 can be implemented as logic circuits on an integrated circuit. For example, the related functions of the arithmetic core 120 can be implemented in various logic blocks, modules, and circuits of one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), and / or other processing units. The related functions of the arithmetic core 120 can be implemented as hardware circuits, such as various logic blocks, modules, and circuits in an integrated circuit, using hardware description languages (such as Verilog HDL or VHDL) or other suitable programming languages.

[0030] In terms of software form and / or firmware form, the related functions of the above-mentioned arithmetic core 120 can be implemented as programming codes. For example, the arithmetic core 120 is implemented using general programming languages (such as C, C++ or assembly language) or other suitable programming languages. The programming codes can be recorded / stored in a non-transitory machine-readable storage medium. In some embodiments, the machine-readable storage medium includes, for example, semiconductor memory and / or a storage device. The semiconductor memory includes a memory card, a read-only memory (ROM), a flash memory, a programmable logic circuit or other semiconductor memory. The storage device includes a tape, a disk, a hard disk drive (HDD), a solid-state drive (SSD) or other storage devices. An electronic device (such as a computer, a central processing unit (CPU), a controller, a microcontroller or a microprocessor) can read and execute the programming codes from the machine-readable storage medium to implement the related functions of the arithmetic core 120. Alternatively, the programming codes can be provided to the electronic device via any transmission medium (such as a communication network or a broadcast wave, etc.). The communication network is, for example, the Internet, a wired communication network, a wireless communication network or other communication media.

[0031] The arithmetic core 120 simplifies the correspondence between the reorder queue (ROQ) and the physical register file (PRF). In the arithmetic core 120, the correspondence between the ROQ and the PRF is statically bound. Therefore, complex circuits such as a dispatch queue, a schedule queue, and a cross-bar (XBAR) circuit do not need to be configured between the ROQ and the PRF, thereby reducing the pipeline depth and improving the PRF usage efficiency. In addition, in the arithmetic core 120, the correspondence between the execution unit and the PRF is statically bound. Therefore, complex circuits such as a cross-bar (XBAR) circuit do not need to be configured between these reorder queue libraries and these execution units. Any execution unit can directly write the execution result back to its respective dedicated PRF. Therefore, the computing device can reduce the pipeline depth and thus efficiently process / execute instructions. The following will use Figure 2 and Figure 3 to illustrate one of the many implementation examples of the arithmetic core 120. The implementation of the arithmetic core 120 is not limited to Figure 2 and Figure 3 the illustrated embodiments.

[0032] Figure 2 is a schematic block diagram of an arithmetic core 120 illustrated according to an embodiment of the present invention. Figure 2 The illustrated memory 110 and the arithmetic core 120 may refer to Figure 1 the related descriptions of the illustrated memory 110 and the arithmetic core 120, and thus will not be elaborated herein. In Figure 2 the illustrated embodiment, the arithmetic core 120 includes an instruction fetch and decode circuit 121, a reorder queue (ROQ) circuit 122, an execution circuit 123, a physical register file (PRF) circuit 124, and a load-store queue (LSQ) circuit 125. The instruction fetch and decode circuit 121 can fetch a plurality of original instructions from the memory 110 and decode the plurality of original instructions to generate a plurality of instructions for the ROQ circuit 122. The ROQ circuit 122 is coupled to the instruction fetch and decode circuit 121 to receive the plurality of instructions.

[0033] Based on the instructions, the LSQ circuit 125 can selectively load the source operand from the memory 110 into the PRF circuit 124. The PRF circuit 124 is coupled to the ROQ circuit 122. The PRF circuit 124 can selectively provide one or more source operands to the ROQ circuit 122. The ROQ circuit 122 is coupled to the execution circuit 123. The ROQ circuit 122 can issue multiple instructions to the execution circuit 123 in an out-of-order manner. Based on the instructions, the ROQ circuit 122 can provide the source operands of the instructions to the execution circuit 123 together. The PRF circuit 124 is coupled to the execution circuit 123. The execution circuit 123 processes / executes the instructions issued by the ROQ circuit 122 and then writes the execution results back to the PRF circuit 124. The LSQ circuit 125 can store the execution results from the PRF circuit 124 into the memory 110.

[0034] Figure 3 is a schematic block diagram of the instruction fetch and decode circuit 121, the ROQ circuit 122, the execution circuit 123, and the PRF circuit 124, as shown in an embodiment of the present invention. In Figure 3 the illustrated embodiment, the instruction fetch and decode circuit 121 includes a plurality of instruction fetch and decoders, such as Figure 3 the illustrated instruction fetch and decoders F&D_1, F&D_2, …, F&D_K. The number K of the instruction fetch and decoders F&D_1 to F&D_K can be any integer according to the actual design. In the case where the arithmetic core 120 is a K-wide superscalar architecture, the number K can be the number of instructions that can be issued in one clock cycle. The ROQ circuit 122 includes a plurality of reorder queues (ROQ) banks, such as Figure 3 the illustrated ROQ banks ROQ_1, ROQ_2, …, ROQ_K. The PRF circuit 124 includes a plurality of physical register files (PRF), such as Figure 3 the illustrated PRF RF_1, RF_2, …, RF_K. The execution circuit 123 includes a plurality of execution units, such as Figure 3 the illustrated execution units EXE_1, EXE_2, …, EXE_K.

[0035] According to the actual design, each of these execution units EXE_1 to EXE_K includes one or more of a branch unit (BRU), an arithmetic logic unit (ALU), an address generation unit (AGU), a load-store unit (LSU), a multiplication and division unit (MDU), and a floating-point and vector unit (FVU). The BRU can process process control flow type instructions. The BRU is a functional unit responsible for processing process control flow type instructions, responsible for calculating the target address, checking the correctness of branch prediction, and also responsible for starting the recovery mechanism in case of prediction failure. The ALU can process arithmetic logic type instructions. The ALU is responsible for performing arithmetic logic calculations on integer type data, including addition, subtraction, logic, shift, and simple multiplication and division. The AGU can calculate the virtual address for accessing the memory. The LSU can process load-store type instructions. The MDU can process multiplication and division type instructions. The FVU can process floating-point type instructions and vector type instructions. For example, in some embodiments, each of these execution units EXE_1 to EXE_K includes a BRU, an ALU, and an AGU.

[0036] In Figure 3 In the illustrated embodiment, these instruction fetch and decoders F&D_1 to F&D_K are respectively bound to these ROQ libraries ROQ_1 to ROQ_K in a one-to-one manner. Therefore, any one of these instruction fetch and decoders F&D_1 to F&D_K can generate an instruction to an exclusive queue library in these ROQ libraries ROQ_1 to ROQ_K. These PRFs RF_1 to RF_K are respectively bound to these ROQ libraries ROQ_1 to ROQ_K in a one-to-one manner. These ROQ libraries ROQ_1 to ROQ_K are respectively bound to these execution units EXE_1 to EXE_K in a one-to-one manner. Therefore, any one of these ROQ libraries ROQ_1 to ROQ_K can issue an instruction to an exclusive execution unit in these execution units EXE_1 to EXE_K. These PRFs RF_1 to RF_K are respectively bound to these execution units EXE_1 to EXE_K in a one-to-one manner. Therefore, any one of these execution units EXE_1 to EXE_K can write the execution result back to an exclusive PRF in these PRFs RF_1 to RF_K.

[0037] For the K-issue design, the pipeline of the operation core 120 will have K execution slices SLICE_1, SLICE_2,..., SLICE_K. For example, in Figure 3In the illustrated execution slice SLICE_1, the instruction fetch and decoder F&D_1 can generate instructions for the ROQ library ROQ_1 (the exclusive queue library of the instruction fetch and decoder F&D_1). Based on the instructions, the ROQ library ROQ_1 can selectively obtain one or more source operands from these ROQ libraries ROQ_1 to ROQ_K. The ROQ library ROQ_1 can issue instructions to the execution unit EXE_1 (the exclusive execution unit of the ROQ library ROQ_1) and provide the source operands of the instructions to the execution unit EXE_1. The execution unit EXE_1 can process / execute the instructions issued by the ROQ library ROQ_1 and directly write the execution result back to the PRF RF_1 (the exclusive PRF of the execution unit EXE_1) without going through the XBAR. Other execution slices SLICE_2 to SLICE_K can refer to the relevant description of the execution slice SLICE_1 and be analogized, so they will not be elaborated here. Taking the execution slice as a unit, any instruction that meets the emission conditions within each execution slice can be out-of-order directly sent to the private execution unit within the same execution slice, and there is no XBAR between the ROQ library and the execution unit within the same execution slice.

[0038] Figure 4 As shown in an embodiment of the present invention, a data flow diagram of the physical register file PRF_U. Figure 4 The illustrated embodiment has 256 ROQ libraries, for example Figure 4 The ROQ libraries from "0" to "255" in the left column shown. Figure 4 The illustrated ROQ libraries "0" to "255" can refer to Figure 3 The relevant description of the illustrated ROQ libraries ROQ_1 to ROQ_K and be analogized, so they will not be elaborated here. Figure 4 The illustrated embodiment has 256 general physical register files (unify PRF, PRF-U), for example Figure 4 The PRF-U from "0" to "255" in the middle column shown. Figure 4 The illustrated PRF-U "0" to "255" can refer to Figure 3 The relevant description of the illustrated PRF RF_1 to RF_K and be analogized, so they will not be elaborated here. These PRF-U "0" to "255" are respectively bound to these ROQ libraries "0" to "255" in a one-to-one manner. That is, the mapping relationship between these ROQ libraries "0" to "255" and these PRF-U "0" to "255" is fixed. Therefore, there is no need to configure complex circuits such as cross-switching (XBAR) circuits between these ROQ libraries "0" to "255" and these PRF-U "0" to "255".

[0039] After the execution unit writes the execution result back to PRF-U, based on the information of ROQ, the execution results of these PRF-U from "0" to "255" can be transmitted to the corresponding architecture register file (ARF). The Instruction Set Architecture (ISA) clearly defines the ARF, so it will not be elaborated here. In Figure 4 In the illustrated embodiment, the ARF includes an architecture register file for integers (ARF-I) and an architecture register file for floating-point numbers (ARF-F). For example, the execution result of PRF-U "5" is transmitted to ARF-F "2", the execution result of PRF-U "6" is transmitted to ARF-I "4", the execution result of PRF-U "7" is transmitted to ARF-F "31", and the execution result of PRF-U "8" is transmitted to ARF-I "1".

[0040] In summary, in the computing device 100, multiple ROQ libraries ROQ_1 to ROQ_K of the reorder queue (ROQ) circuit 122 are respectively bound to multiple execution units EXE_1 to EXE_K of the execution circuit 123 in a one-to-one manner. That is, the mapping relationship between the ROQ libraries ROQ_1 to ROQ_K and the execution units EXE_1 to EXE_K is fixed. Therefore, complex circuits such as a scheduling queue, a scheduling queue, and a crossbar (XBAR) circuit do not need to be configured between these ROQ libraries ROQ_1 to ROQ_K and these execution units EXE_1 to EXE_K. Instructions can be directly sent from these ROQ libraries ROQ_1 to ROQ_K to their respective dedicated execution units. In addition, multiple physical register files RF_1, RF_2,..., RF_K of the physical register file (PRF) circuit 124 are respectively bound to multiple execution units EXE_1 to EXE_K of the execution circuit 123 in a one-to-one manner. That is, the mapping relationship between the physical register files RF_1, RF_2,..., RF_K and the execution units EXE_1 to EXE_K is fixed. Therefore, complex circuits such as an XBAR circuit do not need to be configured between these physical register files RF_1, RF_2,..., RF_K and these execution units EXE_1 to EXE_K. Any execution unit can directly write the execution result back to its respective dedicated PRF. Therefore, the computing device 100 can reduce the pipeline depth and thus efficiently process / execute instructions.

[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A computing device, characterized in that, The computing device includes: An execution circuit including a plurality of execution units; A reorder queue circuit coupled to the execution circuit for issuing a plurality of instructions to the execution circuit in an out-of-order manner, wherein the reorder queue circuit includes a plurality of reorder queue banks, the plurality of reorder queue banks are respectively bound to the plurality of execution units in a one-to-one manner, and any one of the plurality of reorder queue banks issues an instruction to a dedicated execution unit among the plurality of execution units; and A physical register file circuit coupled to the execution circuit and the reorder queue circuit for providing source operands to the reorder queue circuit, wherein the physical register file circuit includes a plurality of physical register files, the plurality of physical register files are respectively bound to the plurality of reorder queue banks in a one-to-one manner, the plurality of physical register files are respectively bound to the plurality of execution units in a one-to-one manner, and any one of the plurality of execution units writes an execution result back to a dedicated physical register file among the plurality of physical register files.

2. The computing device according to claim 1, wherein The computing device further includes: An instruction fetch and decode circuit for fetching a plurality of original instructions from a memory and decoding the plurality of original instructions to generate the plurality of instructions for the reorder queue circuit.

3. The computing device according to claim 2, wherein The instruction fetch and decode circuit includes: A plurality of instruction fetch and decoders respectively bound to the plurality of reorder queue banks in a one-to-one manner, wherein any one of the plurality of instruction fetch and decoders generates an instruction for a dedicated queue bank among the plurality of reorder queue banks.

4. The computing device according to claim 1, wherein Each of the plurality of execution units includes: A branch unit for processing process control flow type instructions.

5. The computing device according to claim 4, wherein The branch unit is used for calculating a target address and checking the correctness of branch prediction.

6. The computing device according to claim 1, wherein Each of the plurality of execution units includes: An arithmetic logic unit for processing arithmetic logic type instructions.

7. The computing device according to claim 6, wherein The arithmetic logic unit is used for performing arithmetic logic calculations on integer type data.

8. The computing device according to claim 7, wherein The arithmetic logic calculations include addition, subtraction, logic, shift, and simple multiplication and division.

9. The computing device according to claim 1, wherein Each of the plurality of execution units includes: An address generation unit for calculating a virtual address for accessing a memory.

10. The computing device according to claim 1, wherein Each of the plurality of execution units includes: A load store unit for processing load store type instructions.

11. The computing device according to claim 1, wherein Each of the plurality of execution units includes: A multiplication and division unit for processing multiplication and division type instructions.

12. The computing device according to claim 1, wherein Each of the plurality of execution units includes: A floating point and vector unit for processing floating point type instructions and vector type instructions.

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