Method, device and storage medium for implementing a user-defined primitive of sequential logic

Abstract

The present disclosure provides a method, device and storage medium for implementing a user-defined primitive of a sequential logic. The method comprises: receiving a description of the user-defined primitive, the description comprising at least a first input, a second input and an output associated with the first input and the second input; generating a first truth table and a second truth table corresponding to the first input and the second input respectively according to the description, wherein the first truth table comprises a first previous input value and a previous output value of the first input and the second input and the output at a previous time, and a first current input value of the first input at a current time; determining a first element value in the first truth table corresponding to the first previous input value, the previous output value and the first current input value; and determining a current output value of the output of the user-defined primitive at the current time in the first truth table based on the first element value.

Description

Technical Field

[0001] This disclosure relates to the field of computer software, and more particularly to a method, apparatus and storage medium for implementing user-defined primitives of sequential logic. Background Technology

[0002] Verilog includes many basic circuit elements, such as AND, OR, and XOR. However, in practice, users sometimes need to build modules with specific functions, which can be very complex to describe using only these built-in elements. Therefore, Verilog also provides users with the ability to write their own primitives, known as User-Defined Primitives (UDPs).

[0003] UDP includes combinational logic UDP and sequential logic UDP. Among them, the current output value of sequential logic UDP depends not only on the current input value, but also on the current internal state (i.e., the previous output value).

[0004] UDP implementations typically retrieve output by looking up a truth table. Taking an edge-triggered sequential logic UDP as an example, its possible input states include nine possibilities (00, 01, 0x, 10, 11, 1x, x0, x1, xx, i.e., from 0 to 0, from 0 to 1, from 0 to x, etc.). Therefore, for an edge-triggered sequential logic UDP with input N, its truth table contains nine elements. N *3, where 3 indicates that the previous output value may have three states (0, 1, x). Traditional truth table schemes for sequential logic UDPs incur huge storage overhead. Summary of the Invention

[0005] In view of this, this disclosure proposes a method, device and storage medium for implementing user-defined primitives of sequential logic.

[0006] In a first aspect, this disclosure provides a method for implementing a user-defined primitive of sequential logic, comprising: receiving a description of the user-defined primitive, the description including at least a first input, a second input, and an output associated with the first input and the second input; generating a first truth table and a second truth table corresponding to the first input and the second input respectively, based on the description of the user-defined primitive, wherein the first truth table includes a first prior input value, a second prior input value, and a prior output value of the first input, the second input, and the output at a previous time step, and a first current input value of the first input at the current time step; determining a first element value in the first truth table corresponding to the first prior input value, the second prior input value, the prior output value, and the first current input value; and determining, based on the first element value, the current output value of the output of the user-defined primitive at the current time step in the first truth table.

[0007] A second aspect of this disclosure provides an electronic device for implementing user-defined primitives of sequential logic, comprising: a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions such that the electronic device performs the method as described in the first aspect.

[0008] A third aspect of this disclosure provides a non-transitory computer-readable storage medium that stores a set of instructions for an electronic device, the set of instructions being used to cause the electronic device to perform the method as described in the first aspect.

[0009] This disclosure provides a method, device, and storage medium for implementing user-defined primitives for sequential logic. By generating a corresponding truth table for each UDP input, the number of elements in the truth table is effectively reduced, thereby lowering the storage space occupied by the truth table. During simulation, the simulation tool can read the stored truth table more quickly, improving the implementation efficiency of UDP. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only for this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1A A schematic diagram of the structure of an exemplary electronic device according to an embodiment of the present disclosure is shown.

[0012] Figure 1B A schematic diagram of an exemplary simulation tool according to an embodiment of the present disclosure is shown.

[0013] Figure 2A A schematic diagram illustrating the description of exemplary timing logic user-defined primitives according to embodiments of the present disclosure is shown.

[0014] Figure 2B A schematic diagram of an exemplary conventional truth table according to an embodiment of the present disclosure is shown.

[0015] Figure 2C A schematic diagram of an exemplary first truth table corresponding to a first input is shown according to an embodiment of the present disclosure.

[0016] Figure 3 A flowchart illustrating an exemplary method for implementing user-defined primitives of timing logic according to embodiments of this disclosure is shown. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0018] It should be noted that, unless otherwise defined, the technical or scientific terms used in this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0019] As mentioned above, the truth table of a traditional user-defined temporal logic primitive (UDP) has as many as 9 elements. N *3. The more elements there are, the larger the storage space occupied by the truth table. Therefore, the traditional truth table scheme for sequential logic UDP will cause a huge overhead in storage space.

[0020] In view of the above problems, this disclosure provides a method, device and storage medium for implementing user-defined primitives of sequential logic. By generating a corresponding truth table for each input, the number of elements in the truth table is effectively reduced, thereby reducing the storage space occupied by the truth table.

[0021] Figure 1A A schematic diagram of the structure of an exemplary electronic device 100 according to an embodiment of the present disclosure is shown.

[0022] Electronic device 100 may be, for example, a host computer. Electronic device 100 may include: processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110. The processor 102, memory 104, network interface 106, and peripheral interface 108 can communicate with each other within electronic device 100 via bus 110.

[0023] Processor 102 may be a central processing unit (CPU), image processor, neural network processor, microcontroller, programmable logic device, digital signal processor, application-specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 can be used to perform functions related to the techniques described in this disclosure. In some embodiments, processor 102 may also include multiple processors integrated as a single logic component. Figure 1A As shown, processor 102 may include multiple processors 102a, 102b and 102c.

[0024] Memory 104 can be configured to store data (e.g., instruction sets, computer code, intermediate data, truth tables, etc.). For example, Figure 1A As shown, the stored data may include program instructions (e.g., program instructions for implementing the techniques of this disclosure) and truth tables. The processor 102 may also access the stored program instructions and truth tables, and execute the program instructions to generate or read the truth tables. The memory 104 may include a non-transitory computer-readable storage medium, such as a volatile or non-volatile storage device. In some embodiments, the memory 104 may include random access memory (RAM), read-only memory (ROM), optical disk, magnetic disk, hard disk, solid-state drive (SSD), flash memory, memory stick, etc.

[0025] Network interface 106 can be configured to enable electronic device 100 to communicate with one or more other external devices via a network. The network can be any wired or wireless network capable of transmitting and / or receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, Near Field Communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It is understood that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.

[0026] The peripheral interface 108 can be configured to connect the electronic device 100 to one or more peripheral devices to enable information input and output. For example, peripheral devices may include input devices such as keyboards, mice, touchpads, touch screens, microphones, and various sensors, as well as output devices such as displays, speakers, vibrators, and indicator lights.

[0027] Bus 110 can be configured to transmit information between various components of electronic device 100 (e.g., processor 102, memory 104, network interface 106, and peripheral interface 108), and can be, for example, an internal bus (e.g., processor-memory bus), an external bus (USB port, PCI-E bus), etc.

[0028] In some embodiments, except Figure 1A In addition to the processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110 shown and described above, the electronic device 100 may also include one or more other components necessary for normal operation and / or one or more other components essential for implementing the solutions of the embodiments of this disclosure. In some embodiments, the electronic device 100 may not include Figure 1A One or more components as shown.

[0029] It should be noted that although the above-described electronic device 100 architecture only shows the processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110, in specific implementations, the architecture of the electronic device 100 may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described electronic device 100 architecture may only include the components necessary for implementing the embodiments of this disclosure, and does not necessarily include all the components shown in the figures.

[0030] Figure 1B A schematic diagram of an exemplary simulation tool 120 according to an embodiment of the present disclosure is shown. The simulation tool 120 may be a computer program running on an electronic device 100.

[0031] In the field of chip design, simulation tools are typically used to simulate a design. One example of such a tool is GalaxSim, produced by Chipown Technology Co., Ltd. Figure 1BThe exemplary simulation tool 120 shown may include a compiler 122 and a simulator 124. The compiler 122 may receive source code 121 (e.g., a hardware description language such as VHDL, Verilog, SystemVerilog, etc.) and compile it into executable code 123 (e.g., machine code, assembly code, software code, truth tables, etc.). The simulator 124 may perform simulation based on the executable code 123 and output the simulation result 125. For example, the simulation tool 120 may transmit the simulation result 125 via... Figure 1A The peripheral interface 108 outputs to an output device (e.g., displayed on a monitor).

[0032] In some embodiments, when it is necessary to build a module with specific functions in the source code 121 written in Verilog, the user can write UDP himself to meet the functional requirements.

[0033] For ease of description, this disclosure uses a two-input sequential logic UDP as an example.

[0034] Figure 2A A schematic diagram of a description 200 of exemplary timing logic user-defined primitives according to an embodiment of this disclosure is shown. Description 200 may include a UDP state table. The UDP state table may be user-defined and represents UDP output values ​​obtained based on the input state and the current state of UDP.

[0035] like Figure 2A As shown, description 200 may include at least the first input i1, the second input i2, the output value q of the previous time step, and the current output q+ associated with the first input i1, the second input i2, and the output value q of the previous time step. It is understood that description 200 may include more than two inputs. From description 200, it can be seen that when the first input i1 transitions from 0 in the previous time step to 1 in the current time step (i.e., the first input i1 is a rising edge), the second input i2 is 0, and the output value q of the previous time step is 1, the current output q+ of the UDP is 0; when the first input i1 is a rising edge and the second input i2 is 1, regardless of the output value q of the previous time step, the current output q+ of the UDP is 1.

[0036] UDP implementations typically obtain output by looking up a truth table.

[0037] Figure 2B A schematic diagram of an exemplary conventional truth table 210 according to an embodiment of the present disclosure is shown. For a two-input sequential logic UDP (i.e., input N=2), the number of elements in a conventional truth table scheme is 243.

[0038] In some embodiments, the simulation tool 120 may be based on, for example... Figure 2A The description 200 shows the generation of a first truth table corresponding to the first input i1 and a second truth table corresponding to the second input i2.

[0039] Figure 2C A schematic diagram of an exemplary first truth table 220 corresponding to the first input i1 is shown according to an embodiment of the present disclosure.

[0040] like Figure 2C As shown, the first truth table 220 may include the previous input value I1 of the first input i1 of UDP at the previous time step, the previous input value I2 of the second input i2 at the previous time step, the previous output value q of UDP at the previous time step, and the current input value I1+ of the first input i1 at the current time step. The previous input values ​​I1, I2, and the previous output value q can all be (0, 1, x), so the first truth table 220 has 3... 3 =27 possible states, that is, the first truth table 220 can have 27 rows. The current input value I1+ of UDP can be (0,1,x,z). Simulation tool 120 can be based on Figure 2A The description 200 shows the element values ​​in the first truth table 220 that correspond to the previous input values ​​I1, I2, previous output q, and current input I1+.

[0041] Taking I1 = x, I2 = x, q = x, and I1+ = 0 as an example, the first input i1 is (x0), the second input i2 is x, and the first output q is x. Returning to... Figure 2A As shown in description 200, this state is undefined, so the current output q+ is x (i.e., unknown). The user can define the value of output x as 3. Therefore, the current output value of UDP at this time is x = 3.

[0042] To facilitate users in finding the UDP output value after input changes, the first truth table 220 may also include element positions (as shown in the first column of the first truth table 220). Element positions are identified starting from 0. In some embodiments, since the current input value I1+ of the first input i1 at the current moment can be one of the four states (0, 1, x, z), the value of the element position in each row is the value of the element position in the previous row plus 4. The values ​​of the element positions in the first truth table 220 can be 0, 4, 8, ..., 104, for a total of 27 values.

[0043] Simulation tool 120 can replace I1 with I1+ and q with q+ to find the row at element position 36 in the first truth table 220 where I1 = 0, I2 = x, and q = x. Based on the value 36 at this element position and the previously obtained current output value 3, simulation tool 120 can calculate the element value corresponding to I1 = x, I2 = x, q = x, and I1+ = 0. In some embodiments, simulation tool 120 can use the sum of the value 36 at the element position and the current output value 3 as the element value. Figure 2C As shown, the element value corresponding to I1=x, I2=x, q=x, I1+=0 is 36+3=39.

[0044] Similarly, for I1 = x, I2 = x, q = x, I1+ = 1, the simulation tool 120 can repeat the aforementioned steps to obtain the current output q+ as x (i.e., 3) from description 200; and find the row in the first truth table 220 where I1 = 1, I2 = x, q = x is at element position 72. Therefore, the element value corresponding to I1 = x, I2 = x, q = x, I1+ = 1 is 72 + 3 = 75. This process continues until the simulation tool 120 obtains all element values ​​in the first truth table 220.

[0045] Similarly, the simulation tool 120 can use the same method as generating the first truth table 220 to generate the second truth table corresponding to the second input i2, which will not be elaborated here.

[0046] After the aforementioned steps, the simulation tool 120 has generated a first truth table 220 corresponding to the first input i1 and a second truth table corresponding to the second input i2. During the simulation, when the UDP receives a new first input or a new second input, the simulation tool 120 can directly obtain the current output value of the UDP by looking up the generated first truth table 220 or second truth table.

[0047] Taking the UDP receiving a new first input i1 as an example, for instance, I1 = x, I2 = x, q = x, I1+ = 0, at this time, the first input i1 changes from the previous input x to the current input 0.

[0048] In some embodiments, the simulation tool 120 can find the corresponding element value 39 in the first truth table 220. The element value 39 is stored in the computer as binary data (100111). Based on the element value 39, the simulation tool 120 can obtain the lower two bits (11) of the element value 39 stored in the computer to obtain the current output value 3 of UDP.

[0049] In other embodiments, the simulation tool 120 can acquire the high-order data (100100) of element 39, excluding the low two bits stored in the computer. This high-order data (100100) indicates the position 36 of the current output value q+ in the first truth table 220. Based on the value of this high-order data, the simulation tool 120 can determine the row of the current output at element position 36 in the first truth table 220. The simulation tool 120 can then read the value x (i.e., 3) corresponding to the output (i.e., column q) from the determined row as the current output value.

[0050] In some other embodiments, the simulation tool 120 can perform a modulo operation on the state number 4 of the current input value I1 of the first input i1 using the element value 39. The result 3 obtained from the modulo operation is the current output value of UDP at this time.

[0051] In some embodiments, UDP can also simultaneously receive a new first input i1 and a new second input i2. In this case, the simulation tool 120 can first process the new first input i1 in the first truth table 220, using the output retrieved from the first truth table 120 as the prior output q; then, using the new first input i1 and the prior output q, it can process the new second input i2 in the second truth table, obtaining the current output value q+ of UDP from the second truth table. In this way, the simulation tool 120 obtains the final current output value of UDP by processing the changing input values ​​in two truth tables one at a time.

[0052] Using the method employed in the embodiments of this disclosure, the number of element values ​​in each truth table is 3. N+1 *4. For a two-input sequential logic UDP (i.e., input N=2), each truth table has 108 elements, and the total number of elements in both truth tables is 216. It can be seen that the total number of elements is less than... Figure 2B The traditional truth table shown contains 243 elements.

[0053] In some embodiments, the UDP input z is processed in the same way as the input x, so the current input values ​​I1+=x and I1+=z can be merged into the same column for processing. In this case, the number of elements in the first truth table 220 can be further reduced to 81. Accordingly, the total number of elements in the two truth tables is 162, further reducing the number of elements in the truth tables.

[0054] It is understood that the above embodiment is illustrated using a two-input sequential logic UDP as an example. In practical applications, sequential logic UDPs can support at least nine inputs. In this case, the number of elements in a traditional truth table scheme can be as high as 10. 10 The scale is smaller than that of the previous method, which can reduce the number of element values ​​to 10.6 The magnitude of the input increases. The advantage of the method provided in this disclosure regarding storage space becomes increasingly apparent as the number of inputs increases.

[0055] The method provided in this disclosure generates a corresponding truth table for each UDP input, effectively reducing the number of elements in the truth table and thus reducing the storage space occupied by the truth table. During simulation, the simulation tool 120 can read the stored truth table more quickly, improving the implementation efficiency of UDP.

[0056] Figure 3 A flowchart is shown of an exemplary method 300 for implementing a timing logic user-defined primitive (UDP) according to an embodiment of this disclosure. Method 300 can be implemented by, for example... Figure 1A The method can be executed by the electronic device 100, or more specifically, by the simulation tool 120 running on the electronic device 100. The method 300 may include the following steps.

[0057] In step S302, the simulation tool 120 can receive a description of the user-defined primitive (UDP) (e.g., Figure 2A The description shown is 200). This description includes at least a first input (e.g., Figure 2A The first input i1 and the second input (e.g., shown) are shown. Figure 2A The second input i2 shown) and the output associated with the first input and the second input (e.g., Figure 2A The output values ​​q and q+ at the previous and current times are shown.

[0058] In some embodiments, the description of the UDP may include a UDP state table.

[0059] In step S304, the simulation tool 120 can generate a first truth table corresponding to the first input and the second input respectively, based on the description of the UDP (e.g., Figure 2C The first truth table 220 and the second truth table are shown. The first truth table includes the first input, the second input, and the output's first prior input value at the previous time step (e.g., ...). Figure 2C The first input value I1 shown), the second first input value (e.g., Figure 2C The preceding input value I2 and the preceding output value (e.g., shown) are shown. Figure 2C The preceding output value q shown, and the first current input value of the first input at the current time (e.g., Figure 2C The current input value shown is I1+).

[0060] In step S306, the simulation tool 120 can determine the first truth table (e.g., Figure 2CThe first truth table 220 shown is consistent with the first prior input value (e.g., Figure 2C The first input value I1 shown), and the second first input value (e.g., Figure 2C The preceding input value I2 shown), and the preceding output value (e.g., Figure 2C The preceding output value q) and the first current input value (e.g., Figure 2C The first element value corresponding to the current input value I1+) shown.

[0061] In some embodiments, the first truth table also includes element positions (e.g., Figure 2C The first column "Element Position" of the first truth table 220 shown. In some embodiments, the element position may be configured as the position index of the first truth table, and the value of the element position is determined by the state number of the first current input value (e.g., Figure 2C The four states of the current input value I1+ of the first input i1 shown are determined (the number of states is 4). For example, the value of the element position in the first truth table 220 can be 0, 4, 8, ..., 104.

[0062] In some embodiments, the simulation tool 120 can obtain information from the UDP description (e.g., based on the first prior input value (e.g., I1 = x), the first current input value (e.g., I1+ = 0), the second prior input value (e.g., I2 = x), and the prior output value (e.g., q = x). Figure 2A The current output value of the UDP is determined in the description 200 shown (e.g., q+=x=3). The simulation tool 120 can determine the element position (e.g., element position 36) in the first truth table based on the first current input value (e.g., I1+=0), the second prior input value (e.g., I2=x), and the current output value (e.g., q+=x). The simulation tool 120 can calculate the first element value based on the element position and the current output value.

[0063] In some embodiments, the simulation tool 120 may use the sum of the value at the element position (e.g., the value at the element position 36) and the current output value (e.g., q+=3) as the first element value (e.g., 36+3=39).

[0064] In some embodiments, the simulation tool 120 may use the method of generating a first truth table to generate a second truth table corresponding to the second input, so as to determine the second element value in the second truth table.

[0065] In step S308, the simulation tool 120 can determine the current output value of the UDP at the current moment in the first truth table based on the first element value (e.g., 39).

[0066] In some embodiments, the simulation tool 120 may obtain the lower two bits of the first element value (e.g., the lower two bits of 39, 11) as the current output value (e.g., 3).

[0067] In other embodiments, the simulation tool 120 may acquire the higher-order data (e.g., the higher-order data of 39, 100100) beyond the lower two digits of the first element value. This higher-order data may indicate the element position of the current output value in the first truth table (e.g., element position 36). The simulation tool 120 may determine the row containing the current output value in the first truth table based on this element position (e.g., the row indicated by element position 36). The simulation tool 120 may then determine the current output value from this row (e.g., the value x = 3 in column q of that row).

[0068] In some other embodiments, the simulation tool 120 may perform a modulo operation based on the first element value (e.g., 39) and the state number (e.g., state number 4) of the first current input value. The simulation tool 120 may use the result of the modulo operation as the current output value (e.g., operation result 3).

[0069] In some embodiments, UDP can receive both a new first input and a new second input simultaneously. The simulation tool 120 can determine the prior output value of the UDP in a first truth table based on the first element value. Then, the simulation tool 120 can continue to determine the current output value of the UDP in a second truth table based on the second element value.

[0070] This disclosure also provides an electronic device for implementing user-defined primitives of sequential logic. The electronic device may be... Figure 1A The electronic device 100 is shown. The electronic device 100 can be configured to execute a computer program stored in memory 104 to implement methods for implementing user-defined primitives of timing logic consistent with this disclosure, such as the exemplary methods described above (e.g., Figure 3 The method shown is 300). It will not be described in detail here.

[0071] This disclosure also provides a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium stores a set of instructions for an electronic device 100. When these instructions are executed, the electronic device 100 implements a method for implementing user-defined timing logic primitives consistent with this disclosure, such as the exemplary method described above (e.g., Figure 3 The method shown is 300). It will not be described in detail here.

[0072] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0073] The foregoing has described specific embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0074] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of the different aspects of this disclosure as described above, which are not provided in detail for the sake of brevity.

[0075] Additionally, to simplify the description and discussion, and to avoid obscuring the present disclosure, the provided drawings may or may not show well-known power / ground connections to integrated circuit (IC) chips and other components. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the present disclosure, and this also takes into account the fact that the details of implementations of these block diagram apparatuses are highly dependent on the platform on which the present disclosure will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present disclosure, it will be apparent to those skilled in the art that the present disclosure may be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0076] Although this disclosure has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0077] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure shall be included within the scope of protection of this disclosure.

Claims

1. A method for implementing a user-defined primitive of sequential logic, comprising: receiving a description of the user-defined primitive, the description comprising at least a first input, a second input, and an output associated with the first input and the second input; generating a first truth table and a second truth table corresponding to the first input and the second input, respectively, according to the description of the user-defined primitive, wherein the first truth table comprises the first input, the second input, and a first previous input value, a second previous input value, and a previous output value of the output at a previous time, and a first current input value of the first input at a current time, and the second truth table comprises the first input, the second input, and the first previous input value, the second previous input value, and the previous output value of the output at the previous time, and a second current input value of the second input at the current time; determining a first element value in the first truth table corresponding to the first previous input value, the second previous input value, the previous output value, and the first current input value; and determining a current output value of the output of the user-defined primitive at the current time in the first truth table based on the first element value.

2. The method of claim 1, wherein, the first truth table further comprises an element position, and determining the first element value in the first truth table corresponding to the first previous input value, the second previous input value, the previous output value, and the first current input value further comprises: determining the current output value from the description of the user-defined primitive according to the first previous input value, the first current input value, the second previous input value, and the previous output value; determining the element position in the first truth table based on the first current input value, the second previous input value, and the current output value; and calculating the first element value according to the element position and the current output value.

3. The method of claim 2, wherein, the element position is configured as a position index of the first truth table, and a value of the element position is determined by a state number of the first current input value.

4. The method of claim 3, wherein, calculating the first element value according to the element position and the current output value further comprises: using a sum of the value of the element position and the current output value as the first element value.

5. The method of claim 4, wherein, determining a current output value of the output of the user-defined primitive at the current time in the first truth table based on the first element value further comprises: obtaining a lower two bits of the first element value as the current output value.

6. The method of claim 4, wherein, determining a current output value of the output of the user-defined primitive at the current time in the first truth table based on the first element value further comprises: obtaining a higher bit of the first element value other than the lower two bits, the higher bit indicating an element position of the current output value in the first truth table; determining a row in which the current output value is located in the first truth table according to the higher bit; and determining the current output value from the row.

7. The method of claim 4, wherein, determining a current output value of the output of the user-defined primitive at the current time in the first truth table based on the first element value further comprises: performing a modulo operation on a state number based on the first element value and the first current input value; and outputting the result of the modulo operation as the current output value. 8.The method of any one of claims 1-7, further comprising: determining a second element value in the second truth table corresponding to the first previous input value, the second previous input value, the previous output value, and the second current input value; determining, based on the first element value, the previous output value of the user-defined primitive in the first truth table; and determining, based on the second element value, the current output value of the user-defined primitive in the second truth table. 9.An electronic device implementing a user-defined primitive of sequential logic, comprising: a memory configured to store a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform the method of any one of claims 1-8. 10.A non-transitory computer-readable storage medium storing a set of instructions for an electronic device, the set of instructions, when executed, cause the electronic device to perform the method of any one of claims 1-8. ​ ​

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