Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate; forming a first dielectric layer and a plurality of gate structures on the substrate, wherein the top surface of the first dielectric layer is higher than the top surface of the gate structure, and the first dielectric layer has a first opening, wherein the first opening exposes the top surface of the gate structure; and using a selective film forming process to form a conductive protective film on the top surface of the gate structure exposed by the first opening. The formation method can improve the performance and reliability of the formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits are becoming higher and higher. In order to improve integration and reduce costs, the key dimensions of components are constantly decreasing, and the circuit density inside the integrated circuit is increasing. This development makes it impossible for the wafer surface to provide enough area to make the required interconnection lines.

[0003] The connection plugs in the transistor structure include connection plugs located on the surface of the gate structure for connecting the gate structure with an external circuit; and connection plugs located on the surface of the source and drain doped regions for connecting the source or drain region of the transistor with an external circuit.

[0004] However, the performance and reliability of semiconductor structures still need to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance and reliability of the semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a first dielectric layer and a plurality of gate structures located on the substrate, wherein source-drain structures are provided in the substrate on both sides of the gate structure, the top surface of the first dielectric layer is higher than the top surface of the gate structure, and the first dielectric layer has a first opening and a second opening, the first opening exposes the top surface of the gate structure, and the second opening exposes the top surface of the source-drain structure; a conductive protective film, wherein the conductive protective film is located on the top surface of the gate structure exposed by the first opening; a first conductive structure located in the first opening, wherein the first conductive structure is also located on the top surface of the conductive protective film, and the first conductive structure is flush with the top surface of the first dielectric layer; and a second conductive structure located in the second opening, wherein the second conductive structure is also located on the top surface of the source-drain structure exposed by the second opening, and the second conductive structure is flush with the top surface of the first dielectric layer.

[0007] Optionally, the material of the conductive protection film includes fluorine-free tungsten.

[0008] Optionally, the thickness of the conductive protective film ranges from 1.5 nanometers to 5 nanometers.

[0009] Optionally, the gate structure includes: a gate dielectric layer, a work function layer located on a surface of the gate dielectric layer, and a gate layer located on a surface of the work function layer.

[0010] Optionally, the material of the work function layer includes TiAl.

[0011] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate; forming a first dielectric layer and a plurality of gate structures on the substrate, wherein the top surface of the first dielectric layer is higher than the top surface of the gate structure, and the first dielectric layer has a first opening, and the first opening exposes the top surface of the gate structure; using a selective film forming process to form a conductive protective film on the top surface of the gate structure exposed by the first opening.

[0012] Optionally, the material of the conductive protective film includes fluorine-free tungsten, the selective film forming process includes a selective atomic layer deposition process, and the reaction gas used in the selective atomic layer deposition process includes tungsten pentachloride.

[0013] Optionally, the parameters of the selective atomic layer deposition process also include: the reaction gas used also includes hydrogen; the reaction temperature is 350 degrees Celsius to 450 degrees Celsius.

[0014] Optionally, the substrate on both sides of the gate structure has a source-drain structure, and the method for forming the semiconductor structure further includes: after forming the conductive protection film, forming a second opening in the first dielectric layer, the second opening exposing the top surface of the source-drain structure.

[0015] Optionally, the method further includes: after forming the second opening, performing a pre-treatment and cleaning step on the top surface of the source / drain structure exposed by the second opening.

[0016] Optionally, the process of the pre-treatment cleaning step includes a dry cleaning process, and the reaction gas used in the dry cleaning process includes NF 3 and NH 3 .

[0017] Optionally, after the pre-treatment cleaning step, the method further includes: forming a first conductive structure in the first opening, and forming a second conductive structure in the second opening.

[0018] Optionally, the method for forming the first conductive structure and the second conductive structure includes: depositing a plug material layer in the first opening, in the second opening and on the surface of the first dielectric layer, wherein the surface of the plug material layer is higher than the surface of the first dielectric layer; and planarizing the plug material layer until the surface of the first dielectric layer is exposed.

[0019] Optionally, the process of forming the first conductive structure and the second conductive structure includes at least one of a metal electroplating process, a chemical vapor deposition process and a selective metal growth process.

[0020] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0021] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the first opening provides space for a conductive structure that is electrically interconnected with the gate structure to be subsequently formed on the top surface of the gate structure. By adopting a selective film forming process, a conductive protective film can be formed on the top surface of the gate structure in a targeted manner with simple process steps. At the same time, since a conductive protective film is formed on the top surface of the gate structure exposed by the first opening, the conductive protective film can protect the exposed top surface of the gate structure in the process before the conductive structure is subsequently formed, such as etching, pretreatment cleaning and other steps, thereby reducing damage to the gate structure, thereby improving the performance and reliability of the semiconductor structure.

[0022] Furthermore, since the second opening is formed after the conductive protective film is formed, the first dielectric layer can protect the source-drain structure during the etching process of forming the first opening and the selective film formation process of forming the conductive protective film, thereby reducing the damage to the surface of the source-drain structure during the etching process of etching the first opening and avoiding the risk of defect seeds forming on the surface of the source-drain structure during the formation of the conductive protective film, thereby improving the performance and reliability of the semiconductor structure.

[0023] Furthermore, since the pretreatment cleaning step is performed on the top surface of the source-drain structure exposed by the second opening after the second opening is formed, not only the natural oxide film on the surface of the source-drain structure can be removed, but also the gate structure is protected in the pretreatment cleaning step through the conductive protective film, thereby avoiding damage to the gate structure caused by the pretreatment cleaning step.

[0024] Furthermore, when the fluorine-free tungsten is formed by a selective atomic layer deposition process in which the reaction gas is tungsten pentachloride gas, the selectivity for the substrate material is high, and the fluorine-free tungsten is easy to form on the surface of substrate materials such as titanium aluminum, titanium nitride, and aluminum, but not easy to form on the surface of dielectric materials. Therefore, the selective atomic layer deposition process can achieve a more targeted formation of a conductive protective film on the top surface of the gate structure with simple process steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 to Figure 2 It is a structural schematic diagram of each step of a method for forming a semiconductor structure;

[0026] Figures 3 to 10 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0027] As described in the background art, the performance and reliability of semiconductor structures still need to be improved. The reasons for the complexity of the manufacturing process are now explained in conjunction with the accompanying drawings.

[0028] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0029] Figure 1 to Figure 2 The present invention is a structural schematic diagram of each step of a method for forming a semiconductor structure.

[0030] Please refer to Figure 1 , providing a substrate 100, on which a dielectric layer 120 and a plurality of gate structures 110 are provided, and source-drain doped regions 130 are provided in the substrate 100 on both sides of the gate structure 110.

[0031] Please continue to refer to Figure 1 , a first opening 121 is formed in the dielectric layer 120, and the bottom of the first opening 121 exposes the top surface of the source-drain structure 130; after the first opening 121 is formed, a second opening 122 is formed in the dielectric layer 120, and the second opening 122 exposes the top surface of the gate structure 110; the exposed top surface of the source-drain structure 130 is pre-cleaned to form a metal plug to remove the natural oxide film (not shown) on the top surface of the source-drain structure 130.

[0032] Please refer to Figure 2 , a metal plug material is deposited in the first opening 121 and the second opening 122 to form a first plug 140 in contact with the top surface of the source-drain structure 130 in the first opening 121 , and a second plug 150 in contact with the top surface of the gate structure 110 in the second opening 122 .

[0033] In the above method, in order to reduce the damage to the gate structure 110 caused by the etching process of forming the first opening 121 , the second opening 122 is formed after the first opening 121 is formed, so that the gate structure 110 can be protected by the dielectric layer 120 during the process of forming the first opening 121 .

[0034] However, the gate structure 110 is exposed at the bottom of the second opening 122, so that the pre-treatment cleaning may damage the gate structure 110. Specifically, when the work function layer of the gate structure 110 includes titanium aluminum (TiAl), the pre-treatment cleaning process uses a reaction gas NF 3 Not only the natural oxide film is etched, but also the work function layer of the gate structure 110 is etched, causing damage to the gate structure 110. Therefore, the performance and reliability of the semiconductor structure are poor.

[0035] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure and a method for forming the same. By forming a conductive protective film on the top surface of the gate structure exposed by the first opening, the gate structure can be protected before a conductive structure electrically interconnected with the gate structure is formed, thereby improving the performance and reliability of the semiconductor structure.

[0036] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Figures 3 to 10 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0038] Please refer to Figure 3 and Figure 4 , Figure 3 yes Figure 4 Schematic diagram of the three-dimensional structure, Figure 4 yes Figure 3 A schematic cross-sectional structure diagram along the X1-X2 direction is provided in the substrate 200.

[0039] In this embodiment, the substrate 200 includes: a base 201 and a plurality of fins 202 separated from each other and located on the base 201 .

[0040] In other embodiments, the substrate is a planar substrate.

[0041] In this embodiment, the material of the substrate 200 includes silicon.

[0042] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, multinary semiconductor materials composed of III-V group elements, silicon on insulator (SOI) or germanium on insulator (GOI), etc. Among them, multinary semiconductor materials composed of III-V group elements include InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0043] Please continue to refer to Figure 3 and Figure 4 , an isolation layer 203 is formed on the substrate 200.

[0044] The isolation layer 203 is located on the surface of the substrate 201 . The isolation layer 203 is also located between adjacent fins 202 . Moreover, the surface of the isolation layer 203 is lower than the top surface of the fin 202 .

[0045] The isolation layer 203 serves to electrically insulate adjacent fins 202 and between the semiconductor device and the substrate 201 .

[0046] In this embodiment, the material of the isolation layer 203 includes silicon oxide.

[0047] Please refer to Figure 5 After forming the isolation layer 203, a first dielectric layer 220 and a plurality of separate gate structures 210 are formed on the substrate 200. The top surface of the first dielectric layer 220 is higher than the top surface of the gate structure 210. The first dielectric layer 220 has a first opening 241 therein. The first opening 241 exposes the top surface of the gate structure 210.

[0048] In this embodiment, the gate structure 210 and the first dielectric layer 220 are also located on the isolation layer 203 , and the gate structure 210 spans across the fin 202 .

[0049] In this embodiment, source-drain structures 230 are provided in the substrate 200 on both sides of the gate structure 210 .

[0050] Specifically, the source-drain structures 230 are located in the fins 202 on both sides of the gate structure 210 .

[0051] The method for forming the plurality of gate structures 210, the first dielectric layer 220 and the source-drain structure 230 includes: forming a plurality of dummy gate structures (not shown in the figure) and gate spacers 215 located on the sidewalls of the dummy gate structures on the isolation layer 203, wherein the plurality of dummy gate structures are separated from each other and the dummy gate structures span the fin 202; forming source-drain structures 230 in the fins 202 on both sides of the dummy gate structures; after forming the source-drain structures 230, forming a lower first dielectric layer (not shown in the figure) on the substrate 200, wherein the lower first dielectric layer covers the sidewall surfaces of the dummy gate structures; removing the dummy gate structures and forming a gate opening in the lower first dielectric layer; forming a gate structure 210 in the gate opening; forming an upper first dielectric layer on the surface of the lower first dielectric layer, wherein the top surface of the upper first dielectric layer is higher than the top surface of the gate structure 210, and the lower first dielectric layer and the upper first dielectric layer constitute the first dielectric layer 220.

[0052] The gate spacer 215 has the function of defining the positions of the source and drain openings on the one hand, and is conducive to forming a gate opening with a better morphology on the other hand.

[0053] Specifically, the method for forming the source-drain structure 230 in this embodiment includes: after forming the dummy gate structure and before forming the lower first dielectric layer, forming source-drain openings (as shown in the figure) in the fins 202 on both sides of the dummy gate structure; and using an epitaxial growth process to form the source-drain openings 230 in the source-drain openings.

[0054] In other embodiments, the process of forming the source-drain structure includes an ion implantation process.

[0055] The gate structure 210 includes a gate dielectric layer 211 , a work function layer 212 located on a surface of the gate dielectric layer 211 , and a gate layer 213 located on a surface of the work function layer 212 .

[0056] Specifically, the gate dielectric layer 211 is located on the inner wall surface of the gate opening.

[0057] The material of the gate dielectric layer 211 includes silicon oxide or a high-K dielectric material, where the high-K dielectric material refers to a material having a dielectric constant greater than 3.9.

[0058] The material of the work function layer 212 includes one or more combinations of TiN, TaN, TiAl, TiAlC, TaAlN, TiAlN, TaCN and AlN.

[0059] Specifically, the material of the work function layer 212 in this embodiment includes TiAl.

[0060] The material of the gate layer 213 includes one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

[0061] The material of the first dielectric layer 220 is a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride.

[0062] The first opening 241 provides space for subsequently forming a conductive protection film and a first conductive structure.

[0063] The method for forming the first opening 241 includes: forming a first patterned layer (not shown in the figure) on the surface of the first dielectric layer 220, wherein the first patterned layer exposes a portion of the surface of the first dielectric layer 220; using the first patterned layer as a mask, etching the first dielectric layer 220 until the top surface of the gate structure 210 is exposed to form the first opening 241.

[0064] The process of etching the first dielectric layer 220 includes: a dry etching process and a wet etching process, or a combination of the two.

[0065] In this embodiment, the first dielectric layer 220 is etched using a dry etching process, which is beneficial to improving the morphology of the formed first opening 241, thereby improving the performance of the formed semiconductor structure.

[0066] Please refer to Figure 6 , a conductive protection film 250 is formed on the top surface of the gate structure 210 exposed by the first opening 241 by using a selective film forming process.

[0067] By adopting the selective film forming process, the conductive protection film 250 can be formed on the top surface of the exposed gate structure 210 in a targeted manner with simple process steps. At the same time, since the conductive protection film 250 is formed on the top surface of the gate structure 210 exposed by the first opening 241, the conductive protection film 250 can protect the exposed top surface of the gate structure 210 in the subsequent process before the first conductive structure is formed, such as etching, pre-treatment cleaning and other steps, thereby reducing the damage to the gate structure 210, thereby improving the performance and reliability of the semiconductor structure.

[0068] In this embodiment, the material of the conductive protection film 250 includes fluorine-free tungsten (FFW, Fluorine Free W).

[0069] In this embodiment, the selective film forming process includes a selective atomic layer deposition process, and the reaction gas used in the selective atomic layer deposition process includes tungsten pentachloride.

[0070] Since the selective atomic layer deposition process uses chlorine-based (tungsten pentachloride) reaction gas to form the material of the conductive protective film 250, the conductive protective film 250 can be formed without fluorine element in the material, that is, the conductive protective film 250 is formed including fluorine-free tungsten.

[0071] Moreover, when the fluorine-free tungsten is formed by the selective atomic layer deposition process using tungsten pentachloride as the reaction gas, the selectivity for the substrate material is high, and the fluorine-free tungsten is easy to form on the surface of substrate materials such as TiN, TiAl, Al, etc., but not easy to form on the surface of dielectric materials. Therefore, the selective atomic layer deposition process can achieve a more targeted formation of a conductive protective film on the top surface of the gate structure 210 with simple process steps.

[0072] At the same time, the material formed by the atomic layer deposition process has good density, which is conducive to better protecting the top surface of the gate structure 210 through the conductive protection film 250.

[0073] In this embodiment, the parameters of the selective atomic layer deposition process also include: the reaction gas used also includes hydrogen; the reaction temperature is 350 degrees Celsius to 450 degrees Celsius.

[0074] In this embodiment, the parameters of the selective atomic layer deposition process also include: the gas used also includes nitrogen.

[0075] Specifically, during the selective atomic layer deposition process, tungsten pentachloride is introduced into the chamber several times, wherein each time the tungsten pentachloride is introduced, the duration of the introduction is 0.1 to 2 seconds. After each introduction of tungsten pentachloride, nitrogen is introduced for purging to discharge the unadsorbed tungsten pentachloride out of the chamber, wherein each time the nitrogen is introduced, the duration of the introduction is 0.5 to 3 seconds. After each removal of the unadsorbed tungsten pentachloride, hydrogen is continuously introduced to react with the adsorbed tungsten pentachloride to form a partially conductive protective film 250 material including fluorine-free tungsten, wherein each time the hydrogen is introduced, the duration of the introduction is 0.5 to 3 seconds.

[0076] In this embodiment, in a direction perpendicular to the surface of the substrate 200 , the thickness of the conductive protection film 250 ranges from 1.5 nanometers to 5 nanometers.

[0077] The thickness of the conductive protective film 250 is too thin, and the conductive protective film 250 formed on the exposed top surface of the gate structure 210 has poor material continuity, which makes it difficult for the conductive protective film 250 to completely cover the top surface of the gate structure 210, resulting in poor protection of the gate structure 210 by the conductive protective film 250. The selective atomic layer deposition process has a low material deposition rate, and a conductive protective film 250 that is too thick will not only lead to material waste, but also increase process time and reduce process efficiency. Therefore, when a suitable thickness range of the conductive protective film 250 is selected, that is, when the thickness range of the conductive protective film 250 is selected to be 1.5 nanometers to 5 nanometers, not only can a conductive protective film 250 with good material continuity be formed to better protect the gate structure 210, but also, material waste is avoided and process efficiency is improved.

[0078] Please refer to Figure 7 After the conductive protection film 250 is formed, a second opening 242 is formed in the first dielectric layer 220 , and the second opening 242 exposes the top surface of the source-drain structure 230 .

[0079] The second opening 242 provides a space for subsequently forming a second conductive structure.

[0080] The method for forming the second opening 242 includes: forming a second patterned layer (not shown in the figure) on the surface of the first dielectric layer 220, wherein the second patterned layer exposes a portion of the surface of the first dielectric layer 220; using the second patterned layer as a mask, etching the first dielectric layer 220 until the top surface of the source-drain structure 230 is exposed to form the second opening 242.

[0081] The process of etching the first dielectric layer 220 to form the second opening 242 includes: a dry etching process and a wet etching process or a combination of the two.

[0082] In this embodiment, the first dielectric layer 220 is etched using a dry etching process, which is beneficial to improving the morphology of the formed second opening 242, thereby improving the performance of the formed semiconductor structure.

[0083] Since the second opening 242 is formed after the conductive protection film 250 is formed, the first dielectric layer 220 can protect the source-drain structure 230 during the etching process of forming the first opening 241 and the selective film formation process of forming the conductive protection film 250, thereby reducing the damage to the surface of the source-drain structure 230 caused by the etching process of the first opening 241 and avoiding the risk of defect seeds being formed on the surface of the source-drain structure 230 during the process of forming the conductive protection film 250, thereby improving the performance and reliability of the semiconductor structure.

[0084] Please refer to Figure 8 After forming the second opening 242 , a pre-treatment cleaning step is performed on the top surface of the source / drain structure 230 exposed by the second opening 242 .

[0085] The pre-treatment cleaning step is used to remove the natural oxide film on the surface of the source / drain structure 230 .

[0086] Since the top surface of the source-drain structure 230 exposed by the second opening 242 is subjected to a pretreatment cleaning step after the second opening 242 is formed, not only the natural oxide film on the surface of the source-drain structure 230 can be removed, but also the gate structure 210 can be protected by the conductive protective film 230 during the pretreatment cleaning step, thereby avoiding damage to the gate structure 210 caused by the pretreatment cleaning step.

[0087] Moreover, since the conductive protection film 230 is exposed during the pretreatment cleaning step, when there is a natural oxide film on the surface of the conductive protection film 230, it can also be removed by the pretreatment cleaning step, thereby further improving the performance and reliability of the semiconductor structure.

[0088] In this embodiment, the process of the pre-treatment cleaning step includes a dry cleaning process.

[0089] Specifically, the reaction gas used in the dry cleaning process includes NF 3 and NH 3 The conductive protection film 250 covers the exposed top surface of the gate structure 210, and the conductive protection film 250 is not easily 3 and NH 3 Therefore, the conductive protective film 250 avoids NF 3 and NH 3 Damage caused to the gate structure 210.

[0090] Next, a first conductive structure is formed in the first opening 241, and a second conductive structure is formed in the second opening 242. For details on the process of forming the first conductive structure and the second conductive structure, please refer to Figures 9 and 10 .

[0091] Please refer to Fig. 9 A plug material layer 260 is deposited in the first opening 241 , in the second opening 242 and on the surface of the first dielectric layer 220 . The surface of the plug material layer 260 is higher than the surface of the first dielectric layer 220 .

[0092] The plug material layer 260 provides material for forming the first conductive structure and the second conductive structure.

[0093] In this embodiment, the process of forming the plug material layer 260 includes a metal electroplating process or a chemical vapor deposition process.

[0094] In other embodiments, the process of forming the plug material layer includes a selective metal growth process.

[0095] Please refer to Fig.10 , planarizing the plug material layer 260 until the surface of the first dielectric layer 220 is exposed, forming a first conductive structure 261 in the first opening 241 , and forming a second conductive structure 262 in the second opening 242 .

[0096] The first conductive structure 261 is electrically interconnected with the gate structure 210 , and the second conductive structure 262 is electrically interconnected with the source-drain structure 230 .

[0097] The material of the first conductive structure 261 and the second conductive structure 262 includes: one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

[0098] Specifically, in this embodiment, the first conductive structure 261 includes: a first conductive structure buffer layer (not shown) located on the inner wall of the first opening 241 and a first conductive structure conductive layer (not shown) located on the surface of the first conductive structure buffer layer.

[0099] Specifically, in this embodiment, the second conductive structure 262 includes: a second conductive structure buffer layer (not shown) located on the inner wall of the second opening 242 and a second conductive structure conductive layer (not shown) located on the surface of the second conductive structure buffer layer.

[0100] The functions of the first conductive structure buffer layer and the second conductive structure buffer layer are, on the one hand, to increase the adhesion of the first conductive structure conductive layer and the second conductive structure conductive layer, thereby improving the performance of the first conductive structure 261 and the second conductive structure 262, and on the other hand, to block the atoms or ions in the first conductive structure conductive layer and the second conductive structure conductive layer from diffusing into the first dielectric layer 220 and the gate structure 210, so as to avoid affecting the performance of the gate structure 210 and avoiding leakage, thereby improving the performance of the semiconductor structure.

[0101] In this embodiment, the process of planarizing the plug material layer 260 includes a chemical mechanical polishing process.

[0102] In the present embodiment, since the first conductive structure 261 and the second conductive structure 262 are formed in the same process, the process efficiency of forming the first conductive structure 261 and the second conductive structure 262 is high.

[0103] In other embodiments, the first conductive structure and the second conductive structure may be formed respectively through different process steps. Specifically, the second conductive structure may be formed before the first conductive structure is formed, or the first conductive structure may be formed before the second conductive structure is formed. Thus, the materials of the first conductive structure and the second conductive structure may be different, and the formation process and material selection of the first conductive structure and the second conductive structure are highly flexible.

[0104] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned forming method, please continue to refer to Fig.10 The semiconductor structure includes: a substrate 200; a first dielectric layer 220 and a plurality of gate structures 210 located on the substrate 200; source-drain structures 230 are provided in the substrate 200 on both sides of the gate structure 210; the top surface of the first dielectric layer 220 is higher than the top surface of the gate structure 210; and the first dielectric layer 210 has a first opening 241 (such as Figure 5 as shown) and a second opening 242 (as shown Figure 5 As shown), the first opening 241 exposes the top surface of the gate structure 210, and the second opening 242 exposes the top surface of the source-drain structure 230; a conductive protection film 250, the conductive protection film 250 is located on the top surface of the gate structure 210 exposed by the first opening 241; located in the first opening 241 (as shown Figure 5 The first conductive structure 261 is located in the second opening 242, and the first conductive structure 261 is also located on the top surface of the conductive protection film 250; the second conductive structure 262 is located in the second opening 242, and the second conductive structure 262 is also located on the top surface of the source-drain structure 230 exposed by the second opening 242.

[0105] In this embodiment, the substrate 200 includes: a base 201 and a plurality of fins 202 separated from each other and located on the base 201 .

[0106] The source-drain structures 230 are located in the fins 202 on both sides of the gate structure 210 .

[0107] In other embodiments, the substrate is a planar substrate.

[0108] In this embodiment, the material of the substrate 200 includes silicon.

[0109] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, multinary semiconductor materials composed of III-V group elements, silicon on insulator (SOI) or germanium on insulator (GOI), etc. Among them, multinary semiconductor materials composed of III-V group elements include InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0110] The gate structure 210 includes a gate dielectric layer 211 , a work function layer 212 located on a surface of the gate dielectric layer 211 , and a gate layer 213 located on a surface of the work function layer 212 .

[0111] The material of the gate dielectric layer 211 includes silicon oxide or a high-K dielectric material, where the high-K dielectric material refers to a material having a dielectric constant greater than 3.9.

[0112] The material of the work function layer 212 includes one or more combinations of TiN, TaN, TiAl, TiAlC, TaAlN, TiAlN, TaCN and AlN.

[0113] Specifically, the material of the work function layer 212 in this embodiment includes TiAl.

[0114] The material of the gate layer 213 includes one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

[0115] The material of the first dielectric layer 220 is a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride.

[0116] In this embodiment, the material of the conductive protection film 250 includes fluorine-free tungsten (FFW, Fluorine Free W).

[0117] In this embodiment, in a direction perpendicular to the surface of the substrate 200 , the thickness of the conductive protection film 250 ranges from 1.5 nanometers to 5 nanometers.

[0118] In this embodiment, the first conductive structure 261 is flush with the top surface of the first dielectric layer 220 , and the second conductive structure 262 is flush with the top surface of the first dielectric layer 220 .

[0119] The first conductive structure 261 is electrically interconnected with the gate structure 210 .

[0120] The material of the first conductive structure 261 includes: one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

[0121] In this embodiment, the first conductive structure 261 includes: a first conductive structure buffer layer (not shown) located on the inner wall of the first opening 241 and a first conductive structure conductive layer (not shown) located on the surface of the first conductive structure buffer layer.

[0122] The function of the first conductive structure buffer layer is, on the one hand, to increase the adhesion of the conductive layer of the first conductive structure, thereby improving the performance of the first conductive structure 261, and on the other hand, to block the atoms or ions in the conductive layer of the first conductive structure from diffusing into the first dielectric layer 220 and the gate structure 210, so as to avoid affecting the performance of the gate structure 210 and avoid leakage, thereby improving the performance of the semiconductor structure.

[0123] The second conductive structure 262 is electrically interconnected with the source-drain structure 230 .

[0124] The material of the second conductive structure 262 includes: one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

[0125] In this embodiment, the second conductive structure 262 includes: a second conductive structure buffer layer (not shown) located on the inner wall of the second opening 242 and a second conductive structure conductive layer (not shown) located on the surface of the second conductive structure buffer layer.

[0126] The function of the second conductive structure buffer layer is, on the one hand, to increase the adhesion of the conductive layer of the second conductive structure, thereby improving the performance of the second conductive structure 262, and on the other hand, to block the atoms or ions in the conductive layer of the second conductive structure from diffusing into the first dielectric layer 220 and the gate structure 210, so as to avoid affecting the performance of the gate structure 210 and avoid leakage, thereby improving the performance of the semiconductor structure.

[0127] In this embodiment, the semiconductor structure further includes: an isolation layer 203 located on the substrate 200 .

[0128] Specifically, the isolation layer 203 is located on the surface of the substrate 201 , and is also located between adjacent fins 202 . Moreover, the surface of the isolation layer 203 is lower than the top surface of the fin 202 .

[0129] The isolation layer 203 serves to electrically insulate adjacent fins 202 and between the semiconductor device and the substrate 201 .

[0130] Specifically, the gate structure 210 and the first dielectric layer 220 are also located on the isolation layer 203 , and the gate structure 210 spans across the fin 202 .

[0131] In this embodiment, the material of the isolation layer 203 includes silicon oxide.

[0132] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A first dielectric layer and a plurality of gate structures are located on a substrate, wherein source-drain structures are provided in the substrate on both sides of the gate structures, a top surface of the first dielectric layer is higher than a top surface of the gate structures, and a first opening and a second opening are provided in the first dielectric layer, wherein the first opening exposes the top surface of the gate structures, and the second opening exposes the top surface of the source-drain structures; A conductive protection film, wherein the conductive protection film is located on a top surface of the gate structure exposed by the first opening; A first conductive structure located in the first opening, the first conductive structure is also located on the top surface of the conductive protection film, and the first conductive structure is flush with the top surface of the first dielectric layer; The second conductive structure is located in the second opening, the second conductive structure is also located on the top surface of the source-drain structure exposed by the second opening, and the second conductive structure is flush with the top surface of the first dielectric layer.

2. The semiconductor structure according to claim 1, wherein: The material of the conductive protection film includes fluorine-free tungsten.

3. The semiconductor structure according to claim 1, wherein: The thickness of the conductive protection film ranges from 1.5 nanometers to 5 nanometers.

4. The semiconductor structure according to claim 1, wherein: The gate structure includes: a gate dielectric layer, a work function layer located on the surface of the gate dielectric layer, and a gate layer located on the surface of the work function layer.

5. The semiconductor structure according to claim 4, characterized in that The material of the work function layer includes TiAl.

6. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; A first dielectric layer and a plurality of gate structures are formed on the substrate, wherein a top surface of the first dielectric layer is higher than a top surface of the gate structure, and a first opening is provided in the first dielectric layer, and the first opening exposes a top surface of the gate structure; The gate structure comprises: a gate dielectric layer, a work function layer located on the surface of the gate dielectric layer, and a gate layer located on the surface of the work function layer; Using a selective film forming process, a conductive protective film is formed on the top surface of the gate structure exposed by the first opening; the conductive protective film covers the top surface of the gate structure; After the conductive protection film is formed, a second opening is formed in the first dielectric layer, wherein the second opening exposes the top surface of the source-drain structure.

7. The method for forming a semiconductor structure according to claim 6, wherein: The material of the conductive protection film includes fluorine-free tungsten, the selective film forming process includes a selective atomic layer deposition process, and the reaction gas used in the selective atomic layer deposition process includes tungsten pentachloride.

8. The method for forming a semiconductor structure according to claim 7, wherein: The parameters of the selective atomic layer deposition process also include: the reaction gas used also includes hydrogen; the reaction temperature is 350 degrees Celsius to 450 degrees Celsius.

9. The method for forming a semiconductor structure according to claim 6, wherein: Also includes: After forming the second opening, a pre-treatment and cleaning step is performed on the top surface of the source / drain structure exposed by the second opening.

10. The method for forming a semiconductor structure according to claim 9, wherein: The process of the pre-treatment cleaning step includes a dry cleaning process, and the reaction gas used in the dry cleaning process includes NF3 and NH3.

11. The method for forming a semiconductor structure according to claim 9, wherein: After the pre-treatment cleaning step, the method further includes: forming a first conductive structure in the first opening, and forming a second conductive structure in the second opening.

12. The method for forming a semiconductor structure according to claim 11, wherein: The method for forming the first conductive structure and the second conductive structure includes: depositing a plug material layer in the first opening, in the second opening and on the surface of the first dielectric layer, wherein the surface of the plug material layer is higher than the surface of the first dielectric layer; and planarizing the plug material layer until the surface of the first dielectric layer is exposed.

13. The method for forming a semiconductor structure according to claim 11, wherein: The process of forming the first conductive structure and the second conductive structure includes at least one of a metal electroplating process, a chemical vapor deposition process, and a selective metal growth process.

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