Semiconductor packaging structure and preparation method thereof

Abstract

The present invention provides a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes: a carrier, a first circuit layer, a second circuit layer, a first redistribution layer, a silicon interposer, a first semiconductor group, and a second semiconductor group. The present invention connects the chips within the first semiconductor group via the silicon interposer, reducing the horizontal transmission distance between chips, thereby increasing the achievable chip density in the semiconductor package structure and improving the horizontal transmission speed between chips. Simultaneously, a structure with embedded chips and a redistribution layer replaces the traditional carrier connection, allowing the silicon interposer to be provided without increasing the device thickness. Furthermore, chip modules with different process requirements within the first and second semiconductor groups are diced and independently manufactured, reducing the manufacturing cost, design cost, and design difficulty of the semiconductor package structure and improving the reuse flexibility and manufacturing efficiency of the chip modules.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit preparation, and in particular relates to a semiconductor packaging structure and a preparation method thereof. Background Art

[0002] Currently, in pursuit of high integration, mainstream system-level chips are produced on the same wafer in the form of photolithography, with multiple computing units or chips responsible for different types of tasks being fabricated, and all units being comprehensively upgraded using advanced processes.

[0003] In traditional multi-chip heterogeneous packaging methods, such as Figure 1 Chips are typically interconnected through internal circuits on a substrate and RDLs (redistribution layers). This interconnection approach presents complex interconnects between chips, long circuit spacing, thick packages, significant signal delay and attenuation, and low transmission efficiency.

[0004] System-level chip packaging continues to integrate more functional units and larger on-chip storage, resulting in not only a surge in the number of transistors in the chip, but also a sharp increase in the chip area. This not only leads to a decrease in chip yield, but also runs counter to the current market demand for small-size portable chips. At the same time, it increases the difficulty of design and is not conducive to modular design and subsequent product updates. In addition, chips that integrate different process technologies and performance requirements are integrated on a wafer using a unified process, which greatly increases the design and preparation costs of the chip.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of this application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are explained in the background technology part of this application. Summary of the Invention

[0006] In view of the above shortcomings of the prior art, the purpose of the present invention is to provide a semiconductor packaging structure and a preparation method thereof, which are used to solve the problems of long transmission distance between chips in the semiconductor packaging structure and complex preparation of system integrated chips in the prior art.

[0007] To achieve the above object, the present invention provides a semiconductor package structure, comprising: a carrier, a first circuit layer, a second circuit layer, a first redistribution layer, a silicon interposer, a first semiconductor group, and a second semiconductor group;

[0008] The carrier includes a first plate surface and a second plate surface arranged opposite to each other, the carrier is provided with a through-groove penetrating the first plate surface and the second plate surface, and the second semiconductor group is embedded in the through-groove; the first plate surface of the carrier is formed with the first circuit layer, and the second plate surface of the carrier is formed with the second circuit layer, the first circuit layer and the second circuit layer are effectively electrically connected via conductive holes penetrating the carrier, and the second circuit layer is formed with solder balls;

[0009] The first redistribution layer includes a first wiring surface and a second wiring surface opposite to each other, the second wiring surface of the first redistribution layer being disposed on the first board surface of the carrier through the first circuit layer, and the second wiring surface of the first redistribution layer being effectively electrically connected to the second semiconductor group through the first circuit layer;

[0010] The silicon interposer includes a first interposer surface and a second interposer surface arranged opposite to each other, a conductive silicon via is provided in the silicon interposer that passes through the silicon interposer, the second interposer surface of the silicon interposer is arranged on the first wiring surface of the first redistribution layer, the conductive silicon via forms an effective electrical connection with the first redistribution layer, and the first semiconductor group is arranged on the first interposer surface of the silicon interposer and forms an effective electrical connection with the conductive silicon via.

[0011] Optionally, the silicon interposer includes multiple layers of silicon wafers, which are pressed to form the silicon interposer, and adjacent silicon wafers in the multiple layers of silicon wafers are connected via the conductive through silicon vias and metal bumps.

[0012] Optionally, the semiconductor packaging structure further includes a first solder array, a second solder array and a third solder array, the conductive silicon vias of the silicon interposer form an effective electrical connection with the first semiconductor group through the first solder array, the first wiring surface of the first redistribution layer forms an effective electrical connection with the silicon interposer through the second solder array, and the solder balls formed by the second circuit layer constitute the third solder array.

[0013] Optionally, all line widths, line spacings, apertures, and metal bump spacings in the semiconductor package structure gradually decrease from the third solder array toward the first solder array.

[0014] Optionally, the first semiconductor group includes one or more chips or / and components selected from capacitors, inductors, resistors, transistor switches, millimeter wave antennas, central processing units, graphics processing units, power management units, dynamic random access memories, flash memories, and filters. The number of the chips or / and components is greater than 1, and a transmission channel is formed between the chips or / and components through the silicon interposer.

[0015] Optionally, each chip in the first semiconductor group is a bare die core made on a single wafer, and different cores are prepared by different preset processes.

[0016] The present invention also provides a method for preparing a semiconductor packaging structure, the method comprising:

[0017] A silicon wafer is provided, comprising a first silicon surface and a second silicon surface disposed opposite to each other; a plurality of conductive through-silicon vias are provided on the first silicon surface, and a metal layer is filled in the conductive through-silicon vias until the conductive through-silicon vias are completely filled;

[0018] Disposing a first solder array on the first silicon surface, and disposing a first semiconductor group on a side of the first solder array away from the first silicon surface, so that the first semiconductor group forms an effective electrical connection with the first silicon surface through the first solder array; removing silicon wafer material from the second silicon surface until the metal layer is exposed, thereby forming a silicon interposer, wherein the first silicon surface serves as a first interposer surface of the silicon interposer, and the second silicon surface serves as a second interposer surface of the silicon interposer;

[0019] A carrier board is provided, the carrier board including a first board surface and a second board surface, a through-groove and a conductive hole are provided on the carrier board, the through-groove and the conductive hole extending through the first board surface and the second board surface; a second semiconductor group is provided in the through-groove, the second semiconductor group including an active surface and an external connection surface, the external connection surface being flush with the first board surface;

[0020] A first circuit layer is provided on the first board surface, and a second circuit layer is provided on the second board surface, wherein the active surface of the second semiconductor group is effectively electrically connected to the second circuit layer; a first redistribution layer is provided on the first circuit layer of the first board surface, wherein the first redistribution layer includes a first wiring surface and a second wiring surface that are oppositely arranged, wherein the second wiring surface is effectively electrically connected to the external surface of the second semiconductor group through the first circuit layer; and a second solder array is provided on the first wiring surface of the first redistribution layer;

[0021] The silicon interposer is disposed on the first wiring surface of the first redistribution layer, and the first semiconductor group and the second semiconductor group are effectively electrically connected via the silicon interposer, the first redistribution layer, and the first wiring layer;

[0022] A third solder array is disposed on the second board surface of the carrier board, so that the third solder array forms an effective electrical connection with the active surface of the second semiconductor group through the second circuit layer.

[0023] Optionally, a plurality of silicon wafers are provided, the plurality of silicon wafers are connected to each other through the through silicon vias and the metal bumps, and the plurality of silicon wafers are pressed to form the silicon interposer.

[0024] Optionally, the first semiconductor group is composed of different bare chip cores and / or components produced on different wafers, and different cores and / or components are produced through different preparation processes, and transmission channels are formed between the cores and / or components through the silicon interposer.

[0025] Optionally, all line widths, line spacings, apertures, and metal bump spacings in the preparation method are gradually reduced from the third solder array toward the first solder array.

[0026] As described above, the semiconductor package structure and the manufacturing method thereof of the present invention have the following beneficial effects:

[0027] The present invention connects the chips in the first semiconductor group through a silicon interposer, shortening the transmission distance between the chips in the horizontal direction, thereby increasing the chip density achievable in the semiconductor packaging structure and improving the transmission speed between the chips in the horizontal direction;

[0028] The present invention replaces the traditional connection carrier board with a structure in which the chip is embedded and a redistribution layer is provided, so that the provision of the silicon interposer does not increase the thickness of the device.

[0029] The present invention cooperates with the first semiconductor group and the second semiconductor group to core-granulate and independently prepare chip modules with different process technology requirements, reducing the preparation cost, design cost and design difficulty of the semiconductor packaging structure, and improving the reuse flexibility and preparation efficiency of the chip modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It shows a schematic diagram of a semiconductor packaging structure in the prior art.

[0031] Figure 2 It shows a structural diagram presented in step 1 of the second embodiment of the present invention.

[0032] Figure 3 It shows a structural diagram presented in step 2 of the second embodiment of the present invention.

[0033] Figure 4 It shows a structural schematic diagram of setting a second encapsulation layer in the optional step 2 in the second embodiment of the present invention.

[0034] Figure 5 It shows a structural diagram presented in step 3 in the second embodiment of the present invention.

[0035] Figure 6 The diagram shows the structure of the first anti-etching layer in step 4 of the second embodiment of the present invention.

[0036] Figure 7It is a schematic structural diagram showing the removal of the first anti-etching layer in step 4 in the second embodiment of the present invention.

[0037] Figure 8 It shows a structural diagram of setting the first redistribution layer and the second circuit layer in step 4 of the second embodiment of the present invention.

[0038] Figure 9 It shows a schematic structural diagram of the removal of the second resist layer and the third resist layer in step 4 in the second embodiment of the present invention.

[0039] Figure 10 It shows a structural diagram presented in step 5 in the second embodiment of the present invention.

[0040] Figure 11 It shows a schematic structural diagram of setting a first encapsulation layer in the optional step 5 in the second embodiment of the present invention.

[0041] Figure 12 It shows a schematic structural diagram of providing a third encapsulation layer in the optional step 5 in the second embodiment of the present invention.

[0042] Figure 13 It shows a schematic structural diagram of setting the third solder array in step 6 of the second embodiment of the present invention.

[0043] Component number description

[0044] 11. Connecting core layer; 21. Base core layer; 30. Embedded chipset; 40. Upper chipset; 50. Existing solder balls; 60. Existing dielectric layer; 70. Existing conductive layer; 80. Existing solder mask layer;

[0045] 101, organic core layer; 102, carrier through hole; 103, second dielectric layer; 104, solder resist layer; 105, second conductive layer; 106, second semiconductor group; 107, third solder array;

[0046] 2011, first dielectric layer; 2012, first conductive layer; 2013, third dielectric layer; 2014, third conductive layer; 2015, first pre-plating layer; 2016, third pre-plating layer; 202, second solder array; 203, first packaging layer; 204, first anti-etching layer; 205, third anti-etching layer;

[0047] 301, silicon interposer; 3011, silicon wafer; 3012, conductive through-silicon via; 302, first solder array; 303, second packaging layer; 304, first semiconductor group; 305, third packaging layer; 306, second anti-etching layer; 307, second pre-plating layer. DETAILED DESCRIPTION

[0048] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] For example, when describing the embodiments of the present invention, schematic diagrams illustrating device structures may be partially enlarged for ease of explanation. These schematic diagrams are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0050] For convenience of description, spatially relative terms such as "under," "below," "below," "below," "above," and "upper" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0051] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0052] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0053] Example 1:

[0054] In the prior art, such as Figure 1As shown, electrical connections are typically made between horizontal and vertical chips via a connecting substrate and RDLs (redistribution layers) grown on both sides of the substrate. The base substrate is used to house the embedded chipset 30. RDLs are required on both sides of the middle connecting substrate to vertically connect the embedded chipset 30 to the upper chipset 40. The RDLs of the middle connecting substrate are electrically connected to the embedded chipset 30 and the upper chipset 40 of the base substrate via solder balls. The bottom of the base substrate also requires an RDL and an existing solder resist layer 80 and existing solder balls 50 for electrical connection to the external system. The RDLs each include an existing dielectric layer 60 and an existing conductive layer 70 stacked on top of each other. The horizontal chips within the upper chipset 40 are electrically connected via the RDL on the upper portion of the connecting substrate. The connecting substrate includes a connecting core layer 11, and the base substrate includes a base core layer 21.

[0055] In this solution, since RDL usually uses organic matter as the dielectric layer structure, its thermal expansion coefficient is relatively high and it is easily affected by temperature during the processing, resulting in warping problems. At the same time, the shape features such as holes and lines after forming are easily affected by the chemical substances involved in the processing, resulting in high surface roughness. The above problems limit the line width and line spacing density that can be achieved by RDL, making the transmission channel distance between chips in the horizontal direction longer and the transmission speed slower. In addition, since the vertical direction uses a structure combining a carrier board and RDL to connect the chips, and the formation of the carrier board requires a core layer for support, the existence of the connecting core layer 11 connecting the carrier board will make the packaging structure in the prior art require a higher thickness to achieve electrical connection in the vertical direction.

[0056] like Figure 13 As shown, the present invention provides a semiconductor package structure, including: a carrier, a first circuit layer, a second circuit layer, a first redistribution layer, a silicon interposer 301, a first semiconductor group 304 and a second semiconductor group 106;

[0057] The carrier includes a first surface and a second surface disposed opposite to each other. A through-groove is provided in the carrier that penetrates the first and second surfaces, and the second semiconductor group 106 is embedded in the through-groove. A first circuit layer is formed on the first surface of the carrier, and a second circuit layer is formed on the second surface of the carrier. The first and second circuit layers are effectively electrically connected via conductive vias penetrating the carrier. Solder balls are formed on the second circuit layer.

[0058] The first redistribution layer includes a first wiring surface and a second wiring surface opposite to each other. The second wiring surface of the first redistribution layer is disposed on the first surface of the carrier through the first circuit layer. The second wiring surface of the first redistribution layer forms an effective electrical connection with the second semiconductor group 106 through the first circuit layer.

[0059] The silicon interposer 301 includes a first interposer surface and a second interposer surface arranged opposite to each other. A conductive silicon via 3012 is provided in the silicon interposer 301 and passes through the silicon interposer 301. The second interposer surface of the silicon interposer 301 is provided on the first wiring surface of the first redistribution layer. The conductive silicon via 3012 forms an effective electrical connection with the first redistribution layer. The first semiconductor group 304 is provided on the first interposer surface of the silicon interposer 301 and forms an effective electrical connection with the conductive silicon via 3012.

[0060] The present invention uses a silicon interposer 301 to replace the RDL structure to achieve electrical connection between chips in the horizontal direction. Since silicon material has a low thermal expansion coefficient and a high Young's modulus, the silicon interposer 301 is less affected by temperature during processing. Therefore, within the same area, the silicon interposer 301 can achieve a higher line width and line spacing density than RDL without causing obvious warping problems. Under the setting of the same line density, a smaller package size can be achieved, while the transmission speed between chips is improved, and a larger data bandwidth is achieved. At the same time, compared with the organic material of RDL, the chemical properties of silicon are more stable, and its formed shape characteristics are not easily affected by the chemicals involved in the processing process, and can achieve lower surface roughness. In addition, because a highly insulating silicon dioxide layer is easily formed on the surface of silicon, the electron mobility at the non-conductive layer position in the silicon interposer 301 is greatly reduced. It is capable of long-term current conduction in a smaller line width and line spacing without causing problems such as short circuit and open circuit due to electron migration. Compared with RDL, the reliability of the packaging structure is stronger. Finally, in the present invention, the electrical connection between chips in the vertical direction can be achieved directly through the RDL grown on the carrier of the embedded chip and the matching structure of the silicon interposer 301. Since the RDL can be directly connected to the embedded chip for conduction, there is no need to lead the electrical signal of the embedded chip from the carrier to the connecting carrier through solder balls in the prior art. At the same time, the line density of the silicon interposer 301 can be higher, so the structure can be thinner and occupy less space, which is conducive to the use of the packaging structure in small-sized portable products. At the same time, a higher transmission speed can be achieved in the vertical direction to meet the needs of application fields with ultra-large data throughput such as cloud infrastructure, 5G, autonomous driving and artificial intelligence.

[0061] As an example, the thickness of the silicon interposer 301 is less than 150 micrometers. Specifically, the size of the silicon interposer 301 can be determined according to the number and size of chips to be connected.

[0062] As an example, the diameter of the conductive through silicon vias 3012 is 10-50 micrometers. Specifically, the size and number of the conductive through silicon vias 3012 can be determined according to the number and size of chips that need to be connected.

[0063] As an example, silicon interposer 301 includes multiple layers of silicon wafers 3011, which are pressed together to form silicon interposer 301. Adjacent silicon wafers 3011 within the multilayer silicon wafers 3011 are connected via conductive through-silicon vias 3012 and metal bumps. Specifically, in the present invention, silicon interposer 301 only requires one layer of wiring to enable multi-chip communication. The number of layers of silicon wafers 3011 can be adjusted based on the number of connections required between chips within the package structure.

[0064] Optionally, an insulating film is provided between the metal layer in the conductive through-silicon via 3012 and the silicon wafer 3011. Preferably, the insulating film is made of silicon dioxide. As an insulating layer, the insulating film can completely electrically isolate the silicon wafer 3011. Furthermore, silicon dioxide has good bonding strength with silicon, and exhibits low stress and high breakdown voltage, thereby improving the device performance and reliability of the semiconductor package structure.

[0065] As an example, the semiconductor packaging structure also includes a first solder array 302, a second solder array 202 and a third solder array 107. The conductive silicon vias 3012 of the silicon interposer 301 form an effective electrical connection with the first semiconductor group 304 through the first solder array 302, the first wiring surface of the first redistribution layer forms an effective electrical connection with the silicon interposer 301 through the second solder array 202, and the solder balls formed by the second circuit layer constitute the third solder array 107.

[0066] Specifically, a first packaging layer 203 is arranged between the second interposer surface of the silicon interposer 301 and the first wiring surface of the first redistribution layer. The first packaging layer 203 fills the gaps in the second solder array 202 to prevent the second interposer surface and the first wiring surface from being affected by external factors such as oxidation and moisture, while reducing the possibility of short circuits between solder balls in the first solder array 302, thereby improving the reliability of the semiconductor packaging structure; the second packaging layer 303 is filled between the gaps in the first solder array 302, which plays a similar protective role as mentioned above on the surface between the first semiconductor group 304 and the silicon interposer 301; a third packaging layer 305 is provided on all surrounding surfaces of the first redistribution layer, the silicon interposer 301, the first semiconductor group 304 and the connection structure therebetween, which plays a similar protective role as mentioned above on the overall packaging structure.

[0067] Specifically, the filling layer material includes but is not limited to epoxy resin, high-performance phenolic resin, silicon powder, and halogen.

[0068] As an example, all line widths, line spacings, apertures, and metal bump spacings in the semiconductor package structure gradually decrease from the third solder array 107 toward the first solder array 302. Specifically, n conductive layers are provided in the first redistribution layer, where n is an integer greater than 1. The third solder array 107 is the first layer, and the number of conductive layers increases toward the first solder array 302. The conductive layer line width, line spacing, via aperture, and via spacing of the nth layer are all less than or equal to the dimensions corresponding to the (n-1)th layer.

[0069] Optionally, the semiconductor packaging structure may also be configured as a fan-in packaging structure, and the corresponding line width and line spacing may be adjusted according to requirements.

[0070] As an example, the first semiconductor group 304 includes one or more chips or / and components selected from the group consisting of capacitors, inductors, resistors, transistor switches, millimeter-wave antennas, central processing units (CPUs), graphics processing units (GPUs), power management units (PMUs), dynamic random access memory (DRAM), flash memory, and filters. The number of chips or / and components is greater than one, and a transmission channel is formed between the chips or / and components via a silicon interposer 301. The present invention, through the provision of a silicon interposer 301, can achieve compatibility with different types of chips and components, enabling system-level chip connectivity.

[0071] As an example, each chip in the first semiconductor group 304 is a bare die core made on a single wafer, and different cores are prepared by different preset processes. Specifically, modules such as logic computing units rely on advanced processes to achieve more I / O ports (input / output ports) and smaller line width / line spacing (such as 7 / 7nm process), and can be prepared on different wafers with other modules that do not have high process requirements (such as 28 / 28nm process). The present invention cores the chips in the first semiconductor group 304, uses separate wafers to make cores that require different preparation processes, and then connects and packages them through a semiconductor packaging structure, so that core designs of different processes can be standardized for different system-level chip designs, thereby reducing design costs and design difficulty. At the same time, because they can be prepared separately, the overall preparation time is shortened and the preparation efficiency is improved. Specifically, the second semiconductor group 106 can also use the same setting method as above.

[0072] Specifically, the first solder arrays 302 for connecting the bottoms of the chips and components in the first semiconductor group 304 are located on the same horizontal plane, and the bottom surface of the first solder array 302 is flush with the first interposer surface of the silicon interposer 301 .

[0073] As an example, the first circuit layer includes a first dielectric layer 2011 and a first conductive layer 2012 stacked on each other, a second dielectric layer 103 and a second conductive layer 105 stacked on each other, a first pre-plating layer 2015 is arranged between the first dielectric layer 2011 and the first conductive layer 2012, and a second pre-plating layer 307 is arranged between the second dielectric layer 103 and the second conductive layer 105; the first redistribution layer includes a third dielectric layer 2013 and a third conductive layer 2014 stacked on each other, and a third pre-plating layer 2016 is arranged between the third dielectric layer 2013 and the third conductive layer 2014.

[0074] Specifically, the carrier includes an organic core layer 101 and a carrier through-hole 102. The carrier through-hole 102 penetrates the organic core layer 101, so that the first circuit layer and the second circuit layer form an effective electrical connection through the organic core layer 101, so that the transmission path in the circuit of the external semiconductor packaging structure that does not need to be processed by the second semiconductor group 106 directly passes through the carrier through-hole 102 to form an effective electrical connection with the first circuit layer, the first redistribution layer, the silicon interposer 301, and the first semiconductor group 304, wherein the organic core layer 101 plays a supporting role for the first circuit layer and the second circuit layer.

[0075] Optionally, a solder resist layer 104 is provided between the solder balls of the third solder array 107 to reduce the effects of external factors such as oxidation and moisture on the second board surface, while also reducing the possibility of short circuits between the solder balls within the third solder array 107 and improving the reliability of the semiconductor package structure. Specifically, materials for the solder resist layer 104 include, but are not limited to, acrylic resin, epoxy resin, and silicone resin, and the solder resist layer 104 can be prepared in dry film or wet film.

[0076] Example 2:

[0077] The present invention provides a method for preparing a semiconductor packaging structure, the preparation method comprising:

[0078] Step 1: Providing a silicon wafer 3011, wherein the silicon wafer 3011 includes a first silicon surface and a second silicon surface disposed opposite to each other; providing a plurality of conductive through-silicon vias 3012 on the first silicon surface, and filling the conductive through-silicon vias 3012 with a metal layer until the conductive through-silicon vias 3012 are completely filled;

[0079] Step 2: Dispose a first solder array 302 on the first silicon surface, and dispose a first semiconductor group 304 on a side of the first solder array 302 away from the first silicon surface. The first semiconductor group 304 forms an effective electrical connection with the first silicon surface through the first solder array 302. Remove the silicon wafer 3011 material on the second silicon surface to expose the metal layer, thereby forming a silicon interposer 301. The first silicon surface serves as the first interposer surface of the silicon interposer 301, and the second silicon surface serves as the second interposer surface of the silicon interposer 301.

[0080] Step 3: Providing a carrier board, the carrier board including a first board surface and a second board surface, and providing a through-groove and a conductive hole on the carrier board, so that the through-groove and the conductive hole penetrate the first board surface and the second board surface; disposing a second semiconductor group 106 in the through-groove, the second semiconductor group 106 including an active surface and an external surface, and the external surface is flush with the first board surface;

[0081] Step 4: Disposing a first circuit layer on the first board surface, disposing a second circuit layer on the second board surface, and forming an effective electrical connection between the active surface of the second semiconductor group 106 and the second circuit layer; disposing a first redistribution layer on the first circuit layer of the first board surface, the first redistribution layer including a first wiring surface and a second wiring surface disposed opposite each other, the second wiring surface forming an effective electrical connection with the external surface of the second semiconductor group 106 through the first circuit layer; and disposing a second solder array 202 on the first wiring surface of the first redistribution layer;

[0082] Step 5: Disposing a silicon interposer 301 on the first wiring surface of the first redistribution layer, and forming an effective electrical connection between the first semiconductor group 304 and the second semiconductor group 106 through the silicon interposer 301, the first redistribution layer, and the first wiring layer;

[0083] Step 6: Dispose a third solder array 107 on the second surface of the carrier, so that the third solder array 107 forms an effective electrical connection with the active surface of the second semiconductor group 106 through the second circuit layer.

[0084] The preparation method of the semiconductor packaging structure of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the preparation method sequence of the semiconductor packaging structure protected by the present invention, and those skilled in the art may change it according to the actual preparation steps.

[0085] First, if Figure 2 As shown, step 1 is performed to provide a silicon wafer 3011, which includes a first silicon surface and a second silicon surface arranged opposite to each other; a plurality of conductive silicon vias 3012 are set on the first silicon surface, and a metal layer is filled in the conductive silicon vias 3012 until the conductive silicon vias 3012 are completely filled.

[0086] Optionally, before providing the metal layer, an insulating film is formed in the conductive through-silicon via 3012. Preferably, the insulating film is made of silicon dioxide. As an insulating layer, the insulating film can completely electrically isolate the silicon wafer 3011. Furthermore, silicon dioxide has good bonding strength with silicon, and exhibits low stress and high breakdown voltage, thereby improving the device performance and reliability of the semiconductor package structure.

[0087] As an example, a plurality of silicon wafers 3011 are provided, and the plurality of silicon wafers 3011 are connected to each other through conductive silicon vias 3012 and metal bumps. The plurality of silicon wafers 3011 are pressed to form a silicon interposer 301 .

[0088] Optionally, the metal layer material in the conductive silicon via 3012 can be a conductive material such as copper, tungsten, or polysilicon.

[0089] Then, if Figure 2 As shown, step 2 is performed, where a first solder array 302 is disposed on the first silicon surface, and a first semiconductor group 304 is disposed on the side of the first solder array 302 facing away from the first silicon surface. The first semiconductor group 304 forms an effective electrical connection with the first silicon surface through the first solder array 302. The silicon wafer 3011 material on the second silicon surface is removed until the metal layer is exposed, thereby forming a silicon interposer 301. The first silicon surface serves as the first interposer surface of the silicon interposer 301, and the second silicon surface serves as the second interposer surface of the silicon interposer 301. The present invention utilizes vertical interconnection through silicon vias 3012 to reduce the interconnect length between chips, minimize transmission signal delay, and reduce parasitic capacitance and inductance, thereby increasing bandwidth and enabling high-speed communication and miniaturized device integration.

[0090] Specifically, when multiple silicon wafers 3011 are pressed to form the silicon interposer 301 , the exposed surface of the silicon wafer 3011 closest to the first solder array 302 is the first interposer surface, and the exposed surface of the silicon wafer 3011 farthest from the first solder array 302 is the second interposer surface.

[0091] As an example, the first semiconductor group 304 is composed of different bare chip cores and / or components made on different wafers. Different cores and / or components are made through different preparation processes, and transmission channels are formed between the cores and / or components through the silicon interposer 301.

[0092] As an example, after forming the silicon interposer 301, the second encapsulation layer 303 is filled between the gaps in the first solder array 302 to prevent the surface between the first semiconductor group 304 and the silicon interposer 301 from being affected by external factors such as oxidation and moisture. This also reduces the possibility of short circuits between solder balls within the first solder array 302, thereby improving the reliability of the semiconductor package structure. Optionally, the step of filling the second encapsulation layer 303 can also be performed in other steps after forming the silicon interposer 301 as needed. The second encapsulation layer 303 can also not only fill the gaps in the first solder array 302, but also cover the surface of the first semiconductor group 304 and / or the silicon interposer 301, serving as a package protection layer, thereby improving the efficiency of the package layer preparation and the simplicity of the package structure, thereby reducing the potential gaps between the package structure and reducing the potential factors of package defects.

[0093] Then, if Figure 4As shown, step 3 is performed, providing a carrier substrate. The carrier substrate includes a first surface and a second surface. Through-grooves and conductive vias are provided on the carrier substrate, extending through the first and second surfaces. A second semiconductor group 106 is disposed within the through-grooves. The second semiconductor group 106 includes an active surface and an external surface, with the external surface flush with the first surface. By aligning the external surface with the first surface, the present invention ensures that transmission signals from the external connection of the semiconductor package structure and transmission signals from the second semiconductor group 106 are transmitted to the first semiconductor group 304 in near-synchronous fashion, thereby improving the accuracy of data transmission and processing and facilitating the growth of RDLs on the carrier substrate.

[0094] Specifically, the carrier also includes an organic core layer 101 and a carrier through hole 102. The carrier through hole 102 penetrates the organic core layer 101. The organic core layer 101 can be a glass fiber cloth coated resin copper clad plate. The resin includes but is not limited to epoxy resin, phenolic resin, and polyester resin.

[0095] Specifically, after the second semiconductor group 106 is provided, a filling layer is provided between the second semiconductor group 106 and the through-groove. Preferably, the filling layer is made of ABF material, which has good fluidity and heat dissipation properties, facilitating the installation and heat dissipation of the second semiconductor group 106.

[0096] Then, if Figure 5 As shown, step 4 is performed, a first circuit layer is set on the first board surface, and a second circuit layer is set on the second board surface, and the active surface of the second semiconductor group 106 is effectively electrically connected to the second circuit layer; a first redistribution layer is set on the first circuit layer of the first board surface, and the first redistribution layer includes a first wiring surface and a second wiring surface that are relatively set, and the second wiring surface is effectively electrically connected to the external surface of the second semiconductor group 106 through the first circuit layer; a second solder array 202 is set on the first wiring surface of the first redistribution layer.

[0097] Specifically, the carrier through-hole 102 enables the first circuit layer and the second circuit layer to form an effective electrical connection through the organic core layer 101, so that the circuit of the external semiconductor package structure does not need to pass through the transmission path of the second semiconductor group 106 and directly forms an effective electrical connection with the first circuit layer, the first redistribution layer, the silicon interposer 301, and the first semiconductor group 304 through the carrier through-hole 102, wherein the organic core layer 101 plays a supporting role for the first circuit layer and the second circuit layer.

[0098] Specifically, the steps for preparing the first circuit layer are as follows: Figure 6As shown, a first dielectric layer 2011 is provided on the first surface of the carrier board, a preset groove is provided in the first dielectric layer 2011, a first pre-plated layer 2015 is provided on the first dielectric layer 2011 and the surface of the groove, a first anti-etching layer 204 is provided on the first pre-plated layer 2015, the first anti-etching layer 204 is patterned to expose the first pre-plated layer 2015 in the groove and the first pre-plated layer 2015 at other preset positions, a first conductive layer 2012 is provided on the surface of the exposed first pre-plated layer 2015, the first conductive layer 2012 fills the groove and the gaps patterned by the first anti-etching layer 204 at the preset positions, and the surface of the first conductive layer 2012 is flush with the surface of the first anti-etching layer 204; then as shown in FIG. Figure 7 As shown, the first resist layer 204 is removed.

[0099] Specifically, if Figure 8 and Figure 9 As shown, after the first circuit layer is prepared, the preparation steps are repeated to sequentially form a third dielectric layer 2013, a groove, a third pre-plating layer 2016, a patterned third resist layer 205, and a third conductive layer 2014 on the surface of the first circuit layer. The third resist layer 205 is then removed, thereby forming a first redistribution layer. Optionally, multiple layers of pre-plating layers, conductive layers, and dielectric layers can be formed as needed to form a first redistribution layer including multiple circuit layers to meet chip connection requirements.

[0100] Specifically, if Figure 8 and Figure 9 As shown, the preparation method also includes setting a second circuit layer on the second board surface of the carrier board. The preparation steps are consistent with the preparation steps of the first circuit layer. A second dielectric layer 103, a groove, a second pre-plating layer 307, a patterned second anti-etching layer 306, and a second conductive layer 105 are sequentially prepared on the second board surface of the carrier board, and then the second anti-etching layer 306 is removed to form the second circuit layer.

[0101] Specifically, the materials of the first conductive layer 2012 , the second conductive layer 105 , and the third conductive layer 2014 include, but are not limited to, electrolytic copper and rolled copper.

[0102] Preferably, the material ductility of the first conductive layer 2012, the second conductive layer 105, and the third conductive layer 2014 is greater than or equal to 22%, and the thickness is 4-8 microns; the ratio of the copper plating thickness of the first conductive layer 2012, the second conductive layer 105, and the third conductive layer 2014 to the line width of the first circuit layer is 1:1.

[0103] Specifically, the materials of the first dielectric layer 2011 , the second dielectric layer 103 , and the third dielectric layer 2013 include, but are not limited to, PI (polyimide), ABF (Ajinomoto built-up film), and epoxy resin.

[0104] Specifically, the materials of the first resist layer 204 , the second resist layer 306 , and the third resist layer 205 include but are not limited to polymer adhesives (such as acrylic acid).

[0105] Optionally, dry or wet etching is used to remove the resist layer; the dry etching method used includes but is not limited to ion milling, reactive ion etching and plasma etching, and the etching gas used in dry etching includes but is not limited to one or more of argon, nitrogen and fluorine-based gases; the etching gas used in wet etching includes but is not limited to OH - 、SO4 2- 、CO3 2- OH - 、H + a compound or a mixture containing H2O2.

[0106] Preferably, the thickness of the first dielectric layer 2011 , the second dielectric layer 103 , and the third dielectric layer 2013 is 5-10 microns, the diameter of the grooves is 30-40 microns, and the spacing between the grooves is 60-80 microns.

[0107] Preferably, the first pre-plating layer 2015 , the second pre-plating layer 307 , and the third pre-plating layer 2016 include a titanium layer and a copper layer. During the preparation process, a titanium layer is first formed on the surface of the groove and the dielectric layer, and then a copper layer is formed on the titanium layer.

[0108] Preferably, the thickness of the first pre-plating layer 2015 , the second pre-plating layer 307 , and the third pre-plating layer 2016 is 300-500 nanometers.

[0109] Then, if Figure 10 As shown, step 5 is performed to dispose the silicon interposer 301 on the first wiring surface of the first redistribution layer, and an effective electrical connection is formed between the first semiconductor group 304 and the second semiconductor group 106 through the silicon interposer 301, the first redistribution layer, and the first wiring layer.

[0110] Specifically, after step 5 is completed, a filling layer is set between the second interposer surface of the silicon interposer 301 and the first wiring surface of the first redistribution layer. The filling layer fills the gaps in the second solder array 202 to prevent the second interposer surface and the first wiring surface from being affected by external factors such as oxidation and moisture, while reducing the possibility of short circuits between solder balls in the first solder array 302, thereby improving the reliability of the semiconductor packaging structure.

[0111] Specifically, during the preparation of the filling layer, the baking temperature can be between 120°C and 150°C, and the preheating temperature is below 80°C. The temperature control is based on the premise of not affecting the reliability of the packaging structure.

[0112] Optionally, the filling layer may be filled using methods including, but not limited to, transfer molding, injection molding, and pre-molding techniques. Specifically, a "S" or "L"-shaped filling direction is used during the filling process to avoid voids between gaps and reduce the risk of device damage due to current concentration.

[0113] Then, if Figure 13 As shown, step 6 is performed to dispose a third solder array 107 on the second surface of the carrier, so that the third solder array 107 forms an effective electrical connection with the active surface of the second semiconductor group 106 through the second circuit layer.

[0114] Preferably, the solder material of the first solder array 302 , the second solder array 202 , and the third solder array 107 is a silver-tin alloy, which provides good electrical connection by utilizing the good viscosity, wettability, and diffusivity of tin.

[0115] Optionally, after providing the third solder array 107, a solder resist layer 104 is provided between the solder balls of the third solder array 107 to reduce the effects of external factors such as oxidation and moisture on the second board surface, while also reducing the possibility of short circuits between the solder balls within the third solder array 107, thereby improving the reliability of the semiconductor package structure. Specifically, materials for the solder resist layer 104 include, but are not limited to, acrylic resin, epoxy resin, and silicone resin, and preparation methods include, but are not limited to, vacuum lamination or coating. The prepared solder resist layer 104 can be either dry film or wet film.

[0116] As an example, all line widths, line spacings, apertures, and metal bump spacings in the fabrication method gradually decrease from the third solder array 107 toward the first solder array 302. The present invention achieves a high-density I / O port for the first semiconductor group 304 by reducing the line spacing from the third solder array 107 toward the first solder array 302, thereby achieving a better fan-out effect.

[0117] In summary, the semiconductor packaging structure and preparation method thereof of the present invention can connect the chips in the first semiconductor group through a silicon interposer, shortening the transmission distance between chips in the horizontal direction, thereby increasing the achievable chip density in the semiconductor packaging structure and increasing the transmission speed between chips in the horizontal direction; at the same time, the structure of embedded chips and setting a redistribution layer is used to replace the traditional connection carrier, so that the setting of the silicon interposer does not increase the thickness of the device; in addition, the chip modules with different process requirements in the first semiconductor group and the second semiconductor group are granulated and prepared independently, thereby reducing the preparation cost, design cost and design difficulty of the semiconductor packaging structure, and improving the reuse flexibility and preparation efficiency of the chip modules.

[0118] Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0119] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that: The semiconductor package structure includes: a carrier, a first circuit layer, a second circuit layer, a first redistribution layer, a silicon interposer, a first semiconductor group, and a second semiconductor group; The carrier includes a first plate surface and a second plate surface arranged opposite to each other, the carrier is provided with a through groove and a conductive hole penetrating the first plate surface and the second plate surface, and the second semiconductor group is embedded in the through groove; the first plate surface of the carrier is formed with the first circuit layer, and the second plate surface of the carrier is formed with the second circuit layer, the first circuit layer and the second circuit layer are effectively electrically connected through the conductive hole penetrating the carrier, and the second circuit layer is formed with solder balls; The first redistribution layer includes a first wiring surface and a second wiring surface opposite to each other, the second wiring surface of the first redistribution layer being disposed on the first board surface of the carrier through the first circuit layer, and the second wiring surface of the first redistribution layer being effectively electrically connected to the second semiconductor group through the first circuit layer; The silicon interposer includes a first interposer surface and a second interposer surface that are oppositely disposed. A conductive through-silicon via (TSV) is disposed in the silicon interposer and penetrates the silicon interposer. The second interposer surface of the silicon interposer is disposed on the first wiring surface of the first redistribution layer. The conductive TSV is effectively electrically connected to the first redistribution layer. The first semiconductor group is disposed on the first interposer surface of the silicon interposer and is effectively electrically connected to the conductive TSV. The silicon interposer comprises a plurality of silicon wafers, which are pressed to form the silicon interposer. Adjacent silicon wafers in the plurality of silicon wafers are connected via the conductive through silicon vias and metal bumps.

2. The semiconductor package structure according to claim 1, wherein: The semiconductor packaging structure also includes a first solder array, a second solder array and a third solder array. The conductive silicon vias of the silicon interposer form an effective electrical connection with the first semiconductor group through the first solder array, the first wiring surface of the first redistribution layer forms an effective electrical connection with the silicon interposer through the second solder array, and the solder balls formed by the second circuit layer constitute the third solder array.

3. The semiconductor package structure according to claim 2, wherein: All line widths, line spacings, apertures, and metal bump spacings in the semiconductor package structure gradually decrease from the third solder array toward the first solder array.

4. The semiconductor package structure according to any one of claims 1 to 3, wherein: The first semiconductor group includes one or more chips or / and components selected from capacitors, inductors, resistors, transistor switches, millimeter wave antennas, central processing units, graphics processing units, power management units, dynamic random access memories, flash memories, and filters. The number of the chips or / and components is greater than one, and a transmission channel is formed between the chips or / and components through the silicon interposer.

5. The semiconductor package structure according to claim 4, wherein: Each chip in the first semiconductor group is a bare die core made on a single wafer, and different cores are prepared by different preset processes.

6. A method for preparing a semiconductor packaging structure, characterized in that: The preparation method comprises: Arranging a plurality of silicon wafers, disposing a plurality of conductive through-silicon vias on a silicon surface of each of the silicon wafers, connecting the plurality of silicon wafers via metal layers and metal bumps completely filled in the conductive through-silicon vias, and pressing the plurality of silicon wafers to form a silicon interposer precursor, the silicon interposer precursor comprising a first silicon surface and a second silicon surface disposed opposite to each other; Disposing a first solder array on the first silicon surface, and disposing a first semiconductor group on a side of the first solder array away from the first silicon surface, so that the first semiconductor group forms an effective electrical connection with the first silicon surface through the first solder array; removing silicon wafer material from the second silicon surface until the metal layer is exposed, thereby forming a silicon interposer, wherein the first silicon surface serves as a first interposer surface of the silicon interposer, and the second silicon surface serves as a second interposer surface of the silicon interposer; A carrier board is provided, the carrier board including a first board surface and a second board surface, a through-groove and a conductive hole are provided on the carrier board, the through-groove and the conductive hole extending through the first board surface and the second board surface; a second semiconductor group is provided in the through-groove, the second semiconductor group including an active surface and an external connection surface, the external connection surface being flush with the first board surface; A first circuit layer is provided on the first board surface, and a second circuit layer is provided on the second board surface, wherein the active surface of the second semiconductor group is effectively electrically connected to the second circuit layer; a first redistribution layer is provided on the first circuit layer of the first board surface, wherein the first redistribution layer includes a first wiring surface and a second wiring surface that are oppositely arranged, wherein the second wiring surface is effectively electrically connected to the external surface of the second semiconductor group through the first circuit layer; and a second solder array is provided on the first wiring surface of the first redistribution layer; The silicon interposer is disposed on the first wiring surface of the first redistribution layer, and the first semiconductor group and the second semiconductor group are effectively electrically connected via the silicon interposer, the first redistribution layer, and the first wiring layer; A third solder array is disposed on the second board surface of the carrier board, so that the third solder array forms an effective electrical connection with the active surface of the second semiconductor group through the second circuit layer.

7. The method for preparing a semiconductor package structure according to claim 6, wherein: The first semiconductor group is composed of different bare chip cores and / or components produced on different wafers, and different cores and / or components are produced through different preparation processes. Transmission channels are formed between the cores and / or components through the silicon interposer.

8. The method for preparing a semiconductor package structure according to any one of claims 6 to 7, wherein: In the preparation method, all line widths, line spacings, apertures, and metal bump spacings are gradually reduced from the third solder array toward the first solder array.

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