Memory and method of manufacturing the same, memory system

Abstract

The embodiment of the present disclosure discloses a memory and a manufacturing method thereof, and a memory system. The manufacturing method of the memory comprises the following steps: providing a semiconductor layer, the semiconductor layer is provided with a plurality of transistor units, the transistor units comprise a first transistor and a second transistor which are symmetrically distributed along a second direction; the first transistor and the second transistor each comprise a semiconductor body extending along a first direction, a gate structure covering one side of the semiconductor body, and a first electrode and a second electrode respectively at two end portions of the semiconductor body along the first direction; the first direction is the thickness direction of the semiconductor layer; a metal compound material layer is deposited on the semiconductor layer by a deposition process; part of the metal compound material layer is removed to form a plurality of connection structures; each connection structure is connected with a first electrode; and a storage structure is formed on the connection structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a memory and a method for manufacturing the same, and a memory system. Background Technology

[0002] The memory array architecture of Dynamic Random Access Memory (DRAM) consists of an array of memory cells (i.e., 1T1C memory cells) each containing one transistor and one capacitor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.

[0003] As the size of dynamic random access memory (DRAM) continues to shrink, so too does the size of transistors. Ensuring a good connection between capacitors and transistors in DRAM has become a pressing issue.

[0004] Public content

[0005] In view of this, the present disclosure provides a memory, a method for manufacturing the same, and a memory system.

[0006] According to one aspect of this disclosure, a method for manufacturing a memory is provided, comprising:

[0007] A semiconductor layer is provided, wherein a plurality of transistor units are disposed therein, the transistor units including a first transistor and a second transistor symmetrically distributed along a second direction; the first transistor and the second transistor each include a semiconductor body extending along a first direction, a gate structure covering one side of the semiconductor body, and a first electrode and a second electrode respectively located at two ends of the semiconductor body along the first direction; the first direction is the thickness direction of the semiconductor layer.

[0008] A metal compound material layer is deposited on the semiconductor layer using a deposition process.

[0009] A portion of the metal compound material layer is removed to form multiple connection structures; each connection structure is connected to a first electrode.

[0010] A storage structure is formed on the connection structure.

[0011] In the above scheme, the plurality of transistor units are arranged in an array in the second direction and the third direction, and a first insulating layer is formed between two adjacent rows of transistor units arranged along the third direction; the second direction and the third direction are both perpendicular to the first direction, and the second direction intersects the third direction.

[0012] In the above scheme, the width of the connection structure in the second direction is greater than the width of the first electrode in the second direction.

[0013] In the above scheme, the material of the metal compound material layer includes tungsten silicide and tungsten germanide.

[0014] In the above scheme, the deposition of a metal compound material layer on the semiconductor layer using a deposition process includes:

[0015] A metal compound material layer is deposited on the semiconductor layer using a physical vapor deposition process.

[0016] In the above scheme, the removal of part of the metal compound material layer to form multiple connection structures includes:

[0017] A mask layer is formed on the metal compound material layer;

[0018] By using the mask layer and an etching process, a portion of the metal compound material layer is removed, while at least the metal compound material layer on the first electrode is retained, forming multiple interconnect structures.

[0019] In the above scheme, the semiconductor layer has a first surface and a second surface opposite to each other in a first direction; the plurality of transistor units are formed on the first surface;

[0020] The method further includes:

[0021] The semiconductor layer is thinned from the second side to expose the second electrode;

[0022] Multiple bit lines are formed; the multiple bit lines are parallel to each other and extend along the second direction; each bit line is connected to the second electrode of each transistor in a row of transistor units arranged along the second direction.

[0023] According to another aspect of this disclosure, a memory is provided, comprising:

[0024] A semiconductor layer having a plurality of transistor units disposed therein, the transistor units including a first transistor and a second transistor symmetrically distributed along a second direction; the first transistor and the second transistor each include a semiconductor body extending along a first direction, a gate structure covering one side of the semiconductor body, and a first electrode and a second electrode respectively at two ends of the semiconductor body along the first direction; the first direction is the thickness direction of the semiconductor layer.

[0025] Multiple connection structures are formed by depositing a metal compound material layer on the semiconductor layer using a deposition process and then removing a portion of the metal compound material layer; each connection structure is connected to a first electrode.

[0026] Multiple storage structures, each connected to a connection structure.

[0027] In the above scheme, the plurality of transistor units are arranged in an array in the second direction and the third direction, and a first insulating layer is formed between two adjacent rows of transistor units arranged along the third direction; the second direction and the third direction are both perpendicular to the first direction, and the second direction intersects the third direction.

[0028] In the above scheme, the width of the connection structure in the second direction is greater than the width of the first electrode in the second direction.

[0029] In the above scheme, the memory further includes:

[0030] Multiple bit lines; the multiple bit lines are parallel to each other and extend along the second direction; each bit line is connected to the second electrode of each transistor in a row of transistor cells arranged along the second direction.

[0031] In the above scheme, the material of the metal compound material layer includes tungsten silicide and tungsten germanide.

[0032] In the above scheme, the memory includes dynamic random access memory, and the storage structure includes storage capacitors.

[0033] According to another aspect of this disclosure, a memory system is provided, comprising: one or more memories as described in any of the above embodiments; and

[0034] A memory controller, which is coupled to the memory and controls the memory.

[0035] This disclosure provides a memory and its fabrication method, as well as a memory system. The fabrication method includes: providing a semiconductor layer, wherein a plurality of transistor units are disposed in the semiconductor layer, each transistor unit including a first transistor and a second transistor symmetrically distributed along a second direction; each of the first and second transistors includes a semiconductor body extending along a first direction, a gate structure covering one side of the semiconductor body, and a first electrode and a second electrode respectively located at two ends of the semiconductor body along the first direction; the first direction is the thickness direction of the semiconductor layer; depositing a metal compound material layer on the semiconductor layer using a deposition process; removing a portion of the metal compound material layer to form a plurality of interconnect structures; each interconnect structure being coupled to a first electrode; and forming a memory structure on the interconnect structures. In this disclosure, by directly depositing a metal compound material layer on the semiconductor layer and removing a portion of the metal compound material layer to form interconnect structures, the problem of small-size effect occurring when directly using the ends of the semiconductor body to form interconnect structures, due to the small width of the ends of the semiconductor body in the second direction, and the occurrence of breakage and aggregation of the interconnect structures under high temperature conditions, resulting in poor connection effect of the formed interconnect structures and high contact resistance between the memory structure and the transistors, thereby reducing the performance of the memory, can be improved. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the circuit connection of a DRAM transistor provided in an embodiment of this disclosure;

[0037] Figure 2 This is a three-dimensional structural diagram of a memory provided in an embodiment of the present disclosure;

[0038] Figure 3 A cross-sectional schematic diagram of a memory provided in an embodiment of this disclosure;

[0039] Figure 4a A schematic diagram illustrating the relationship between annealing temperature and crystal phase of a metal compound provided in this embodiment of the disclosure;

[0040] Figure 4b A schematic diagram illustrating the relationship between metal silicide thickness or linewidth and temperature, provided in an embodiment of this disclosure.

[0041] Figure 5a This is a schematic diagram of a connection structure exhibiting agglomeration phenomenon, provided in an embodiment of this disclosure.

[0042] Figure 5b This is a schematic diagram illustrating a connection structure fracture phenomenon provided in an embodiment of the present disclosure.

[0043] Figure 6A schematic flowchart illustrating a method for manufacturing a memory according to an embodiment of this disclosure;

[0044] Figures 7-10 A cross-sectional schematic diagram of the manufacturing process of another memory provided in an embodiment of this disclosure. Detailed Implementation

[0045] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the implementation methods set forth herein. Rather, these implementation methods are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0046] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0047] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0048] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0049] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0050] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0051] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0052] The memory involved in the embodiments of this disclosure includes, but is not limited to, dynamic random access memory. The following description only uses dynamic random access memory as an example.

[0053] However, it should be noted that the following description of dynamic random access memory is only for illustrating this disclosure and is not intended to limit the scope of this disclosure.

[0054] In some embodiments of this disclosure, the dynamic random access memory is composed of multiple memory cell structures. Each memory cell structure mainly consists of a transistor and a memory cell (storage capacitor) controlled by the transistor. That is, the dynamic random access memory includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0055] Figure 1 This is a circuit connection diagram of a 1T1C architecture provided in an embodiment of this disclosure; Figure 2 This is a three-dimensional structural diagram of a memory provided in an embodiment of this disclosure; as shown. Figure 1 as well as Figure 2 As shown, the drain of transistor T is electrically connected to the bit line (BL), and the source of transistor T is electrically connected to one of the electrode plates of capacitor C. The other electrode plate of capacitor C can be connected to a reference voltage, which can be ground or other voltages. The gate of transistor T is connected to the word line (WL). The transistor T is turned on or off by applying a voltage through the word line WL. The bit line BL is used to perform read or write operations on transistor T when it is turned on.

[0056] As memory technology advances, the size of dynamic random access memory (DRAM) is constantly shrinking, and the size of transistors is also shrinking. This makes it increasingly difficult to create a connection structure that provides good connectivity between transistors and capacitors.

[0057] This disclosure provides a method for fabricating a memory, the method comprising: providing a semiconductor layer in which a plurality of semiconductor bodies are formed; after doping two ends of the semiconductor bodies along a first direction to form a first doped region and a second electrode; next, removing a portion of the first doped region to form a first groove; forming a metal material layer in the first groove; and performing two annealing processes to allow the metal material layer to react with the material of a portion of the first doped region to form a memory. Figure 3 The interconnect structure 109 shown is composed of a metal compound. The remaining portion, a first doped region, forms the first electrode 106 of the transistor. The semiconductor body between the first electrode 106 and the second electrode 107 forms the channel region of the transistor. Here, the first electrode 106 can be the source of the transistor, and the second electrode 107 can be the drain of the transistor.

[0058] In the memory fabrication method provided in the above embodiments, two annealing processes are required. Figure 4a This is a schematic diagram illustrating the relationship between annealing temperature and crystal phase of a metal compound provided in embodiments of this disclosure, as shown below. Figure 4a As shown, the first annealing causes the metal material layer to react with part of the first doped region to form a high-resistivity metal compound with phase C49. The reaction temperature of the first annealing is lower than T1. The second annealing requires a higher temperature to transform the phase C49 into a low-resistivity metal compound with phase C54. The reaction temperature of the second annealing is lower than T2 but higher than T1. When the reaction temperature is higher than T2, agglomeration occurs. Metal compounds, such as metal silicides, have a fatal drawback in their formation. Figure 4b This is a schematic diagram illustrating the relationship between metal silicide thickness or linewidth and temperature, as provided in the embodiments of this disclosure. Figure 4b As shown, as the thickness or linewidth of the metal silicide decreases, the critical temperature T1 for the transition from the C49 phase to the C54 phase increases, while the critical temperature T2 for the clumping of the C54 phase decreases. This can lead to a critical point where T1 = T2, or even T2 being less than T1. If T2 is less than T1, the metal silicide will directly clumpe after entering the C49 phase, and the C54 phase interval will not exist at all. In other words, the process conditions for reducing the resistivity of the metal silicide cannot be found.

[0059] Research has found that in the memory fabrication method provided in the above embodiments, when forming the metal compound, the solution provided in the above embodiments of this disclosure utilizes the first doped region at one end of the semiconductor substrate to directly react with the metal material layer to form the metal compound. Since the size of the first doped region at one end of the semiconductor substrate is small, typically a columnar body 20 nm long and 10 nm wide, a small-size effect occurs during the formation of the metal compound. Due to aggregation and continuous silicon consumption, breakage is likely to occur during subsequent heat treatment. This results in poor connection performance of the formed interconnect structure, high contact resistance between the capacitor and the transistor, and thus reduced memory performance. Furthermore, the metal compound formed by the solution provided in the above embodiments of this disclosure has low thermal stability, and problems may occur during subsequent drain activation processes, such as... Figure 5a And such as Figure 5b The agglomeration and breakage shown result in a high resistance in the formed connection structure. The metal compounds formed using the schemes provided in the above embodiments generally include nickel silicide, titanium silicide, and cobalt silicide. Nickel silicide has low thermal stability, while titanium silicide and cobalt silicide will experience silicon-consuming breakage and agglomeration under small size and high temperature conditions, leading to process instability and affecting device performance and normal production.

[0060] In view of this, in order to solve the above problems, this disclosure provides another method for manufacturing a memory, which can form a connection structure with low contact resistance between the capacitor and the transistor. Figure 6 This is a schematic flowchart illustrating a method for manufacturing a memory according to an embodiment of this disclosure. Figure 6 As shown, the method for manufacturing a memory provided in this embodiment includes the following steps:

[0061] S100: A semiconductor layer is provided, wherein a plurality of transistor units are disposed in the semiconductor layer, the transistor units including a first transistor and a second transistor symmetrically distributed along a second direction; the first transistor and the second transistor each include a semiconductor body extending along the first direction, a gate structure covering one side of the semiconductor body, and a first electrode and a second electrode respectively at two ends of the semiconductor body along the first direction; the first direction is the thickness direction of the semiconductor layer.

[0062] S200: A metal compound material layer is deposited on the semiconductor layer using a deposition process;

[0063] S300: Part of the metal compound material layer is removed to form multiple connection structures; each connection structure is coupled to a first electrode;

[0064] S400: A storage structure is formed on the connection structure.

[0065] It should be understood that Figure 6The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 6 The steps shown can be adjusted in order according to actual needs. Figures 7 to 10 This is a cross-sectional schematic diagram illustrating the fabrication process of a memory according to an embodiment of this disclosure. It should be noted that... Figures 7 to 10 This is a schematic diagram illustrating the complete manufacturing process of a memory. Unmarked parts in some of the accompanying drawings can be shared. The following section will discuss this further. Figure 6 , Figures 7 to 10 The method for manufacturing the memory provided in the embodiments of this disclosure will be described in detail.

[0066] In step S100, as Figure 7 As shown, it mainly provides a semiconductor layer 101.

[0067] In some specific examples, the semiconductor layer 101 may include a substrate, which may include a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon-germanium (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.

[0068] In some specific examples, the gate structure 103 includes a gate 104 and a gate oxide layer 105.

[0069] In some specific examples, the material of gate 104 includes, but is not limited to, polysilicon, conductive metal, or conductive alloy. Conductive metal may include tungsten or copper, etc.

[0070] In some specific examples, the semiconductor body 102 between the first electrode 106 and the second electrode 107 constitutes the channel region of the transistor, and the gate oxide layer 105 is located between the gate 104 and the channel region to electrically isolate the channel region and the gate 104 and reduce the hot carrier effect of the transistor.

[0071] Here, the semiconductor body 102 extends along the first direction, which can be understood as the channel region of the transistor being a vertical channel, and its channel being perpendicular to the thickness direction of the semiconductor layer 101.

[0072] In some specific examples, the gate oxide layer 105 includes, but is not limited to, silicon oxide. Methods for forming the gate oxide layer 105 include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and other processes.

[0073] Here, the first electrode 106 can be the source or drain of a transistor, and the second electrode 107 can also be the source or drain of a transistor. For example, when the first electrode 106 is the source, the second electrode 107 is the drain; when the first electrode 106 is the drain, the second electrode 107 is the source.

[0074] Here, the first transistor 1001 and the second transistor 1002 are symmetrically distributed along the second direction, as can be referred to Figure 7 To understand: Both the first transistor 1001 and the second transistor 1002 include a first electrode 106, a second electrode 107, a semiconductor body 102, a gate 104, and a gate oxide layer 105. The gate 104 and the semiconductor body 102 in both the first transistor 1001 and the second transistor 1002 are located on opposite sides of the gate oxide layer 105 in a second direction. The gate 104 of the first transistor 1001 is located on the side of the gate oxide layer 105 of the first transistor 1001 closer to the second transistor 1002 in the second direction. The gate 104 of transistor 1002 is located on the side of the gate oxide layer 105 of the second transistor 1002 that is closer to the first transistor 1001 on the two opposite sides in the second direction. The semiconductor body 102 of the first transistor 1001 is located on the side of the gate oxide layer 105 of the first transistor 1001 that is farther away from the second transistor 1002 on the two opposite sides in the second direction. The semiconductor body 102 of the second transistor 1002 is located on the side of the gate oxide layer 105 of the second transistor 1002 that is farther away from the first transistor 1001 on the two opposite sides in the second direction.

[0075] In some embodiments, the plurality of transistor units 100 are arranged in an array in a second direction and a third direction, and a first insulating layer is formed between two adjacent rows of transistor units arranged along the third direction; the second direction and the third direction are both perpendicular to the first direction, and the second direction intersects the third direction.

[0076] Here, the intersection of the second direction and the third direction can be understood as the angle between the second direction and the third direction being less than or equal to 90 degrees. In some specific examples, the angle between the second direction and the third direction is equal to 90 degrees.

[0077] In some specific examples, the first direction can be understood as in Figures 7-10 The Z-axis direction shown is not limited to the Z-axis direction. The second direction can be understood as... Figures 7-10 The X-axis direction shown is not limited to the X-axis direction; it should be understood that the second direction is not limited to the X-axis direction. The third direction can be understood as... Figures 7-10The Y-axis direction shown in the figure can be understood to mean that the third direction is not limited to the Y-axis direction.

[0078] In some specific examples, a space such as [missing information] is also provided between the gate 104 and the gate oxide layer 105. Figure 7 The adhesive layer 111 shown.

[0079] In some specific examples, such as Figure 7 As shown, a first insulating layer 112 is provided between two adjacent transistor units 100, and a second insulating layer 113 is also provided between the first transistor 1001 and the second transistor 1002 in each transistor unit 100.

[0080] In some specific examples, the materials of the first insulating layer 112 and the second insulating layer 113 may be the same or different.

[0081] In some specific examples, the material of the first insulating layer 112 includes, but is not limited to, silicon oxide and silicon nitride.

[0082] In some specific examples, the material of the second insulating layer 113 includes, but is not limited to, silicon oxide and silicon nitride.

[0083] In some specific examples, cavities are formed in the first insulating layer 112 to isolate adjacent transistor cells 100 and improve mutual interference between adjacent transistor cells 100.

[0084] In some specific examples, the methods for forming the first insulating layer 112 and the second insulating layer 113 include, but are not limited to, PVD, CVD, and ALD.

[0085] In some specific examples, the methods for forming the first electrode 106 and the second electrode 107 include, but are not limited to, doping processes and diffusion processes. In some specific examples, the formed transistor can be an N-type transistor or a P-type transistor.

[0086] In an N-type transistor, both the source and drain are doped with N-type doping; in a P-type transistor, both the source and drain are doped with P-type doping. For example, when the doping type is P-type, the P-type impurity source can be boron (B), aluminum (Al), etc., and the P-type impurity source is not limited to these; when the doping type is N-type, the N-type impurity source can be phosphorus (P), arsenic (As), etc., and the N-type impurity source is not limited to these.

[0087] In some specific examples, the width of the first electrode 106 in the second direction is less than a first preset value.

[0088] In some specific examples, the range of the first preset value is 20nm-30nm.

[0089] Understandably, as memory size requirements continue to increase, the size of the first electrode 106 of the vertical channel transistor is constantly shrinking. Therefore, forming a metal compound interconnect structure 109 using the smaller first electrode 106 to connect the transistor and the memory structure 110 presents significant manufacturing challenges. The solution proposed in this embodiment reduces these challenges and addresses the difficulty of forming the metal compound interconnect structure 109 when the first electrode 106 is small.

[0090] It should be noted that the first preset value given in the above embodiments is only an exemplary demonstration and is not intended to limit the first preset value in this disclosure. In actual applications, the first preset value can be set according to the specific actual process conditions.

[0091] In step S200, as Figure 8 As shown, a metal compound material layer 108 is mainly formed on the semiconductor layer 101.

[0092] In some embodiments, the deposition of a metal compound material layer 108 on the semiconductor layer 101 using a deposition process includes:

[0093] A metal compound material layer 108 is deposited on the semiconductor layer 101 using a physical vapor deposition process.

[0094] In some specific examples, the method of forming a metal compound material layer 108 on the semiconductor layer 101 also includes a chemical vapor deposition process.

[0095] In some specific examples, the material of the metal compound material layer 108 includes, but is not limited to, tungsten silicide and tungsten germanide.

[0096] In step S300, as Figure 9 As shown, it mainly forms multiple connection structures 109.

[0097] In some embodiments, the removal of a portion of the metal compound material layer 108 to form a plurality of connection structures 109 includes:

[0098] A mask layer is formed on the metal compound material layer 108;

[0099] Using the mask layer, a portion of the metal compound material layer 108 is removed by an etching process, while at least the metal compound material layer on the first electrode 106 is retained, forming multiple connection structures 109.

[0100] Here, retaining at least the metal compound material layer on the first electrode 106 can be understood as follows: only the metal compound material layer on the first electrode 106 can be retained, such that the width of the formed connection structure 109 in the second direction is equal to the width of the first electrode 106 in the second direction; or the metal compound material layer on the first electrode 106 and part of the metal compound material layer on the gate structure 103 can be retained, such that the width of the formed connection structure 109 in the second direction is greater than the width of the first electrode 106 in the second direction.

[0101] In some specific examples, the mask layer may include a photoresist mask or a hard mask patterned based on a photolithography mask. For example, silicon nitride.

[0102] In some specific examples, the methods for removing part of the metal compound material layer 108 include, but are not limited to, dry plasma etching processes.

[0103] In some embodiments, the width of the connection structure 109 in the second direction is greater than the width of the first electrode 106 in the second direction.

[0104] It is understood that in this embodiment of the present disclosure, by directly depositing a metal compound layer on the semiconductor layer 101 and forming the connection structure 109 after removing part of the metal compound layer, the problem of small size effect caused by the limitation of the size of the end of the semiconductor body 102 when directly forming the metal compound connection structure 109 by annealing one end of the semiconductor body 102 with the metal material layer can be improved. In addition, in this embodiment of the present disclosure, the connection structure is formed by directly depositing the metal compound material layer without high-temperature annealing, so there is no breakage problem caused by silicon consumption. Therefore, the above-mentioned solution provided by this embodiment of the present disclosure can reduce the process difficulty. In addition, in this embodiment of the present disclosure, the size of the connection structure 109 can be adjusted by adjusting the pattern on the mask layer, so that the size of the formed connection structure 109 is not limited by the size of the end of the semiconductor body 102. The width of the formed connection structure 109 in the second direction is greater than the width of the first electrode 106 in the second direction, so that the contact area between the connection structure 109 and the first electrode 106 is increased, thereby reducing the contact resistance between the transistor and the memory structure 110.

[0105] In some embodiments, the material of the metal compound material layer 108 includes tungsten silicide and tungsten germanide.

[0106] It is understandable that tungsten silicide and tungsten germanide have good thermal stability, generally greater than 1000℃, which can meet the thermal stability requirements of the novel vertical channel memory for the connection structure 109 proposed in this embodiment.

[0107] In step S400, as Figure 10As shown, the storage structure 110 is mainly formed on the connection structure 109.

[0108] In some specific examples, forming the memory structure 110 may include the following steps: forming a memory structure hole on the connection structure 109; forming the memory structure 110 in the memory structure hole, for example, forming a memory capacitor.

[0109] In some specific examples, the storage capacitor can present various structures. For example, the storage capacitor may include a cup-shaped capacitor (CUP), a cylindrical capacitor (CYL), or a pillar-shaped capacitor (PIL). Each of these capacitors includes a bottom electrode, a top electrode, and a dielectric layer located between the bottom and top electrodes.

[0110] In some specific examples, the bottom electrode is connected to the first electrode 106 in the memory, the top electrode of the cup-shaped capacitor CUP is grounded, and the cup-shaped capacitor CUP is used to store the written data.

[0111] It should be noted that, when the bottom electrode areas of the cup-shaped capacitor (CUP), cylindrical capacitor (CYL), and pillar-shaped capacitor (PIL) are equal, the top electrode area of ​​the cylindrical capacitor (CYL) is the largest, followed by the top electrode areas of the cylindrical capacitor (CYL) and pillar-shaped capacitor (PIL). Therefore, in practical applications, the cylindrical capacitor (CYL) can be used as the storage unit of a memory, which is beneficial for improving the integration density of the memory.

[0112] In some embodiments, the semiconductor layer 101 has a first surface and a second surface opposite to each other in a first direction; the plurality of transistor units 100 are formed on the first surface;

[0113] The method further includes:

[0114] The semiconductor layer 101 is thinned from the second surface to expose the second electrode 107;

[0115] Multiple bit lines are formed; the multiple bit lines are parallel to each other and extend along the second direction; each bit line is connected to the second electrode 107 of each transistor in a row of transistor units arranged along the second direction.

[0116] In some specific examples, the memory includes dynamic random access memory, and the storage structure 110 includes storage capacitors.

[0117] It is understood that in this embodiment of the present disclosure, the memory provided is a vertical channel transistor, with its source and drain at the upper and lower ends of the channel region, the bit line connected to the second electrode 107, and the storage capacitor connected to the first electrode 106. It can be fabricated on both sides of the wafer, thereby improving the efficiency of process development.

[0118] In some specific examples, the process for thinning the semiconductor layer 101 includes, but is not limited to, etching and chemical mechanical polishing processes.

[0119] It is understood that the bit line BL is used to perform read or write operations on the transistor when the transistor is turned on.

[0120] In some specific examples, bit lines are formed by forming metal lines at predetermined bit line locations. These metal lines include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicides, or any combination thereof.

[0121] The embodiments disclosed herein merely exemplify some common memories, and the scope of protection of this disclosure is not limited thereto. Any memory that includes the memory provided in the embodiments of this disclosure is within the scope of protection of this invention.

[0122] This disclosure provides a method for fabricating a memory, comprising: providing a semiconductor layer 101, wherein a plurality of transistor units 100 are disposed in the semiconductor layer 101, the transistor unit 100 including a first transistor 1001 and a second transistor 1002 symmetrically distributed along a second direction; each of the first transistor 1001 and the second transistor 1002 includes a semiconductor body 102 extending along the first direction, a gate structure 103 covering one side of the semiconductor body 102, and a first electrode 106 and a second electrode 107 respectively at two ends of the semiconductor body 102 along the first direction; the first direction is the thickness direction of the semiconductor layer 101; depositing a metal compound material layer 108 on the semiconductor layer 101 using a deposition process; removing part of the metal compound material layer 108 to form a plurality of interconnect structures 109; each interconnect structure 109 being coupled to a first electrode 106; and forming a memory structure 110 on the interconnect structure 109. In this embodiment, a metal compound material layer 108 is directly deposited on the semiconductor layer 101, and a portion of the metal compound material layer 108 is removed to form a connection structure 109. This improves the problem that when the connection structure 109 is formed directly using the end of the semiconductor body 102, the small size effect occurs when forming the connection structure 109 because the end of the semiconductor body 102 has a small width in the second direction, and the connection structure will break and agglomerate under high temperature conditions, resulting in poor connection effect of the formed connection structure 109 and large contact resistance between the storage structure 110 and the transistor, thereby reducing the performance of the memory.

[0123] According to another aspect of this disclosure, embodiments of this disclosure also provide a memory, including:

[0124] A semiconductor layer having a plurality of transistor units disposed therein, each transistor unit including a first transistor and a second transistor symmetrically distributed along a second direction; each of the first transistor and the second transistor includes a semiconductor body extending along the first direction, a gate structure covering one side of the semiconductor body, and a first electrode and a second electrode respectively located at two ends of the semiconductor body along the first direction; the first direction is the thickness direction of the semiconductor layer.

[0125] Multiple connection structures are formed by depositing a metal compound material layer on the semiconductor layer using a deposition process and then removing a portion of the metal compound material layer; each connection structure is connected to a first electrode.

[0126] Multiple storage structures, each connected to a connection structure.

[0127] In some embodiments, the plurality of transistor units are arranged in an array in a second direction and a third direction, and a first insulating layer is formed between two adjacent rows of transistor units arranged along the third direction; the second direction and the third direction are both perpendicular to the first direction, and the second direction intersects the third direction.

[0128] In some embodiments, the width of the connection structure in the second direction is greater than the width of the first electrode in the second direction.

[0129] In some embodiments, the memory further includes:

[0130] Multiple bit lines; the multiple bit lines are parallel to each other and extend along the second direction; each bit line is connected to the second electrode of each transistor in a row of transistor cells arranged along the second direction.

[0131] In some embodiments, the material of the metal compound material layer includes tungsten silicide and tungsten germanide.

[0132] In some embodiments, the memory includes dynamic random access memory, and the memory structure includes a storage capacitor.

[0133] The memory provided in the above embodiments has been described in detail on the method side, and will not be repeated here.

[0134] According to another aspect of this disclosure, embodiments of this disclosure also provide a memory system, including:

[0135] One or more memories as described in the above embodiments; and

[0136] A memory controller, which is coupled to the memory and controls the memory.

[0137] In some specific examples, the memory can be used as computer memory in a memory system or as a cache in a memory system.

[0138] In some specific examples, the memory can be used in conjunction with a solid-state drive (SSD) to improve read and write speeds. Currently, high-end SSDs often embed DRAM to enhance performance and improve random read / write speeds. For instance, during file writing, especially small file writing, small files are processed by DRAM before being stored in Flash memory, resulting in higher SSD storage efficiency and faster speeds.

[0139] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.

[0140] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0141] This disclosure provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

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