Trench-type silicon carbide MOSFET structure and manufacturing method thereof

Abstract

The present invention discloses a trench silicon carbide MOSFET structure and a method for fabricating the same. The trench silicon carbide MOSFET structure includes a trench gate region, which includes at least one first PN junction formed by doping and at least one second PN junction formed by doping, the second PN junction being arranged parallel to and in an opposite direction to the first PN junction. The trench silicon carbide MOSFET structure of the present invention reduces the input and output capacitance of the silicon carbide MOSFET structure by forming two PN junctions arranged in opposite directions.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a trench-type silicon carbide MOSFET structure and a manufacturing method thereof. Background Art

[0002] As a third-generation power device, silicon carbide MOSFETs offer advantages such as fast switching speed, wide bandgap, low power consumption, low on-resistance, high operating frequency, and high temperature resistance. They have become ideal devices for special applications such as high temperature, high voltage, and high frequency. The development of silicon carbide MOSFETs aims to improve performance by transforming the traditional planar structure into a trench structure. Compared to Si devices, silicon carbide MOSFETs can be used at higher frequencies, which requires silicon carbide MOSFETs to have lower input capacitance (Ciss), output capacitance (Coss), and Maitreya capacitance (Crss) to ensure faster switching speeds.

[0003] Currently, most manufacturers have no obvious way to reduce the input capacitance of devices with rated voltage and rated VTH, and can only accept the capacitance value brought by the process platform.

[0004] The information disclosed in this background technology section is only intended to enhance understanding of the overall background of the invention and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the Invention

[0005] An object of the present invention is to provide a trench silicon carbide MOSFET structure, which can reduce the input capacitance and output capacitance of the silicon carbide MOSFET structure by forming two PN junctions arranged in opposite directions.

[0006] To achieve the above objectives, an embodiment of the present invention provides a trench silicon carbide MOSFET structure, including a trench gate region, wherein the trench gate region includes:

[0007] at least one first PN junction formed by doping;

[0008] At least one second PN junction is formed by doping, and the second PN junction is parallel to and opposite to the first PN junction.

[0009] In one or more embodiments of the present invention, the trench gate region includes a control gate region and a shield gate region that are isolated from each other, and the first PN junction and the second PN junction are both formed in the control gate region.

[0010] In one or more embodiments of the present invention, the trench silicon carbide MOSFET structure further includes:

[0011] a first conductive type substrate;

[0012] A first conductive type semiconductor drift region is formed above the first conductive type substrate;

[0013] a second conductive type semiconductor base region formed above the first conductive type semiconductor drift region; and

[0014] a first conductive type semiconductor source region formed above the second conductive type semiconductor base region;

[0015] The trench gate region is formed in the first conductive type semiconductor drift region, the second conductive type semiconductor base region, and the first conductive type semiconductor source region.

[0016] In one or more embodiments of the present invention, the trench gate region also includes a trench, which passes through the first conductive type semiconductor source region and the second conductive type semiconductor base region from top to bottom, and extends into the first conductive type semiconductor drift region. The control gate region and the shield gate region are both located in the trench, and the control gate region is located above the shield gate region.

[0017] In one or more embodiments of the present invention, the trench is filled with a first isolation medium, and the control gate region and the shield gate region are isolated from the first conductive type semiconductor source region, the second conductive type semiconductor base region and the first conductive type semiconductor drift region by the first isolation medium.

[0018] In one or more embodiments of the present invention, a control gate structure is formed in the control gate region, and the control gate structure includes a first conductivity type doped region and a second conductivity type doped region arranged laterally;

[0019] A third conductive type doping region is formed above the first conductive type doping region by doping, and the first conductive type doping region and the third conductive type doping region form the first PN junction;

[0020] A fourth conductive type doping region is formed above the second conductive type doping region by doping, and the second conductive type doping region and the fourth conductive type doping region located above the second conductive type doping region form the second PN junction.

[0021] In one or more embodiments of the present invention, the first conductivity type is N-type, the second conductivity type is P-type, the third conductivity type is P-type, and the fourth conductivity type is N-type.

[0022] In one or more embodiments of the present invention, the trench silicon carbide MOSFET structure further includes:

[0023] a source electrode, the source electrode being formed on and in contact with the first conductive type semiconductor source region;

[0024] a gate electrode, the gate electrode being in contact with the control gate structure;

[0025] A drain electrode is formed below the first conductive type substrate and in contact with the first conductive type substrate.

[0026] In one or more embodiments of the present invention, the control gate structure and the source electrode are isolated from each other by a second isolation medium.

[0027] The present invention also provides a method for manufacturing a trench silicon carbide MOSFET structure, comprising:

[0028] doping the control gate structure to form a first PN junction;

[0029] The control gate structure is doped to form a second PN junction, where the second PN junction is parallel to and opposite to the first PN junction.

[0030] Compared with the prior art, the trench silicon carbide MOSFET structure of the embodiment of the present invention forms two PN junction parasitic capacitors set in opposite directions in the trench gate region by doping, thereby reducing the input capacitance and output capacitance, and the size of the parasitic capacitance can be adjusted by the doping concentration.

[0031] The trench silicon carbide MOSFET structure of the embodiment of the present invention forms a pair of reverse PN junctions in the trench gate region, so that the trench silicon carbide MOSFET structure can be bidirectionally conductive, further reducing Cgd and Cgs capacitances. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a trench silicon carbide MOSFET structure according to one embodiment of the present invention.

[0033] Figures 2 to 10 It is a structural schematic diagram of the manufacturing process of a trench silicon carbide MOSFET structure according to one embodiment of the present invention. DETAILED DESCRIPTION

[0034] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

[0035] Unless expressly stated otherwise, throughout the specification and claims, the term "comprise" or variations such as "include" or "comprising", etc., will be understood to include the stated elements or components but not to exclude other elements or other components.

[0036] As mentioned in the background technology, faster switching speeds for SiC MOSFETs require lower input capacitance, output capacitance, and Maitreya capacitance. However, existing SiC MOSFET structures do not offer the potential for achieving smaller input capacitance, output capacitance, and Maitreya capacitance.

[0037] In order to solve the above technical problems, one embodiment of the present invention provides a trench silicon carbide MOSFET structure, which reduces the input capacitance and output capacitance of the silicon carbide MOSFET structure by forming two PN junctions arranged in opposite directions.

[0038] like Figure 1 As shown, a trench silicon carbide MOSFET structure includes a first conductive type substrate 11, a first conductive type semiconductor drift region 12, a second conductive type semiconductor base region 13, a first conductive type semiconductor source region 14, a trench gate region 20, a source electrode 31, a gate electrode and a drain electrode 32.

[0039] A first-conductivity-type semiconductor drift region 12 is formed above a first-conductivity-type substrate 11, a second-conductivity-type semiconductor base region 13 is formed above the first-conductivity-type semiconductor drift region 12, and a first-conductivity-type semiconductor source region 14 is formed above the second-conductivity-type semiconductor base region 13. A trench gate region 20 is formed within the first-conductivity-type semiconductor drift region 12, the second-conductivity-type semiconductor base region 13, and the first-conductivity-type semiconductor source region 14. The trench gate region 20 includes at least one first PN junction formed by doping and at least one second PN junction formed by doping, the second PN junction being arranged parallel to and opposite to the first PN junction. A source electrode 31 contacts the first-conductivity-type semiconductor source region 14, a gate electrode contacts the first and second PN junctions within the trench gate region 20, and a drain electrode 32 contacts the first-conductivity-type substrate 11.

[0040] The trench gate region 20 includes a trench 23 , a control gate region 21 , and a shield gate region 22 . A first PN junction and a second PN junction are both formed in the control gate region 21 .

[0041] The trench 23 passes through the first-conductivity-type semiconductor source region 14 and the second-conductivity-type semiconductor base region 13 from top to bottom, extending into the first-conductivity-type semiconductor drift region 12. The control gate region 21 and the shield gate region 22 are both located within the trench 23, with the control gate region 21 located above the shield gate region 22. The trench 23 is filled with a first isolation dielectric 41, which isolates the control gate region 21 and the shield gate region 22 from the first-conductivity-type semiconductor source region 14, the second-conductivity-type semiconductor base region 13, and the first-conductivity-type semiconductor drift region 12. The control gate region 21 and the shield gate region 22 are also isolated from each other by the first isolation dielectric 41. The first isolation dielectric 41 comprises silicon oxide.

[0042] A control gate structure is formed within the control gate region 21. The control gate structure includes a first-conductivity-type doped region 211 and a second-conductivity-type doped region 212 arranged laterally. A third-conductivity-type doped region 213 is formed above the first-conductivity-type doped region 211 through doping. The first-conductivity-type doped region 211 and the third-conductivity-type doped region 213 form a first PN junction, which is a forward PN junction. A fourth-conductivity-type doped region 214 is formed above the second-conductivity-type doped region 212 through doping. The second-conductivity-type doped region 212 forms a second PN junction with the fourth-conductivity-type doped region 214 located above it, which is a reverse PN junction.

[0043] In a specific embodiment, the conductive material in the first conductive type doping region 211 includes polysilicon, and the doping concentration range of the first conductive type doping region 211 is 1E15-5E15; the conductive material in the second conductive type doping region 212 includes polysilicon, and the doping concentration range of the second conductive type doping region 212 is 5E16-8E16; the conductive material in the third conductive type doping region 213 includes polysilicon, and the doping concentration range of the third conductive type doping region 213 is 5E16-8E16; and the conductive material in the fourth conductive type doping region 214 includes polysilicon, and the doping concentration of the fourth conductive type doping region 214 includes 1E15-5E15.

[0044] The shielding gate region 22 is filled with a shielding gate conductive material, which includes doped polysilicon.

[0045] In one embodiment, the first conductivity type is N-type, the second conductivity type is P-type, the third conductivity type is P-type, and the fourth conductivity type is N-type. In other embodiments, the first conductivity type is P-type, the second conductivity type is N-type, the third conductivity type is N-type, and the fourth conductivity type is P-type.

[0046] The source electrode 31 is formed on and in contact with the first-conductivity-type semiconductor source region 14. The control gate structure and the source electrode 31 are isolated by a second isolation dielectric 42. The second isolation dielectric 42 comprises BPSG or TEOS. The gate electrode and the control gate structure are in contact with each other. The drain electrode 32 is formed below and in contact with the first-conductivity-type substrate 11. The source electrode 31 is made of aluminum, the gate electrode is made of aluminum, and the drain electrode 32 is made of silver.

[0047] The working principle of the trench silicon carbide MOSFET structure of the present invention is described below by taking the first conductivity type as N type, the second conductivity type as P type, the third conductivity type as P type, and the fourth conductivity type as N type as an example:

[0048] First, the input capacitance, Ciss, refers to the capacitance between the GS (gate and source) electrodes measured with an AC signal when the DS (source and drain) electrodes are shorted. Ciss is the capacitance of the GS (gate and source) electrodes in parallel with the capacitance of the GD (gate and drain) electrodes, i.e., Ciss = Cgs + Cgd. The output capacitance, Coss, refers to the capacitance between the DS (source and drain) electrodes measured with an AC signal when the GS (gate and source) electrodes are shorted. Coss is the capacitance of the GD (gate and drain) electrodes in parallel with the capacitance of the DS (source and drain) electrodes, i.e., Coss = Cgd + Cds. The reverse transfer capacitance, Crss, refers to the capacitance between the S (source) electrodes grounded and the GD (gate and drain) electrodes, i.e., Crss = Cgd.

[0049] The trench silicon carbide MOSFET structure of the present invention further reduces the above-mentioned Cgs and Cgd by adding a pair of reverse PN junctions, thereby achieving the purpose of reducing Ciss, Coss, and Crss.

[0050] refer to Figure 1 As shown, Figure 1In the trench silicon carbide MOSFET structure, the first PN junction formed by the first conductive type doping region 211 and the third conductive type doping region 213 is defined as the A junction, and the second PN junction formed by the second conductive type doping region 212 and the fourth conductive type doping region 214 is defined as the B junction. Cgs after adding the A junction capacitance is represented by Cgs*, and Cgd after adding the B junction capacitance is represented by Cgd*. The new Cgs* is the series connection of the A junction capacitance and the original Cgs. According to the series capacitance formula 1 / Cgs*=1 / CpnA+1 / Cgs, Cgs* is reduced. In this state, the B junction is in the on state and does not participate in the capacitance. The new Cgd* is the series connection of the B junction capacitance and the original Cgd. According to the series capacitance formula: 1 / Cgd*=1 / CpnB+1 / Cgd, Cgd is reduced. In this state, the A junction is in the on state and does not participate in the capacitance. Where Cgs is the original Cgs without the added PN junction, Cgd is the original Cgd without the added PN junction, CpnA is the A-junction capacitance, and CpnB is the B-junction capacitance. This reduces the overall Ciss of the trench silicon carbide MOSFET structure. CpnA and CpnB are determined by the N-type and P-type doping concentrations and can be adjusted to achieve the desired values based on the process.

[0051] In one embodiment of the present invention, a method for manufacturing a trench silicon carbide MOSFET structure is also provided, comprising: doping the control gate structure to form a first PN junction; doping the control gate structure to form a second PN junction, wherein the second PN junction is parallel to the first PN junction and arranged in reverse.

[0052] Figures 2 to 10 A structural schematic diagram of a manufacturing process of a trench silicon carbide MOSFET structure according to an embodiment of the present invention is provided. The manufacturing process of the trench silicon carbide MOSFET structure of the present application is described in detail below in conjunction with a specific example.

[0053] refer to Figure 2 As shown, an N-type semiconductor drift region 12 is formed on a semiconductor substrate 11; a P-type semiconductor base region 13 is formed on the N-type semiconductor drift region 12; and an N-type semiconductor source region 14 is formed on the P-type semiconductor base region 13. The doping concentration of the N-type semiconductor source region 14 is 1E16.

[0054] refer to Figure 3 As shown, a trench 23 of a desired depth is formed on the N-type semiconductor source region 14, the P-type semiconductor base region 13, and the N-type semiconductor drift region 12 by dielectric deposition, photolithography, and etching. A first isolation dielectric 41 is formed on the inner sidewalls and bottom wall of the trench 23.

[0055] refer to Figure 4 and Figure 5As shown, doped polysilicon is deposited in the trench 23 and the doped polysilicon is etched to form a shield gate structure 22 .

[0056] refer to Figure 6 As shown, the first isolation dielectric material is filled again in the trench 23 to form a first isolation dielectric 41 . The first isolation dielectric 41 completely fills the trench 23 to cover the shielding gate structure 22 .

[0057] refer to Figure 7 As shown, the first isolation dielectric 41 is etched to form a cavity as shown, and doped polysilicon is deposited in the cavity to form a first conductive type doped region 211. The upper surface of the first conductive type doped region 211 is not higher than the upper surface of the first isolation dielectric 41 located on the inner side wall of the trench 23.

[0058] refer to Figure 8 As shown, the first conductive type doping region 211 is doped with the second conductive type in its lateral direction to form a second conductive type doping region 212;

[0059] refer to Figure 9 As shown, the first conductive type doping region 211 is doped with the third conductive type in its longitudinal direction to form a third conductive type doping region 213, wherein the first conductive type doping region 211 and the third conductive type doping region 213 form a first PN junction. The second conductive type doping region 212 is doped with the fourth conductive type doping region 214 in its longitudinal direction to form a fourth conductive type doping region 214, wherein the second conductive type doping region 212 forms a second PN junction with the fourth conductive type doping region 214 located above it. In this embodiment, the first conductive type is N-type, the second conductive type is P-type, the third conductive type is P-type, and the fourth conductive type is N-type.

[0060] refer to Figure 10 As shown, a second isolation dielectric 42 is formed above the third conductivity type doped region 213 and the fourth conductivity type doped region 214. A drain electrode 32 is formed below the semiconductor substrate 11; a source electrode 31 is formed above the N-type semiconductor source region 14, and the source electrode 31 is isolated from the control gate region 21 by the second isolation dielectric 42; and a gate electrode is formed to communicate with the trench gate region 20.

[0061] Compared with the prior art, the trench silicon carbide MOSFET structure of the embodiment of the present invention forms two PN junction parasitic capacitors set in opposite directions in the trench gate region by doping, thereby reducing the input capacitance and output capacitance, and the size of the parasitic capacitance can be adjusted by the doping concentration.

[0062] The trench silicon carbide MOSFET structure of the embodiment of the present invention forms a pair of reverse PN junctions in the trench gate region, so that the trench silicon carbide MOSFET structure can be bidirectionally conductive, further reducing Cgd and Cgs capacitances.

[0063] The various aspects, embodiments, features and examples of the present invention should be considered as illustrative in all respects and are not intended to limit the present invention, the scope of which is defined solely by the claims. Other embodiments, modifications and uses will be apparent to those skilled in the art without departing from the spirit and scope of the invention as claimed.

[0064] The use of headings and sections in this application is not meant to limit the invention; each section may apply to any aspect, embodiment, or feature of the invention.

[0065] Throughout this application, where a composition is described as having, containing, or comprising particular components, or where a process is described as having, containing, or comprising particular process steps, it is contemplated that the compositions taught by the present invention also consist essentially of, or consist of, the recited components, and that the processes taught by the present invention also consist essentially of, or consist of, the recited process steps.

[0066] In this application, where an element or component is referred to as being included in and / or selected from a list of recited elements or components, it should be understood that the element or component may be any one of the recited elements or components and may be selected from a group consisting of two or more of the recited elements or components. Furthermore, it should be understood that the elements and / or features of the compositions, apparatuses, or methods described herein may be combined in various ways, whether explicitly or implicitly stated herein, without departing from the spirit and scope of the present teachings.

[0067] Unless specifically stated otherwise, the use of the terms "including", "having" and "comprising" should generally be construed as open ended and non-limiting.

[0068] Unless specifically stated otherwise, the use of the singular herein includes the plural (and vice versa). Furthermore, unless the context clearly dictates otherwise, the singular forms "a," "an," and "the" include the plural. Additionally, where the term "about" is used before a quantitative value, the present teachings also include the specific quantitative value itself unless specifically stated otherwise.

[0069] Should be understood that, the order of each step or the order in which specific action is performed is not very important, as long as the present invention teachings remain operable.In addition, two or more steps or actions can be performed simultaneously.

[0070] It should be understood that the figures and descriptions of the present invention have been simplified to illustrate elements relevant to a clear understanding of the present invention, while other elements have been eliminated for clarity. However, those skilled in the art will recognize that these and other elements may be desirable. However, since such elements are well known in the art and since they do not promote a better understanding of the present invention, a discussion of such elements is not provided herein. It should be understood that the figures are presented for illustrative purposes and are not intended to be construction diagrams. Omitted details and modifications or alternative embodiments are within the scope of those skilled in the art.

[0071] It will be appreciated that in certain aspects of the present invention, a single component may be replaced by multiple components and multiple components may be replaced by a single component to provide an element or structure or to perform one or more given functions. Except where such substitution would not operate to practice a specific embodiment of the present invention, such substitution is considered within the scope of the present invention.

[0072] Although the present invention has been described with reference to illustrative embodiments, it will be understood by those skilled in the art that various other changes, omissions, and / or additions may be made and that substantial equivalents may be substituted for the elements of the embodiments without departing from the spirit and scope of the present invention. Additionally, many modifications may be made to adapt specific circumstances or materials to the teachings of the present invention without departing from the scope of the present invention. Therefore, it is not intended herein to limit the present invention to the disclosed specific embodiments for carrying out the present invention, but rather to include all embodiments within the scope of the appended claims. Furthermore, unless specifically stated, any use of the terms first, second, etc. does not indicate any order or importance, but rather uses the terms first, second, etc. to distinguish one element from another.

Claims

1. A trench silicon carbide MOSFET structure, characterized in that: Comprising a trench gate region (20), the trench gate region (20) comprising: at least one first PN junction formed by doping; At least one second PN junction formed by doping, wherein the second PN junction is parallel to and opposite to the first PN junction; The trench gate region (20) comprises a control gate region (21) and a shield gate region (22) that are isolated from each other, and the first PN junction and the second PN junction are both formed in the control gate region (21); The trench silicon carbide MOSFET structure further includes: A first conductive type substrate (11); A first conductive type semiconductor drift region (12) is formed above the first conductive type substrate (11); a second conductive type semiconductor base region (13) formed above the first conductive type semiconductor drift region (12); and A first conductive type semiconductor source region (14) is formed above the second conductive type semiconductor base region (13); The trench gate region (20) is formed in the first conductive type semiconductor drift region (12), the second conductive type semiconductor base region (13) and the first conductive type semiconductor source region (14); The trench gate region (20) further includes a trench (23), wherein the trench (23) sequentially passes through the first conductive type semiconductor source region (14) and the second conductive type semiconductor base region (13) from top to bottom, and extends into the first conductive type semiconductor drift region (12); the control gate region (21) and the shield gate region (22) are both located in the trench (23), and the control gate region (21) is located above the shield gate region (22); The trench is filled with a first isolation medium (41), and the control gate region (21) and the shield gate region (22) are isolated from the first conductive type semiconductor source region (14), the second conductive type semiconductor base region (13), and the first conductive type semiconductor drift region (12) by the first isolation medium (41); The control gate region and the shield gate region are also isolated from each other by a first isolation medium.

2. The trench silicon carbide MOSFET structure according to claim 1, wherein: A control gate structure is formed in the control gate region (21), the control gate structure comprising a first conductive type doping region (211) and a second conductive type doping region (212) arranged laterally; A third conductive type doping region (213) is formed above the first conductive type doping region (211) by doping, and the first conductive type doping region (211) and the third conductive type doping region (213) form the first PN junction; A fourth conductive type doping region (214) is formed above the second conductive type doping region (212) by doping, and the second conductive type doping region (212) and the fourth conductive type doping region (214) located above the second conductive type doping region (212) form the second PN junction.

3. The trench silicon carbide MOSFET structure according to claim 2, wherein: The first conductivity type is N-type, the second conductivity type is P-type, the third conductivity type is P-type, and the fourth conductivity type is N-type.

4. The trench silicon carbide MOSFET structure according to claim 2, wherein: The trench silicon carbide MOSFET structure further includes: a source electrode (31), the source electrode (31) being formed on the first conductive type semiconductor source region (14) and in contact with the first conductive type semiconductor source region (14); a gate electrode, the gate electrode being in contact with the control gate structure; A drain electrode (32), wherein the drain electrode (32) is formed below the first conductive type substrate (11) and is in contact with the first conductive type substrate (11).

5. The trench silicon carbide MOSFET structure according to claim 4, wherein: The control gate structure and the source electrode (31) are isolated by a second isolation medium (42).

6. A method for manufacturing a trench silicon carbide MOSFET structure according to any one of claims 1 to 5, characterized in that: include: doping the control gate structure to form a first PN junction; The control gate structure is doped to form a second PN junction, where the second PN junction is parallel to and opposite to the first PN junction.

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