LDMOS device and method of forming the same

Abstract

An LDMOS device and a forming method thereof, wherein the structure comprises: a deep well region in a substrate, the deep well region being of a second conductivity type opposite to a first conductivity type; a field oxide structure on a surface of the deep well region, a top surface of the field oxide structure being higher than a top surface of the substrate, the field oxide structure comprising a first field oxide layer, a second field oxide layer and a plurality of third field oxide layers between the first field oxide layer and the second field oxide layer, the first field oxide layer, the second field oxide layer and the plurality of third field oxide layers being separate from each other; a body region in the deep well region, the body region being adjacent to the first field oxide layer and being of the first conductivity type; a first gate field plate on a surface of a part of the first field oxide layer and a surface of a part of the body region; a second gate field plate on a surface of a part of the second field oxide layer; and a source region and a drain region on both sides of the field oxide structure, the source region being in the body region and the drain region being in the deep well region, the source region and the drain region being of the second conductivity type, so that the withstand voltage of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to an LDMOS device and a method for forming the same. Background Art

[0002] The BCD (Bipolar-CMOS-DMOS) process is a monolithic integration technology used to fabricate bipolar junction transistors (BJTs), complementary metal-oxide semiconductors (CMOSs), and double-diffused metal-oxide semiconductors (DMOSs) on the same chip. Devices manufactured using the BCD process are widely used in power management, display drivers, automotive electronics, industrial control, and other fields.

[0003] In the current high-voltage BCD process, a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) device is used as a voltage-resistant device.

[0004] However, the semiconductor structure formed by the existing LDMOS device technology needs to be further improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide an LDMOS device and a method for forming the same, so as to improve the performance of the formed device.

[0006] To solve the above technical problems, the technical solution of the present invention provides an LDMOS device, comprising: a substrate, the substrate being of a first conductivity type; a deep well region located within the substrate, the deep well region being of a second conductivity type, the second conductivity type being opposite to the first conductivity type; a field oxide structure located on a surface of the deep well region, the top surface of the field oxide structure being higher than the top surface of the substrate, the field oxide structure comprising a first field oxide layer, a second field oxide layer, and a plurality of third field oxide layers located between the first field oxide layer and the second field oxide layer, the first field oxide layer, the second field oxide layer, and the plurality of third field oxide layers being separate from each other; a body region located within the deep well region, the body region being adjacent to the first field oxide layer and being of the first conductivity type; a first gate field plate located on a portion of the surface of the first field oxide layer and a portion of the surface of the body region; a second gate field plate located on a portion of the surface of the second field oxide layer; and a source region and a drain region located on either side of the field oxide structure, the source region being located within the body region, the drain region being located within the deep well region, and the source region and the drain region being of the second conductivity type.

[0007] Optionally, the method further includes: a lead-out region located in the body region, the lead-out region being in contact with the source region and being farther away from the field oxide structure than the source region, and the lead-out region being of the first conductivity type.

[0008] Optionally, it also includes: a conductive structure located on the substrate, the conductive structure including a first conductive layer, a second conductive layer and a third conductive layer; the first conductive layer is electrically connected to the lead-out region and the source region, and the first conductive layer extends above the first gate field plate; the second conductive layer is electrically connected to the second gate field plate and the drain region; the third conductive layer is floating and located between the first conductive layer and the second conductive layer.

[0009] Optionally, the third conductive layer is located above at least one of the third field oxide layers.

[0010] Optionally, in a direction from the source region to the drain region, a distance between the third conductive layer and the second conductive layer ranges from 0.1 micrometers to 20 micrometers.

[0011] Optionally, the first field oxygen layer, the second field oxygen layer and each of the third field oxygen layers are ring-shaped, and the first field oxygen layer, the plurality of third field oxygen layers and the second field oxygen layer are arranged from the drain region toward the source region and are arranged around the drain region.

[0012] Optionally, it includes: the body region is arranged around the outside of the drain region; the field oxide structure is arranged around the outside of the drain region and is located on the deep well region inside the body region; the second gate field plate is arranged around the outside of the drain region and is located inside the body region; the first gate field plate is arranged around the outside of the second gate field plate and is located inside the body region, and extends to part of the surface of the body region.

[0013] Optionally, the substrate includes a first region, a second region, and a third region arranged along a first direction; the source region surrounds the drain region, the drain region includes a first drain region located in the first region, a plurality of second drain regions located in the second region and connected to the first drain region, and a plurality of third drain regions located in the third region and connected to the second drain region, one second drain region corresponds to one third drain region, the first drain region extends along the second direction, the second drain region is parallel to the first direction and arranged along the second direction; the second gate field plate includes a first gate portion located in the first region, a plurality of first line gate portions located outside the second drain region, and a second gate portion located in the third region, one second drain region corresponds to two first line gate portions The first gate portion and the second gate portion connect the first gate portions together and surround the outside of the drain region; the first gate field plate is located on the inner side of the source region, and the first gate field plate includes a third gate portion located in the first region, a plurality of second gate portions located outside the second drain region, and a fourth gate portion located in the third region. One second drain region corresponds to two second gate portions. The plurality of second gate portions are parallel to the first direction and arranged along the second direction. The third gate portion and the fourth gate portion connect the plurality of second gate portions together and surround the outside of the second gate field plate.

[0014] Optionally, the first direction and the second direction are perpendicular to each other.

[0015] Optionally, the number of the plurality of third field oxide layers ranges from 0 to 50; in the direction from the source region to the drain region, the size of the first field oxide layer ranges from 0.1 microns to 10 microns; in the direction from the source region to the drain region, the size of the second field oxide layer ranges from 0.1 microns to 10 microns; in the direction from the source region to the drain region, the size of each of the third field oxide layers ranges from 0.1 microns to 10 microns.

[0016] Optionally, it further includes: a doped region located in the deep well region below the field oxide structure.

[0017] Accordingly, the technical solution of the present invention also provides a method for forming an LDMOS device, comprising: providing a substrate, the substrate being of a first conductivity type; forming a deep well region in the substrate, the deep well region being of a second conductivity type, the second conductivity type being opposite to the first conductivity type; forming a field oxide structure on a portion of the surface of the deep well region, the top surface of the field oxide structure being higher than the top surface of the substrate, the field oxide structure comprising a first field oxide layer, a second field oxide layer, and a plurality of third field oxide layers located between the first field oxide layer and the second field oxide layer, the first field oxide layer, the second field oxide layer, and The several third field oxide layers are all separated from each other; a body region is formed in the deep well region, the body region is of the first conductivity type, and the body region is adjacent to the first field oxide layer; a first gate field plate and a second gate field plate are formed on a portion of the surface of the field oxide structure, the first gate field plate is located on a portion of the surface of the first field oxide layer and also extends to a portion of the surface of the body region, and the second gate field plate is located on a portion of the surface of the second field oxide layer; a source region and a drain region are formed on both sides of the field oxide structure, the source region is located in the body region, the drain region is located in the deep well region, and the source region and the drain region are of the second conductivity type.

[0018] Optionally, the method further includes: forming a lead-out region in the body region, the lead-out region being in contact with the source region, and the lead-out region being farther away from the field oxide structure than the source region, and the lead-out region being of the first conductivity type.

[0019] Optionally, after forming the source region, the drain region and the lead-out region, the method further includes: forming an interlayer dielectric layer on the surface of the substrate; forming a conductive structure in the interlayer dielectric layer, the conductive structure including a first conductive layer, a second conductive layer and a third conductive layer; the first conductive layer is electrically connected to the lead-out region and the source region, and the first conductive layer extends above the first gate field plate; the second conductive layer is electrically connected to the second gate field plate and the drain region; the third conductive layer is floating and is located between the first conductive layer and the second conductive layer.

[0020] Optionally, the first field oxygen layer, the second field oxygen layer and each of the third field oxygen layers are ring-shaped, and the first field oxygen layer, the plurality of third field oxygen layers and the second field oxygen layer are arranged from the drain region toward the source region and are arranged around the drain region.

[0021] Optionally, it includes: the body region is arranged around the outside of the drain region; the field oxide structure is arranged around the outside of the drain region and is located on the deep well region inside the body region; the second gate field plate is arranged around the outside of the drain region and is located inside the body region; the first gate field plate is arranged around the outside of the second gate field plate and is located inside the body region, and extends to part of the surface of the body region.

[0022] Optionally, the substrate includes a first region, a second region, and a third region arranged along a first direction; the source region surrounds the drain region, the drain region includes a first drain region located in the first region, a plurality of second drain regions located in the second region and connected to the first drain region, and a plurality of third drain regions located in the third region and connected to the second drain region, one second drain region corresponds to one third drain region, the first drain region extends along the second direction, the second drain region is parallel to the first direction and arranged along the second direction; the second gate field plate includes a first gate portion located in the first region, a plurality of first line gate portions located outside the second drain region, and a second gate portion located in the third region, one second drain region corresponds to two first line gate portions The first gate portion and the second gate portion connect the first gate portions together and surround the outside of the drain region; the first gate field plate is located on the inner side of the source region, and the first gate field plate includes a third gate portion located in the first region, a plurality of second gate portions located outside the second drain region, and a fourth gate portion located in the third region. One second drain region corresponds to two second gate portions. The plurality of second gate portions are parallel to the first direction and arranged along the second direction. The third gate portion and the fourth gate portion connect the plurality of second gate portions together and surround the outside of the second gate field plate.

[0023] Optionally, the method further includes: after forming the field oxide structure, forming a doped region in the deep well region below the field oxide structure.

[0024] Optionally, the process of forming the doped region includes a plasma implantation process.

[0025] Optionally, the process of forming the field oxide structure includes a local oxidation isolation process.

[0026] Compared with the existing technology, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0027] In the method for forming an LDMOS device provided by the technical solution of the present invention, a field oxide structure is formed on a portion of the surface of the deep well region. The field oxide structure includes a first field oxide layer, a second field oxide layer, and a plurality of third field oxide layers located between the first field oxide layer and the second field oxide layer. The first field oxide layer, the second field oxide layer, and the plurality of third field oxide layers are all separate from each other. Since the field oxide structure is divided into multiple field oxide layers, there is a change in electric field strength at the beginning or end of each field oxide layer due to a change in oxide layer thickness. From the perspective of the lateral electric field distribution in the drift region of the LDMOS device, the electric field distribution may generate several electric field peaks at the beginning or end of each field oxide layer. The magnitude of the electric field peak can be adjusted according to the size of the field oxide layer and the number of field oxide layers. These several electric field peaks increase the overall electric field of the device, thereby improving the overall breakdown voltage performance of the device. Accordingly, under the same breakdown voltage performance requirements, the longitudinal electric field of the field oxide structure near the "bird's beak region" is also reduced, thereby improving the overall reliability of the device.

[0028] Furthermore, a conductive structure is formed in the interlayer dielectric layer, and the conductive structure includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer is electrically connected to the lead-out region and the source region, and the first conductive layer extends above the first gate field plate. The second conductive layer is electrically connected to the second gate field plate and the drain region. The third conductive layer is floating and is located between the first conductive layer and the second conductive layer. The first conductive layer, the second conductive layer and the third conductive layer act as metal field plates, further improving the voltage resistance of the device.

[0029] Furthermore, a doped region is formed in the deep well region below the field oxide structure. The doped region enables the current to have two circuit paths in the drift regions above and below the doped region, thereby improving the operating current of the device.

[0030] In the LDMOS device provided by the technical solution of the present invention, the field oxide structure includes a first field oxide layer, a second field oxide layer, and a plurality of third field oxide layers located between the first and second field oxide layers. The first field oxide layer, the second field oxide layer, and the plurality of third field oxide layers are all separate from each other. Since the field oxide structure is divided into multiple field oxide layers, there is a change in electric field strength at the beginning or end of each field oxide layer due to a change in oxide layer thickness. From the perspective of the lateral electric field distribution in the drift region of the LDMOS device, the electric field distribution may generate a plurality of electric field peaks at the beginning or end of each field oxide layer. The magnitude of the electric field peak can be adjusted according to the size of the field oxide layer and the number of field oxide layers. The plurality of electric field peaks increase the overall electric field of the device, thereby improving the overall breakdown voltage performance of the device. Accordingly, under the same breakdown voltage performance requirements, the longitudinal electric field of the field oxide structure near the "bird's beak region" is also reduced, thereby improving the overall reliability of the device.

[0031] Furthermore, a conductive structure located on the substrate includes a first conductive layer, a second conductive layer and a third conductive layer, the first conductive layer is electrically connected to the lead-out region and the source region, and the first conductive layer extends above the first gate field plate, the second conductive layer is electrically connected to the second gate field plate and the drain region, the third conductive layer is floating and located between the first conductive layer and the second conductive layer, the first conductive layer, the second conductive layer and the third conductive layer act as metal field plates, further improving the voltage resistance of the device.

[0032] Furthermore, the doped region in the deep well region below the field oxide structure enables the current to have two circuit paths in the drift regions above and below the doped region, thereby improving the operating current of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic diagram of the cross-sectional structure of an LDMOS device;

[0034] Figures 2 to 7 1 is a schematic structural diagram of each step of a method for forming an LDMOS device according to an embodiment of the present invention;

[0035] Figures 8 to 10 It is a structural schematic diagram of each step of a method for forming an LDMOS device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0036] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0037] As described in the background art, the performance of LDMOS devices formed using existing technologies urgently needs to be improved. An LDMOS device will now be described and analyzed.

[0038] Figure 1 It is a schematic diagram of the cross-sectional structure of an LDMOS device.

[0039] Please refer to Figure 1The LDMOS device includes: a substrate 101; a deep well region 102 located in the substrate 101, the deep well region 102 being of a first conductivity type; a substrate lead-out region 103 located in the substrate 101, the substrate lead-out region 103 being of a second conductivity type and located outside the deep well region 102; a field oxide layer 104 located on a surface of the deep well region 102; a first well region 105 located in the deep well region 102, the first well region 105 being located on the field oxide layer 104. and the substrate lead-out region 103; an adjacent doped region 106 and a gate lead-out region 107 located within the first well region 105, wherein the doped region 106 is of the first conductivity type and the gate lead-out region 107 is of the second conductivity type, and the doped region 106 and the gate lead-out region 107 are electrically connected to each other via a first conductive structure 108; a gate structure located on the surface of the first well region 105, wherein the gate structure includes a gate oxide layer 109 and a polysilicon gate 110 located on the gate oxide layer 109, and the polysilicon gate 110 is electrically connected to the first conductive structure 108. The silicon gate 110 also extends to the surface of the field oxide layer 104; a polysilicon field plate 111 is also provided on the surface of the field oxide layer 104; a drain 112 is located in the deep well region 102, and the drain 112 and the first well region 105 are respectively located on both sides of the field oxide layer 104, and the polysilicon field plate 111 and the drain 112 are electrically interconnected through a second conductive structure 113; a source 114 is located in the deep well region 102, and the source 114 is also located between the substrate lead-out region 103 and the first well region 105. 5; a dielectric layer (not shown in the figure) located on the surface of the substrate 100, wherein the dielectric layer has a conductive layer, wherein the conductive layer includes the first conductive structure 108 and the second conductive structure 113, and the conductive layer also includes a third conductive structure 115, a fourth conductive structure 116 and a fifth conductive structure 117, wherein the third conductive structure 115 is electrically connected to the substrate lead-out region 103, the fourth conductive structure 116 is electrically connected to the source 114, and the fifth conductive structure 117 is electrically connected to the gate structure.

[0040] The above structure is an ultra-high voltage LDMOS device prepared based on the BCD process. In the BCD process, the gate oxide layer of the CMOS device (not shown) and the gate oxide layer 109 of the LDMOS device share the same gate oxide (GOX) deposition process. Since the current density of the CMOS device is highly dependent on the thickness of the gate oxide layer, in order to improve the current density of the CMOS device, it is usually necessary to thin the thickness of the gate oxide layer. However, when the gate oxide layer of the CMOS device is thinned, the gate oxide layer 109 of the LDMOS device is also thinned accordingly, so that the electric field strength of the gate oxide layer 109 near the polysilicon gate 110 end (bird's beak area A) is increased, which increases the breakdown risk when testing the breakdown voltage of the device to a certain extent, causing the "burning tube" phenomenon. At the same time, it also brings the failure risk of the high temperature reverse bias (HTRB) test. In addition, as the voltage resistance requirements increase, higher voltage is usually achieved by increasing the length of the drift region. As the length of the drift region increases, the electric field near the bird's beak region A will become higher and higher, limiting the voltage resistance improvement of the device.

[0041] To address the above-mentioned problems, the present invention provides an LDMOS device and a method for forming the same. A field oxide structure is formed on a portion of the surface of the deep well region. The field oxide structure includes a plurality of discrete field oxide layers arranged in a direction from the source region toward the drain region. Since the field oxide structure is divided into a plurality of field oxide layers, electric field strength varies at the beginning or end of each field oxide layer due to variations in oxide layer thickness. From the perspective of the lateral electric field distribution in the drift region of the LDMOS device, the electric field distribution may generate a plurality of electric field peaks at the beginning or end of each field oxide layer. The magnitude of the electric field peaks can be adjusted based on the size and number of the field oxide layers. These plurality of electric field peaks increase the overall electric field of the device, thereby improving the overall breakdown voltage performance of the device. Accordingly, under the same breakdown voltage performance requirements, the longitudinal electric field of the field oxide structure near the "bird's beak region" is also reduced, thereby improving the overall reliability of the device.

[0042] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Figures 2 to 7 It is a structural schematic diagram of each step of a method for forming an LDMOS device according to an embodiment of the present invention.

[0044] Please refer to Figure 2 , providing a substrate 201, wherein the substrate 201 is of a first conductivity type.

[0045] The first conductivity type includes N type or P type. In this embodiment, the first conductivity type is P type.

[0046] Please continue to refer to Figure 2 A deep well region 202 is formed in the substrate 201 , and the deep well region 202 is of a second conductivity type, which is opposite to the first conductivity type.

[0047] The second conductivity type includes N type or P type. In this embodiment, the second conductivity type is N type.

[0048] In this embodiment, the formation process of the deep well region 202 includes: forming a mask layer on the surface of the substrate 201, wherein the mask layer exposes a portion of the surface of the substrate 201; using the mask layer as a mask, injecting dopant ions into the substrate 201; after injecting dopant ions into the substrate 201, performing high-temperature treatment on the substrate 201 to form the deep well region 202.

[0049] Please refer to Figure 3 and Figure 4 , Figure 3 for Figure 4 Schematic diagram of the top view of the structure, Figure 4 for Figure 3 The schematic cross-sectional structure diagram along the EE1 direction in the middle dotted box shows that a field oxygen structure 203 is formed on a portion of the surface of the deep well region 202. The top surface of the field oxygen structure 203 is higher than the top surface of the substrate 201. The field oxygen structure 203 includes a first field oxygen layer 203a, a second field oxygen layer 203b, and the plurality of third field oxygen layers 203c located between the first field oxygen layer 203a and the second field oxygen layer 203b. The first field oxygen layer 203a, the second field oxygen layer 203b, and the plurality of third field oxygen layers 203c are all separate from each other.

[0050] In this embodiment, the first field oxygen layer 203a, the second field oxygen layer 203b, and each of the third field oxygen layers 203c are all ring-shaped. Specifically, the second field oxygen layer 203b is located inside, each of the third field oxygen layers 203c surrounds the second field oxygen layer 203b, and the first field oxygen layer 203a surrounds the third field oxygen layers 203c.

[0051] Subsequently, a source region and a drain region are formed on both sides of the field oxide structure 203 , respectively. The first field oxide layer 203 a , the third field oxide layers 203 c and the second field oxide layer 203 b are arranged from the drain region toward the source region and surround the drain region.

[0052] The number of the plurality of third field oxide layers 203c ranges from 0 to 50. In this embodiment, the number of the third field oxide layers 203c is two. In other embodiments, the size and number of the third field oxide layers 203c are adjusted according to actual needs.

[0053] In this embodiment, along the direction from the source region to the drain region, the size of the first field oxide layer 203 a ranges from 0.1 micrometers to 10 micrometers.

[0054] In this embodiment, along the direction from the source region to the drain region, the size of the second field oxide layer 203 b ranges from 0.1 microns to 10 microns.

[0055] In this embodiment, along the direction from the source region to the drain region, the size of each of the third field oxide layers 203 c ranges from 0.1 microns to 10 microns.

[0056] It should be noted that, in this embodiment, the first field oxide layer 203 a , the second field oxide layer 203 b and each of the third field oxide layers 203 c are respectively ring-shaped, and the size is the width of the ring region where each field oxide layer is located.

[0057] In this embodiment, after forming the field oxide structure 203, a doped region 204 is formed in the deep well region 202 below the field oxide structure 203. In other embodiments, after forming the deep well region and before forming the field oxide structure, a doped region is formed in the deep well region, and the doped region is also located below the subsequently formed field oxide structure.

[0058] The doped region 204 allows the current to have two circuit paths in the drift region above and below the doped region 204 , thereby increasing the operating current of the device.

[0059] In this embodiment, the process of forming the doped region 204 includes a plasma implantation process.

[0060] In this embodiment, the process of forming the field oxide structure 203 includes a local oxidation isolation process.

[0061] In this embodiment, the method for forming the field oxide structure 203 includes: forming a masking layer (not shown in the figure) on the surface of the substrate 201, wherein the masking layer exposes a portion of the surface of the substrate 201; forming the field oxide structure 203 on the exposed surface of the substrate 201 using a wet oxygen process; and after forming the field oxide structure 203, removing the masking layer.

[0062] Please refer to Figure 5 and Figure 6 , Figure 5 for Figure 6 The cross-sectional structure diagram along the EE1 direction in the dotted box is shown in the figure. Figure 6 for Figure 5 Schematic diagram of the top structure, a body region 205 is formed in the deep well region 202, the body region 205 is of the first conductivity type, and the body region 205 is adjacent to the first field oxide layer 203a; a first gate field plate 206 and a second gate field plate 208 are formed on a portion of the surface of the field oxide structure 203, the first gate field plate 206 is located on a portion of the surface of the first field oxide layer 203a, and also extends to a portion of the surface of the body region 205, the second gate field plate 208 is located on a portion of the surface of the second field oxide layer 203b; a source region 209 and a drain region 210 are formed on both sides of the field oxide structure 203, the source region 209 is located in the body region 205, the drain region 210 is located in the deep well region 202, and the source region 209 and the drain region 210 are of the second conductivity type.

[0063] At this point, since the field oxide structure 203 is divided into multiple field oxide layers, there is a change in electric field strength at the beginning or end of each field oxide layer due to the change in oxide layer thickness. From the perspective of the lateral electric field distribution in the drift region of the LDMOS device, the electric field distribution may generate several electric field peaks at the beginning or end of each field oxide layer. The size of the electric field peak can be adjusted according to the size of the field oxide layer and the number of field oxide layers. The several electric field peaks increase the overall electric field of the device, thereby improving the breakdown voltage performance of the device as a whole; accordingly, under the same breakdown voltage performance requirements, the longitudinal electric field of the field oxide structure 203 near the "bird's beak area" will also be reduced, thereby improving the overall reliability of the device.

[0064] In this embodiment, the body region 205 is formed after forming the field oxide structure 203. In other embodiments, the body region may be formed after forming the deep well region and before forming the field oxide structure.

[0065] In this embodiment, a gate oxide layer 207 is provided between the first gate field plate 206 and the substrate 201 .

[0066] In this embodiment, the body region 205 is disposed around the outer side of the drain region 210 .

[0067] In this embodiment, the field oxide structure 203 is arranged to surround the outside of the drain region 210 and is located on the deep well region 202 inside the body region 205; the second gate field plate 208 is arranged to surround the outside of the drain region 210 and is located inside the body region 205; the first gate field plate 206 is arranged to surround the outside of the second gate field plate 208 and is located inside the body region 205, and extends to a portion of the surface of the body region 205.

[0068] In this embodiment, a lead-out region 211 is further formed in the body region 205 . The lead-out region 211 contacts the source region 209 and is farther away from the field oxide structure 203 than the source region 209 . The lead-out region 211 is of the first conductivity type.

[0069] It should be noted that Figure 5 The lead-out area 211 is omitted in the top view structural diagram.

[0070] In this embodiment, after forming the source region 209, the drain region 210, and the lead-out region 211, please refer to Figure 7 .

[0071] Please Figure 6 Continue to refer to Figure 7 , an interlayer dielectric layer (not shown in the figure) is formed on the surface of the substrate 201; a conductive structure is formed in the interlayer dielectric layer, and the conductive structure includes a first conductive layer 212, a second conductive layer 213 and a third conductive layer 214; the first conductive layer 212 is electrically connected to the lead-out region 211 and the source region 209, and the first conductive layer 212 extends above the first gate field plate 206; the second conductive layer 213 is electrically connected to the second gate field plate 208 and the drain region 210; the third conductive layer 214 is floating and is located between the first conductive layer 212 and the second conductive layer 213.

[0072] The first conductive layer 212 is used to lead out the source region 209, and the second conductive layer 213 is used to lead out the drain region 210; at the same time, the first conductive layer 212, the second conductive layer 213 and the third conductive layer 214 act as metal field plates, further improving the voltage resistance of the device.

[0073] In this embodiment, along the direction from the source region 209 to the drain region 210 , a distance d between the third conductive layer 214 and the second conductive layer 213 ranges from 0.1 micrometers to 20 micrometers.

[0074] In this embodiment, the third conductive layer 214 is located above at least one third field oxide layer 203c to enhance the metal field plate function of the third conductive layer 214 and increase the breakdown voltage performance of the device.

[0075] In this embodiment, the shape of the LDMOS device is circular. In other embodiments, the shape of the LDMOS device can be circular, elliptical, or bullet-shaped.

[0076] Accordingly, the embodiment of the present invention further provides an LDMOS device formed by the above method, please continue to refer to Figure 5 and Figure 7 , comprising: a substrate 201, the substrate 201 being of a first conductivity type; a deep well region 202 located in the substrate 201, the deep well region 202 being of a second conductivity type, the second conductivity type being opposite to the first conductivity type; a field oxide structure 203 located on the surface of the deep well region 202, the top surface of the field oxide structure 203 being higher than the top surface of the substrate 201, the field oxide structure 203 comprising a first field oxide layer 203a, a second field oxide layer 203b, and a plurality of third field oxide layers 203c located between the first field oxide layer 203a and the second field oxide layer 203b, the first field oxide layer 203a, the second field oxide layer 203b, and the Several third field oxide layers 203c are separated from each other; a body region 205 is located in the deep well region 202, the body region 205 is adjacent to the first field oxide layer 203a, and the body region 205 is of the first conductivity type; a first gate field plate 206 is located on a portion of the surface of the first field oxide layer 203a and a portion of the surface of the body region 205; a second gate field plate 208 is located on a portion of the surface of the second field oxide layer 203b; a source region 209 and a drain region 210 are located on both sides of the field oxide structure 203, the source region 209 is located in the body region 205, the drain region 210 is located in the deep well region 202, and the source region 209 and the drain region 210 are of the second conductivity type.

[0077] In the LDMOS device, since the field oxide structure 203 is divided into multiple field oxide layers, there is a change in electric field strength at the beginning or end of each field oxide layer due to a change in oxide layer thickness. From the perspective of the lateral electric field distribution in the drift region of the LDMOS device, the electric field distribution may generate several electric field peaks at the beginning or end of each field oxide layer. The magnitude of the electric field peak can be adjusted according to the size of the field oxide layer and the number of field oxide layers. The several electric field peaks increase the overall electric field of the device, thereby improving the breakdown voltage performance of the device as a whole. Correspondingly, under the same breakdown voltage performance requirements, the longitudinal electric field of the field oxide structure near the "bird's beak region" will also be reduced, thereby improving the overall reliability of the device.

[0078] In this embodiment, the LDMOS device further includes: a lead-out region 211 located in the body region 205 , the lead-out region 211 is in contact with the source region 209 , and the lead-out region 211 is farther from the field oxide structure 203 than the source region 209 , and the lead-out region 211 is of the first conductivity type.

[0079] In this embodiment, the LDMOS device further includes: a conductive structure located on the substrate 201, the conductive structure including a first conductive layer 212, a second conductive layer 213 and a third conductive layer 214; the first conductive layer 212 is electrically connected to the lead-out region 211 and the source region 209, and the first conductive layer 212 extends above the first gate field plate 206; the second conductive layer 213 is electrically connected to the second gate field plate 208 and the drain region 210; the third conductive layer 214 is floating and located between the first conductive layer 212 and the second conductive layer 213.

[0080] The first conductive layer 212 , the second conductive layer 213 and the third conductive layer 214 function as metal field plates, further improving the voltage resistance of the device.

[0081] In this embodiment, the third conductive layer 214 is located above at least one third field oxide layer 203c to enhance the metal field plate function of the third conductive layer 214 and increase the breakdown voltage performance of the device.

[0082] In this embodiment, along the direction from the source region 209 to the drain region 210 , a distance d between the third conductive layer 214 and the second conductive layer 213 ranges from 0.1 micrometers to 20 micrometers.

[0083] In this embodiment, the first field oxygen layer 203 a, the second field oxygen layer 203 b and each of the third field oxygen layers 203 c are all ring-shaped. The first field oxygen layer 203 a, the third field oxygen layers 203 c and the second field oxygen layer 203 b are arranged from the drain region 210 toward the source region 209 and are arranged around the drain region 210.

[0084] In this embodiment, the body region 205 is arranged to surround the outside of the drain region 210; the field oxide structure 203 is arranged to surround the outside of the drain region 210 and is located on the deep well region 202 inside the body region 205; the second gate field plate 208 is arranged to surround the outside of the drain region 210 and is located inside the body region 205; the first gate field plate 206 is arranged to surround the outside of the second gate field plate 208 and is located inside the body region 205, and extends to a portion of the surface of the body region 205.

[0085] In this embodiment, the number of the plurality of third field oxide layers 203c ranges from 0 to 50; in the direction from the source region 209 to the drain region 210, the size of the first field oxide layer 203a ranges from 0.1 microns to 10 microns; in the direction from the source region 209 to the drain region 210, the size of the second field oxide layer 203b ranges from 0.1 microns to 10 microns; in the direction from the source region 209 to the drain region 210, the size of each of the third field oxide layers 203c ranges from 0.1 microns to 10 microns.

[0086] In this embodiment, the LDMOS device further includes a doped region 204 located in the deep well region 202 below the field oxide structure 203 .

[0087] The doped region 204 allows the current to have two circuit paths in the drift region above and below the doped region 204 , thereby increasing the operating current of the device.

[0088] In this embodiment, the shape of the LDMOS device is circular. In other embodiments, the shape of the LDMOS device can be circular, elliptical, or bullet-shaped.

[0089] Figures 8 to 10 It is a structural schematic diagram of each step of a method for forming an LDMOS device according to another embodiment of the present invention.

[0090] Please refer to Figures 8 and 9 , Figure 8 for Figure 9 Schematic diagram of the top view of the structure, Figure 9 for Figure 8A schematic cross-sectional structure diagram along the DD1 direction is provided, wherein a substrate 301 is provided, wherein the substrate 301 is of a first conductivity type; a deep well region 302 is formed in the substrate 301, wherein the deep well region 302 is of a second conductivity type, and the second conductivity type is opposite to the first conductivity type; a field oxide structure 303 is formed on a surface of a portion of the deep well region 302, wherein the top surface of the field oxide structure 303 is higher than the top surface of the substrate 301, and the field oxide structure 303 includes a first field oxide layer 303a, a second field oxide layer 303b, and a plurality of third field oxide layers 303c located between the first field oxide layer 303a and the second field oxide layer 303b, wherein the first field oxide layer 303a, the second field oxide layer 303b, and the plurality of third field oxide layers 303c are all separated from each other. ; A body region 305 is formed in the deep well region 302, and the body region 305 is of the first conductivity type. The body region 305 is adjacent to the first field oxide layer 303a; a first gate field plate 306 and a second gate field plate 308 are formed on a portion of the surface of the field oxide structure 303, the first gate field plate 306 is located on a portion of the surface of the first field oxide layer 303a, and also extends to a portion of the surface of the body region 305, and the second gate field plate 308 is located on a portion of the surface of the second field oxide layer 303b; a source region 309 and a drain region 310 are formed on both sides of the field oxide structure 303, the source region 309 is located in the body region 305, and the drain region 310 is located in the deep well region 302, and the source region 309 and the drain region 310 are of the second conductivity type.

[0091] In this embodiment, a lead-out region 311 is further formed in the body region 305. The lead-out region 311 contacts the source region 309 and is further away from the field oxide structure 303 than the source region 309. The lead-out region 311 is of the first conductivity type. Figure 8 Only the source region 309 in the body region 305 is shown, and the lead-out region 311 is not shown.

[0092] In this embodiment, after forming the field oxide structure 303, a doped region 304 is formed in the deep well region 302 below the field oxide structure 303. In other embodiments, after forming the deep well region and before forming the field oxide structure, a doped region is formed in the deep well region, and the doped region is also located below the subsequently formed field oxide structure.

[0093] In this embodiment, a gate oxide layer 307 is provided between the first gate field plate 306 and the substrate 301 .

[0094] In this embodiment, the body region 305 is arranged to surround the outside of the drain region 310; the field oxide structure 303 is arranged to surround the outside of the drain region 310 and is located on the deep well region 302 inside the body region 305; the second gate field plate 308 is arranged to surround the outside of the drain region 310 and is located inside the body region 305; the first gate field plate 306 is arranged to surround the outside of the second gate field plate 308 and is located inside the body region 305, and extends to a portion of the surface of the body region 305.

[0095] The main difference between this embodiment and the previous embodiment is that the overall shape of the LDMOS device is different.

[0096] Specifically, the substrate 301 includes a first region I, a second region II, and a third region III arranged along a first direction X; the source region 309 surrounds the drain region 310, the drain region 310 includes a first drain region 310a located in the first region I, a plurality of second drain regions 310b located in the second region II and connected to the first drain region 310a, and a plurality of third drain regions 310c located in the third region III and connected to the second drain region 310b, one second drain region 310b corresponds to one third drain region 310c, the first drain region 310a extends along a second direction Y, the second drain regions 310b are parallel to the first direction X and arranged along the second direction Y; the second gate field plate 308 includes a first gate portion 308a located in the first region I, a plurality of first line gate portions 308b located outside the second drain region 310b, and a second gate portion 308c located in the third region III, one second drain region 310b corresponds to two a first line grid portion 308b, the plurality of first line grid portions 308b are parallel to the first direction X and arranged along the second direction Y, the first gate portion 308a and the second gate portion 308c connect the plurality of first line grid portions 308b together and surround the outside of the drain region 310; the first gate field plate 306 located inside the source region 309, the first gate field plate 306 includes a third gate portion 306a located in the first region I, a plurality of second line grid portions 306b located outside the second drain region 310b and a fourth gate portion 306c located in the third region III, one second drain region 310b corresponds to two second line grid portions 306b, the plurality of second line grid portions 306b are parallel to the first direction X and arranged along the second direction Y, the third gate portion 306a and the fourth gate portion 306c connect the plurality of second line grid portions 306b together and surround the outside of the second gate field plate 308.

[0097] In this embodiment, after forming the source region 309, the drain region 310 and the lead-out region 311, Figure 9 Continue to refer to Figure 10 .

[0098] Please refer to Figure 10 , an interlayer dielectric layer (not shown in the figure) is formed on the surface of the substrate 301; a conductive structure is formed in the interlayer dielectric layer, and the conductive structure includes a first conductive layer 312, a second conductive layer 313 and a third conductive layer 314; the first conductive layer 312 is electrically connected to the lead-out region 311 and the source region 309, and the first conductive layer 312 extends above the first gate field plate 306; the second conductive layer 313 is electrically connected to the second gate field plate 308 and the drain region 310; the third conductive layer 314 is floating and is located between the first conductive layer 312 and the second conductive layer 313.

[0099] In this embodiment, the specific method for forming the LDMOS device can be referred to the previous embodiment and will not be described in detail here.

[0100] Accordingly, the embodiment of the present invention further provides an LDMOS device formed by the above method, please continue to refer to Figure 8 .

[0101] The main difference between this embodiment and the previous embodiment is that the overall shape of the LDMOS device is different.

[0102] Specifically, the substrate 301 includes a first region I, a second region II, and a third region III arranged along a first direction X; the source region 309 surrounds the drain region 310, the drain region 310 includes a first drain region (not shown in the figure) located in the first region I, a plurality of second drain regions (not shown in the figure) located in the second region II and connected to the first drain region, and a plurality of third drain regions (not shown in the figure) located in the third region III and connected to the second drain region, one second drain region corresponds to one third drain region, the first drain region extends along a second direction Y, the second drain region is parallel to the first direction X and arranged along the second direction Y; the second gate field plate 308 includes a first gate portion 308a located in the first region I, a plurality of first line gate portions 308b located outside the second drain region 310b, and a second gate portion 308c located in the third region III, one second drain region corresponds to two first line gate portions 308 b. The plurality of first wire grid portions 308b are parallel to the first direction X and arranged along the second direction Y. The first gate portion 308a and the second gate portion 308c connect the plurality of first wire grid portions 308b together and surround the outside of the drain region 310. The first gate field plate 306 is located inside the source region 309. The first gate field plate 306 includes a third gate portion 306a located in the first region I, a plurality of second wire grid portions 306b located outside the second drain region 310b, and a fourth gate portion 306c located in the third region III. One second drain region 310b corresponds to two second wire grid portions 306b. The plurality of second wire grid portions 306b are parallel to the first direction X and arranged along the second direction Y. The third gate portion 306a and the fourth gate portion 306c connect the plurality of second wire grid portions 306b together and surround the outside of the second gate field plate 308.

[0103] It should be noted that, in this embodiment, only two second drain regions connected to the first drain region are shown. In other embodiments, the number of the second drain regions may be greater than two.

[0104] In this embodiment, the first direction X and the second direction Y are perpendicular to each other.

[0105] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming an LDMOS device, characterized in that: include: Providing a substrate, wherein the substrate is of a first conductivity type; forming a deep well region in the substrate, wherein the deep well region is of a second conductivity type, and the second conductivity type is opposite to the first conductivity type; forming a field oxide structure on a surface of a portion of the deep well region, wherein a top surface of the field oxide structure is higher than a top surface of the substrate, the field oxide structure comprising a first field oxide layer, a second field oxide layer, and a plurality of third field oxide layers located between the first field oxide layer and the second field oxide layer, wherein the first field oxide layer, the second field oxide layer, and the plurality of third field oxide layers are all separate from each other; forming a body region in the deep well region, wherein the body region is of the first conductivity type and is adjacent to the first field oxide layer; forming a first gate field plate and a second gate field plate on a portion of the surface of the field oxide structure, wherein the first gate field plate is located on a portion of the surface of the first field oxide layer and also extends to a portion of the surface of the body region, and the second gate field plate is located on a portion of the surface of the second field oxide layer; A source region and a drain region are formed on both sides of the field oxide structure. The source region is located in the body region, and the drain region is located in the deep well region. The source region and the drain region are of the second conductivity type.

2. The method for forming an LDMOS device according to claim 1, wherein: Also includes: A lead-out region is formed in the body region, the lead-out region is in contact with the source region, and the lead-out region is farther away from the field oxide structure than the source region, and the lead-out region is of the first conductivity type.

3. The method for forming an LDMOS device according to claim 2, wherein: After forming the source region, the drain region and the lead-out region, the method further includes: forming an interlayer dielectric layer on the surface of the substrate; forming a conductive structure in the interlayer dielectric layer, the conductive structure including a first conductive layer, a second conductive layer and a third conductive layer; the first conductive layer is electrically connected to the lead-out region and the source region, and the first conductive layer extends above the first gate field plate; the second conductive layer is electrically connected to the second gate field plate and the drain region; the third conductive layer is floating and is located between the first conductive layer and the second conductive layer.

4. The method for forming an LDMOS device according to claim 1, wherein: The first field oxygen layer, the second field oxygen layer and each of the third field oxygen layers are all ring-shaped. The first field oxygen layer, the third field oxygen layers and the second field oxygen layer are arranged from the drain region to the source region and are arranged around the drain region.

5. The method for forming an LDMOS device according to claim 4, wherein: include: The body region is arranged around the outside of the drain region; the field oxide structure is arranged around the outside of the drain region and is located on the deep well region inside the body region; the second gate field plate is arranged around the outside of the drain region and is located inside the body region; the first gate field plate is arranged around the outside of the second gate field plate and is located inside the body region, and extends to a portion of the surface of the body region.

6. The method for forming an LDMOS device according to claim 4, wherein: The substrate includes a first region, a second region, and a third region arranged along a first direction; the source region surrounds the drain region, the drain region includes a first drain region located in the first region, a plurality of second drain regions located in the second region and connected to the first drain region, and a plurality of third drain regions located in the third region and connected to the second drain region, one second drain region corresponds to one third drain region, the first drain region extends along a second direction, the second drain region is parallel to the first direction and arranged along the second direction; the second gate field plate includes a first gate portion located in the first region, a plurality of first line gate portions located outside the second drain region, and a second gate portion located in the third region, one second drain region corresponds to two first line gate portions, The several first wire grid portions are parallel to the first direction and arranged along the second direction. The first gate portion and the second gate portion connect the several first wire grid portions together and are arranged around the outside of the drain region. The first gate field plate is located on the inner side of the source region, and the first gate field plate includes a third gate portion located in the first region, several second wire grid portions located outside the second drain region and a fourth gate portion located in the third region. One second drain region corresponds to two second wire grid portions. The several second wire grid portions are parallel to the first direction and arranged along the second direction. The third gate portion and the fourth gate portion connect the several second wire grid portions together and are arranged around the outside of the second gate field plate.

7. The method for forming an LDMOS device according to claim 1, wherein: Also includes: After the field oxide structure is formed, a doped region is formed in the deep well region below the field oxide structure.

8. The method for forming an LDMOS device according to claim 7, wherein: The process of forming the doped region includes a plasma implantation process.

9. The method for forming an LDMOS device according to claim 1, wherein: The process of forming the field oxide structure includes a local oxidation isolation process.

10. An LDMOS device, characterized in that: The method for forming an LDMOS device according to any one of claims 1 to 9 comprises: a substrate of a first conductivity type; a deep well region located in the substrate, the deep well region being of a second conductivity type, the second conductivity type being opposite to the first conductivity type; a field oxide structure located on the surface of the deep well region, wherein the top surface of the field oxide structure is higher than the top surface of the substrate, the field oxide structure comprising a first field oxide layer, a second field oxide layer, and a plurality of third field oxide layers located between the first field oxide layer and the second field oxide layer, wherein the first field oxide layer, the second field oxide layer, and the plurality of third field oxide layers are all separate from each other; a body region located in the deep well region, the body region being adjacent to the first field oxide layer and being of a first conductivity type; a first gate field plate located on a portion of the surface of the first field oxide layer and a portion of the surface of the body region; a second gate field plate located on a surface of a portion of the second field oxide layer; The source region and the drain region are located on both sides of the field oxide structure, the source region is located in the body region, the drain region is located in the deep well region, and the source region and the drain region are of the second conductivity type.

11. The LDMOS device according to claim 10, wherein: Also includes: The lead-out region is located in the body region, the lead-out region is in contact with the source region, and the lead-out region is farther away from the field oxide structure than the source region, and the lead-out region is of the first conductivity type.

12. The LDMOS device according to claim 11, wherein: Also includes: a conductive structure located on the substrate, the conductive structure comprising a first conductive layer, a second conductive layer and a third conductive layer; The first conductive layer is electrically connected to the lead-out region and the source region, and the first conductive layer extends above the first gate field plate; the second conductive layer is electrically connected to the second gate field plate and the drain region; the third conductive layer is floating and is located between the first conductive layer and the second conductive layer.

13. The LDMOS device according to claim 12, wherein: The third conductive layer is located above at least one of the third field oxide layers.

14. The LDMOS device according to claim 12, wherein: In a direction from the source region to the drain region, a distance between the third conductive layer and the second conductive layer ranges from 0.1 micrometers to 20 micrometers.

15. The LDMOS device according to claim 10, wherein: The first field oxygen layer, the second field oxygen layer and each of the third field oxygen layers are all ring-shaped. The first field oxygen layer, the third field oxygen layers and the second field oxygen layer are arranged from the drain region to the source region and are arranged around the drain region.

16. The LDMOS device according to claim 15, wherein: include: The body region is arranged around the outside of the drain region; the field oxide structure is arranged around the outside of the drain region and is located on the deep well region inside the body region; the second gate field plate is arranged around the outside of the drain region and is located inside the body region; the first gate field plate is arranged around the outside of the second gate field plate and is located inside the body region, and extends to a portion of the surface of the body region.

17. The LDMOS device according to claim 15, wherein: The substrate includes a first region, a second region, and a third region arranged along a first direction; the source region surrounds the drain region, the drain region includes a first drain region located in the first region, a plurality of second drain regions located in the second region and connected to the first drain region, and a plurality of third drain regions located in the third region and connected to the second drain region, one second drain region corresponds to one third drain region, the first drain region extends along a second direction, the second drain region is parallel to the first direction and arranged along the second direction; the second gate field plate includes a first gate portion located in the first region, a plurality of first line gate portions located outside the second drain region, and a second gate portion located in the third region, one second drain region corresponds to two first line gate portions, The several first wire grid portions are parallel to the first direction and arranged along the second direction. The first gate portion and the second gate portion connect the several first wire grid portions together and are arranged around the outside of the drain region. The first gate field plate is located on the inner side of the source region, and the first gate field plate includes a third gate portion located in the first region, several second wire grid portions located outside the second drain region and a fourth gate portion located in the third region. One second drain region corresponds to two second wire grid portions. The several second wire grid portions are parallel to the first direction and arranged along the second direction. The third gate portion and the fourth gate portion connect the several second wire grid portions together and are arranged around the outside of the second gate field plate.

18. The LDMOS device according to claim 17, wherein: The first direction and the second direction are perpendicular to each other.

19. The LDMOS device according to claim 10, wherein: The number of the plurality of third field oxide layers ranges from 0 to 50; in the direction from the source region to the drain region, the size of the first field oxide layer ranges from 0.1 microns to 10 microns; in the direction from the source region to the drain region, the size of the second field oxide layer ranges from 0.1 microns to 10 microns; and in the direction from the source region to the drain region, the size of each of the third field oxide layers ranges from 0.1 microns to 10 microns.

20. The LDMOS device according to claim 10, wherein: Also includes: A doped region is located in the deep well region below the field oxide structure.

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