Semiconductor power discrete device based on a release substrate and method of manufacturing

Abstract

The application discloses a semiconductor power discrete device based on a stripping substrate and a manufacturing method. The device comprises an epitaxial layer, a gate layer and a functional layer. The gate layer is arranged on a first surface of the epitaxial layer and comprises a gate structure, a first passivation layer structure and a metal substrate. The gate structure is close to the first surface, the first passivation layer structure is arranged on two sides of the gate structure oppositely and protrudes from the gate structure at an end far from the epitaxial layer, and the metal substrate is located at the other end of the gate structure and the first passivation layer structure. The functional layer is arranged on a second surface of the epitaxial layer and comprises a second passivation layer structure, a source structure and a drain structure which are arranged on the second surface in parallel. The second passivation layer structure is arranged between the source structure and the drain structure to isolate the source structure and the drain structure. The device provided by the application has the advantages of less soldering lines, good heat dissipation effect and strong performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor power discrete devices, and particularly relates to a semiconductor power discrete device based on a split substrate and a method for manufacturing the semiconductor power discrete device. BACKGROUND

[0002] Most of the existing semiconductor devices are manufactured in a normal orientation, and in the packaging process, separate wire bonding is needed to connect the electrodes of the chip and the package pins, and there is a possibility of false welding.

[0003] In addition, in order to bear a large current, the metal electrodes of the semiconductor power discrete device in the normal orientation have a relatively large thickness, and the use of metal is excessive, which causes high cost and waste of resources.

[0004] In addition, the semiconductor power discrete device in the normal orientation has different designs of the chip on the packaging support, and therefore separate mold opening is needed, which results in high mold cost and difficulty in standardization of the support.

[0005] In addition, the semiconductor power discrete device in the normal orientation also has the problem of low chip heat dissipation efficiency, which greatly affects the performance of the device. SUMMARY

[0006] An advantage of the present application is to provide a semiconductor power discrete device based on a split substrate and a manufacturing method, wherein one side of the device can be provided on the support through two electrode patches of the source structure and the drain structure, and wire bonding is only performed on the metal substrate electrode end of the other side, which greatly reduces the number of wire bonds and the possibility of false wire bonding.

[0007] An advantage of the present application is to provide a semiconductor power discrete device based on a split substrate and a manufacturing method, wherein the source structure and the drain structure are on one side of the device, and the gate structure is on the other side of the device, and the distance between the source structure and the drain structure can be shortened under the same current, which reduces the area of the entire device, increases the number of devices in the same wafer range, and effectively reduces the cost. In addition, due to the reduced area, the device can also be used in some places with limited space, and the application range is wider.

[0008] An advantage of the present application is to provide a semiconductor power discrete device based on a stripping substrate and a manufacturing method, wherein the source structure and the drain structure can be directly pasted to the packaging support, thereby greatly reducing the thickness of the metal substrate on the other side, not only reducing the use of noble metals, saving resources, but also reducing the manufacturing cost of the device, and reducing the overall resistance of the device, reducing the internal resistance loss, and improving the overall performance of the device.

[0009] An advantage of the present application is to provide a semiconductor power discrete device based on a stripping substrate and a manufacturing method, which can realize unified standardized design, without the need to design a support mold for different forms of devices or chips, greatly reducing the cost of packaging.

[0010] An advantage of the present application is to provide a semiconductor power discrete device based on a stripping substrate and a manufacturing method, wherein whether the metal substrate is pasted to the packaging support or the source structure and the drain structure on the other side are pasted to the packaging support, the heat dissipation performance of the device can be greatly improved compared with the original substrate structure.

[0011] To achieve at least one of the above advantages of the present application, in a first aspect, the present application provides a semiconductor power discrete device based on a stripping substrate, comprising:

[0012] An epitaxial layer, wherein the epitaxial layer has a first surface and a second surface arranged opposite to each other;

[0013] A gate layer arranged on the first surface of the epitaxial layer, wherein the gate layer comprises a gate structure, a first passivation layer structure and a metal substrate, wherein the gate structure is close to the first surface, the first passivation layer structure is arranged opposite to both sides of the gate structure and protrudes from the gate structure at the end away from the epitaxial layer, and the metal substrate is located at the other end of the gate structure and the first passivation layer structure;

[0014] A functional layer arranged on the second surface of the epitaxial layer, wherein the functional layer comprises a second passivation layer structure, a source structure and a drain structure arranged side by side on the second surface, wherein the second passivation layer structure is between the source structure and the drain structure to insulate the source structure and the drain structure.

[0015] According to an embodiment of the present application, the thickness of the first passivation layer structure is 0.8um-1.5um.

[0016] According to an embodiment of the present application, the thickness of the gate structure is 0.05um-0.2um.

[0017] According to an embodiment of the present application, the thickness of the second passivation layer structure is 0.8um-1um.

[0018] According to an embodiment of the present application, the thickness of the source structure and the drain structure are equal and greater than or equal to 2um.

[0019] According to an embodiment of the present application, the epitaxial layer comprises a U-GaN layer and an AlGaN layer, wherein the U-GaN layer is close to the gate layer and the AlGaN layer is close to the functional layer.

[0020] In a second aspect, the present application further provides a method for manufacturing the aforementioned semiconductor power discrete device based on exfoliation substrate, comprising first forming the gate layer on the first surface of the epitaxial layer, and then forming the functional layer on the second surface of the epitaxial layer, wherein the method for forming the gate layer comprises the following steps:

[0021] S110, growing or depositing a passivation layer on the first surface of the epitaxial layer, wherein the thickness of the passivation layer is 0.8um-1.5um;

[0022] S120, etching the passivation layer close to the middle position to the epitaxial layer by using a wet HF method or a dry ICP etching process, removing the photoresist, and performing a cleaning process, thereby forming the first passivation layer structure on both sides of the part where the photoresist is removed;

[0023] S130, using a PVD process to manufacture a gate electrode on the part where the photoresist has been removed, then performing a RTA 550℃-650℃ rapid annealing treatment in an atmospheric environment, and finally performing a p-ohmic contact process to form the gate structure, wherein the thickness of the gate structure is 0.05um-0.2um;

[0024] S140, binding the metal substrate by using a binding process, thereby finally forming the gate layer;

[0025] wherein the method for forming the functional layer comprises the following steps:

[0026] S210, exfoliating the substrate of the semiconductor power device with the substrate;

[0027] S220, etching the buffer layer of the semiconductor power device to expose the epitaxial layer by using an ICP etching process;

[0028] S230, performing S&D photolithography on the surface of the epitaxial layer and performing a treatment, thereby forming the source structure and the drain structure;

[0029] S240, growing or depositing a passivation layer, etching the passivation layer at the source structure and the drain structure, then removing the photoresist, cleaning, forming the second passivation layer structure isolated between the source structure and the drain structure.

[0030] According to an embodiment of the present application, in step S110, the passivation layer is formed by growing SiO2, SiONx or SiONx by PECVD method, or by Sputter, PVD or TEOS deposition.

[0031] According to an embodiment of the present application, in step S210, the substrate is removed by laser stripping process, or removed by wet etching process, wherein the wet etching solution is a mixture of HNO3, CH3COOH and HF in a predetermined ratio.

[0032] According to an embodiment of the present application, in step S230, the processing includes: first etching by ICP, then sequentially evaporating electrodes Ni / Au / Ni / Au by PVD process, then performing left-off process, and finally performing organic cleaning and placing in N2 for 1-5L / min RTA annealing, wherein the annealing time is 4.5min-5.5min.

[0033] These and other objects, features and advantages of the present application will become apparent with reference to the following detailed description of the preferred embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 A front view structural schematic diagram of a semiconductor power discrete device based on substrate stripping according to a preferred embodiment of the present application is shown.

[0035] Figure 2 A variation schematic diagram of step S210 and step S220 according to a preferred embodiment of the present application is shown.

[0036] Reference signs: 10-gate layer, 101-gate structure, 102-first passivation layer structure, 103-metal substrate, 20-epitaxial layer, 30-functional layer, 301-source structure, 302-second passivation layer structure, 303-drain structure. DETAILED DESCRIPTION

[0037] The following description is presented to enable any person skilled in the art to practice the present application as claimed. The preferred embodiments disclosed herein are only examples of the present application and alternative embodiments will be apparent to those skilled in the art. The patentable scope of the present application is defined by the appended claims and can include other embodiments that offer optional features separately or in combination with the preferred embodiments disclosed herein.

[0038] It is to be understood that the terms "longitudinal", "transverse", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like as used herein with reference to the orientation or position of an item or element indicate the orientation or position as shown in the drawings, which are for purposes of illustration and description only, and do not indicate or imply that the item or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as a limitation of the invention.

[0039] It is to be understood that the term "one" is to be understood as "at least one" or "one or more" such that a quantity of an element can be either one or more than one. The term "one" is not to be construed as limiting the quantity to only one.

[0040] Reference Figure 1 A semiconductor power discrete device based on a peel-off substrate according to a preferred embodiment of the present application will be described in detail below, wherein the semiconductor power discrete device based on a peel-off substrate comprises an epitaxial layer 20, a gate layer 10 and a functional layer 30.

[0041] The epitaxial layer 20 has a first surface and a second surface arranged oppositely, wherein the gate layer 10 is arranged on the first surface of the epitaxial layer 20, and comprises a gate structure 101, a first passivation layer structure 102 and a metal substrate 103. The gate structure 101, also referred to as a gate electrode or G electrode, is close to the first surface. The first passivation layer structure 102 is arranged on both sides of the gate structure 101 and protrudes from the gate structure 101 at the end away from the epitaxial layer 20. The metal substrate 103 is arranged at the other end of the gate structure 101 and the first passivation layer structure 102, and can simultaneously play a supporting and conductive role.

[0042] In an embodiment, the thickness of the first passivation layer structure 102 is 0.8um-1.5um, such as 0.9um, 1.0um, 1.2um or 1.4um, etc. The first passivation layer structure 102 can be any one of SiO2, Si3N4, SiONx or Polyimide.

[0043] In an embodiment, the thickness of the gate structure 101 is 0.05um-0.2um, such as 0.08um, 0.1um, 0.13um, 0.16um or 0.18um, etc. Generally, the thickness of the gate structure 101 is much smaller than the thickness of the first passivation layer structure 102.

[0044] The functional layer 30 is arranged on the second surface of the epitaxial layer 20, and includes a second passivation layer structure 302, a source structure 301 and a drain structure 303 arranged side by side on the second surface, wherein the second passivation layer structure 302 is arranged between the source structure 301 and the drain structure 303 to isolate the source structure 301 and the drain structure 303.

[0045] In one embodiment, the thickness of the second passivation layer structure 302 is 0.8-1 um, such as 0.85 um, 0.9 um or 0.95 um, and the second passivation layer structure 302 can be any one of SiO2, Si3N4, SiNx, SiONx or Polyimide.

[0046] Further preferably, the thickness of the source structure 301 and the drain structure 303 is equal and greater than or equal to 2 um.

[0047] In one embodiment, the epitaxial layer 20 includes a U-GaN layer and an AlGaN layer, wherein the U-GaN layer is close to the gate layer 10, and the AlGaN layer is close to the functional layer 30.

[0048] It should be noted that in a conventional semiconductor power device, S (source electrode), D (drain electrode) and G (gate electrode) are located on the front surface of the other surface of the substrate, and the above three electrodes need to be separately connected by wire bonding. In the present application, the substrate of the conventional semiconductor power device is peeled off, and a metal substrate 103, or a copper substrate, is used instead, which can attach the functional layer 30 to a packaging support, and only needs to be connected by wire bonding at the electrode end of the metal substrate 103, thereby greatly reducing the number of solder wires and the possibility of wire bonding;

[0049] In addition, it is also worth mentioning that since the source structure 301 and the drain structure 303 are on the second surface of the epitaxial layer 20, and the gate structure 101 is on the first surface of the epitaxial layer 20, the distance between the source structure 301 and the drain structure 303 can be greatly reduced under the same current (by reducing the width of the second passivation layer structure, while in a conventional semiconductor power device, the distance between the source structure and the drain structure cannot be reduced due to the presence of the gate structure), so that the overall area of the device provided by the present application can be greatly reduced, thereby greatly increasing the number of chip devices that can be made in a wafer, making the device provided by the present application more convenient to use and more widely applicable.

[0050] In addition, taking a hemt device with 1200V20A as an example, the G electrode originally needs to use Au with a thickness of 10 um, and the device provided in the application adopts the metal substrate 103 connection instead of Au, and at the same time, since the source electrode structure 301 and the drain electrode structure 303 can be directly pasted to the packaging support, the thickness of the metal substrate 103 can be reduced to 2 um, thereby greatly reducing the thickness of the entire device, and also greatly reducing the resistance and resistance consumption of the device, and improving the overall performance of the device;

[0051] The device provided in the application can make the packaging support realize unified standardization, and it is no longer necessary to design a support mold for different forms of chips, thereby greatly reducing the packaging cost;

[0052] At the same time, the chip provided in the application also has two erection modes, one of which is to paste one side of the metal substrate 103 to the packaging support for heat dissipation, and the heat conduction efficiency of metal is better than that of sapphire, silicon and other substrates, so that the heat dissipation efficiency of the device can be greatly improved; the other is to directly paste one side of the functional layer 30 to the packaging support for heat dissipation in a flip-chip manner, and the heat conduction efficiency of metal is also better than that of sapphire, silicon and other substrates, so that the heat dissipation efficiency of the device can be greatly improved, thereby further improving the overall performance of the device;

[0053] Finally, the structure of the device provided in the application is simpler, and the yield and performance of the product can be more easily improved in the process, for example, the line width of the G electrode of the original middle and high power power electronic switching device needs to be 0.5 um, and in the case of not affecting the performance of the power electronic switch, the line width of the G electrode in the device provided in the application can be 1 um.

[0054] In a second aspect, the application further provides a method for manufacturing the aforementioned semiconductor power discrete device based on a separation substrate, comprising first forming the gate layer on the first surface of the epitaxial layer to provide support for the epitaxial layer when the functional layer is subsequently formed, and then forming the functional layer on the second surface of the epitaxial layer, wherein the method for forming the gate layer comprises the following steps, in combination with Figure 2 :

[0055] S110, growing or depositing a passivation layer on the first surface of the epitaxial layer, wherein the thickness of the passivation layer is 0.8-1.5um, such as 0.9um, 1.0um, 1.2um or 1.4um, etc., wherein, when growing, the first passivation layer can be any one of SiO2, Si3N4, SiNx, SiONx or Polyimide structure, which is grown by PECVD process, wherein, when depositing, SiO2 can be formed by Sputter, PVD or TEOS deposition;

[0056] S120, using wet HF or BHF method to etch or using dry ICP process to etch the passivation layer close to the middle position to the epitaxial layer, removing photoresist, and performing cleaning treatment such as O2-PLASMA and SPM process, forming the first passivation layer structure on both sides of the removed photoresist part;

[0057] S130, using PVD process to make gate electrode (such as Ni / Au=20nm / 20nm) on the part where the photoresist has been removed, then performing RTA 550-650℃ rapid annealing treatment in air environment, generally 600℃ rapid annealing treatment for 5min, and finally performing p-ohmic contact process to form the gate structure, wherein the thickness of the gate structure is 0.05-0.2um, such as 0.08um, 0.1um, 0.13um, 0.16um or 0.18um, etc. Generally, the thickness of the gate structure is much smaller than the thickness of the first passivation layer structure;

[0058] S140, binding the metal substrate by using binding process to finally form the gate layer, wherein in the binding process, first PVD process is used to evaporate Ni / Pt / Au / Cu=20nm / 50nm / 200 / 50nm, then CuSO4 solution is used for electroplating 20um, then another piece of 500um Cu is taken, and finally the binding process is used to bind the first passivation layer structure and the gate structure on the surface of the device together;

[0059] The method for forming the functional layer comprises the following steps:

[0060] S210, peeling off the substrate of the semiconductor power device with the substrate, which can be a sapphire substrate or a Si substrate;

[0061] S220, using ICP etching process CL2+BCl3 to etch the buffer layer of the semiconductor power device to expose the epitaxial layer, such as when the thickness of the Buffer layer is 50nm and the thickness of the U-GaN layer is 1um, the etching depth is 1.05um;

[0062] S230, performing S&D lithography on the surface of the epitaxial layer and processing to form the source structure and the drain structure;

[0063] S240, growing or depositing a passivation layer, etching the passivation layer at the source structure and the drain structure, growing or depositing the passivation layer in the manner shown in step S110, then removing the photoresist, and performing cleaning processing, removing the photoresist and then performing cleaning processing in the manner shown in step S120, to form the second passivation layer structure insulated between the source structure and the drain structure.

[0064] In one embodiment, in step S210, the substrate is stripped by a laser stripping process, or is etched and removed by a wet etching process, wherein the wet etching solution is a mixture of HNO3, CH3COOH and HF in a predetermined ratio, such as HNO3: CH3COOH: HF = 1:3:6.

[0065] Further preferably, in step S230, the processing includes: first performing CL2 etching by ICP, then sequentially evaporating electrodes Ni / Au / Ni / Au = 50nm / 50nm / 50nm / 500nm by a PVD process, then performing a left-off process, and finally performing organic cleaning and then performing RTA annealing in N2 at 1-5L / min (such as 1.5, 2, 3, 3.5 or 4L / min), wherein the annealing time is 4.5min-5.5min, preferably 5min.

[0066] It should be noted that the terms "first", "second" in the present application are only used for descriptive purposes, and do not indicate any order, and should not be understood as indicating or implying relative importance, and these terms can be interpreted as names.

[0067] It should be understood by those skilled in the art that the above description and the embodiments of the application shown in the drawings are only examples and do not limit the application. The advantages of the application have been fully and effectively achieved. The functions and structural principles of the application have been shown and described in the embodiments, and the embodiments of the application can be modified or changed in any way without departing from the principles.

Claims

1. A semiconductor power discrete device based on a stripped substrate, characterized in that, include: An epitaxial layer, wherein the epitaxial layer has a first surface and a second surface disposed opposite to each other; A gate layer is disposed on the first surface of the epitaxial layer, wherein the gate layer includes a gate structure, a first passivation layer structure and a metal substrate, wherein the gate structure is close to the first surface, the first passivation layer structure is disposed opposite to both sides of the gate structure and protrudes from the gate structure at the end away from the epitaxial layer, and the metal substrate is located on the surface of the gate structure and the first passivation layer structure away from the epitaxial layer. A functional layer is disposed on the second surface of the epitaxial layer, wherein the functional layer includes a second passivation layer structure, a source structure and a drain structure disposed side by side on the second surface, wherein the second passivation layer structure is disposed between the source structure and the drain structure to isolate the source structure and the drain structure; The epitaxial layer includes a U-GaN layer and an AlGaN layer, wherein the U-GaN layer is close to the gate layer and the AlGaN layer is close to the functional layer.

2. The semiconductor power discrete device based on a stripped substrate as described in claim 1, characterized in that, The thickness of the first passivation layer structure is 0.8 μm to 1.5 μm.

3. The semiconductor power discrete device based on a stripped substrate as described in claim 2, characterized in that, The thickness of the gate structure is 0.05μm to 0.2μm.

4. The semiconductor power discrete device based on a stripped substrate as described in any one of claims 1 to 3, characterized in that, The thickness of the second passivation layer structure is 0.8 μm to 1 μm.

5. The semiconductor power discrete device based on a stripped substrate as described in claim 4, characterized in that, The source structure and the drain structure have the same thickness, and both are greater than or equal to 2 μm.

6. A method for manufacturing a semiconductor power discrete device based on a stripped substrate as described in any one of claims 1 to 5, characterized in that, The method includes first forming the gate layer on the first surface of the epitaxial layer, and then forming the functional layer on the second surface of the epitaxial layer, wherein the method of forming the gate layer includes the following steps: S110, a passivation layer is deposited on the first surface of the epitaxial layer, wherein the thickness of the passivation layer is 0.8 μm to 1.5 μm; S120, the passivation layer near the center is etched to the epitaxial layer using wet HF etching or dry ICP process, the photoresist is removed, and a cleaning process is performed to form the first passivation layer structure on both sides of the photoresist-removed portion. S130, a gate electrode is fabricated using PVD process on the part where the photoresist has been removed, and then subjected to RTA rapid annealing treatment at 550℃~650℃ in an atmospheric environment. Finally, an ohmic contact process is performed to form the gate structure, wherein the thickness of the gate structure is 0.05μm~0.2μm. S140, the metal substrate is bonded using a bonding process to ultimately form the gate layer; The method for forming the functional layer includes the following steps: S210, stripping the substrate of a semiconductor power device with a substrate; S220, the buffer layer of the semiconductor power device is etched using an ICP etching process until the epitaxial layer is exposed; S230, S&D lithography is performed on the surface of the epitaxial layer, and the process is carried out to form the source structure and the drain structure; S240, deposit a passivation layer, etch the passivation layer at the source structure and the drain structure, then remove the photoresist and perform a cleaning process to form a second passivation layer structure that is isolated between the source structure and the drain structure.

7. The method for manufacturing a semiconductor power discrete device based on a stripped substrate as described in claim 6, characterized in that, In step S110, SiO2 or SiON is grown by PECVD. X The passivation layer is formed by sputtering, PVD, or TEOS deposition.

8. The method for manufacturing a semiconductor power discrete device based on a stripped substrate as described in claim 7, characterized in that, In step S210, the substrate is peeled off using a laser lift-off process or the substrate is removed by a wet etching process, wherein the wet etching solution is a mixture of HNO3, CH3COOH and HF mixed in a predetermined ratio.

9. The method for manufacturing a semiconductor power discrete device based on a stripped substrate as described in claim 8, characterized in that, In step S230, the process includes: firstly, ICP etching with Cl2, then sequentially depositing Ni / Au / Ni / Au electrodes using PVD process, followed by a stripping process, and finally, organic cleaning followed by RTA annealing in N2 at a rate of 1-5 L / min, wherein the annealing time is 4.5 min-5.5 min.

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