Differential residual amplifier using SCCMFB to eliminate tail current sources and improve gain

Abstract

A differential residual amplifier positioned between multiple stages of an analog-to-digital converter (ADC). A switched-capacitor common-mode feedback circuit determines the voltage shift. An AC-coupled input network uses switched capacitors to shift the voltage to the differential input of the residual amplifier upwards to apply to the upper pair of p-channel differential transistors whose sources are connected to the power supply. The AC-coupled input network also shifts the voltage to the differential input of the residual amplifier downwards to apply to the lower pair of n-channel differential transistors whose sources are grounded. The drains of the p-channel differential transistors are connected to the differential output via p-channel cascode transistors. The n-channel cascode transistors connect the drains of the n-channel differential transistors to the differential output. The drains of the differential transistors can be connected to the input of the differential amplifier to drive the gates of the cascode transistors, thereby achieving a gain boost. No tail current is used to allow for a wider output voltage swing at lower supply voltages.

Description

Technical Field

[0001] This invention relates to residual amplifiers, and more specifically, to low-voltage residual amplifiers in analog-to-digital converters (ADCs) without tail current sources. Background Technology

[0002] Analog-to-digital converters (ADCs) are widely used in many applications. Some applications require both high accuracy and high sampling speed. Using multi-bit ADCs, high accuracy, such as 8-bit to 12-bit, can be achieved.

[0003] Figure 1 The capacitor array in the ADC is shown. The converter 101 has a weighted array of capacitors 20, 26, and 28, which share the charge at the input of comparator 12, which generates a digital bit VCOMP of 1 when the + input of the comparator has a voltage higher than the - input.

[0004] A controller or sequencer (not shown) controls switches 16 and 18, which allow various voltages to be switched to the outer or bottom plates of capacitors 20, 26, and 28. Each switch can be controlled individually. Successive approximation (SA) routines can be used to sequentially switch smaller capacitors on or off to test different digital values ​​and see which digital value best approximates the analog input voltage.

[0005] For example, converter 101 can be initialized by setting all switches 16 and 18 to connect the common-mode voltage VCM to the outer plate of all capacitors 20, 26, and 28. The + and - input lines to comparator 12 can also be driven to VCM via an equalization switch (not shown). VCM can be generated using a 1:1 resistor divider as the midpoint between reference voltages (e.g., (Vrefp + Vrefn) / 2).

[0006] Then, during the sampling phase, the true analog voltage AINP (Vinp) is applied to the outer plates of all capacitors 20 and 26 connected to the + input terminal of comparator 12 on the inner (top) plate via switches 16 and 18, while the supplementary analog voltage AINN (Vinn) is applied to the outer plates of all capacitors 20 and 28 connected to the - input terminal of comparator 12 on the inner plate via switches 16 and 18. VCM is applied to both input terminals of comparator 12. Therefore, the differential analog input voltage is sampled onto the plates of capacitors 20, 26, and 28.

[0007] Next, during phase evaluation, switches 16 and 18 drive the VCM to all output boards, but the Successive-Approximation (SA) routine sequentially tests smaller capacitors driven by a reference voltage instead of the VCM.

[0008] For example, when testing the most significant bit (MSB) capacitors 26 and 28, the upper switch 18 connects the reference Vrefn to the outer plate of MSB capacitor 26, while the lower switch 18 connects the reference Vrefp to the outer plate of MSB capacitor 28. This switching causes charge sharing and a shift of charge between MSB capacitors 26 and 28 and the + and - input lines of comparator 12, which may toggle the digital output VCOMP. The SA routine can observe the toggling of VCOMP and, as a result, set it to clear the bits in the successive approximation register (SAR). By sequentially testing the smaller capacitor 20, the SA routine can fill the SAR with a good approximation of the analog input voltage.

[0009] Figure 2 A prior art multi-stage ADC with residual amplifiers is illustrated. Instead of a single converter 101 with multiple bits of resolution, multiple converters 106, 116 can be used in multiple stages. For example, instead of a single 12-bit converter 101, the first converter 106 can generate 5 bits (most significant bit, MSB), while the second converter 116 generates an additional 8 bits (least significant bit, LSB).

[0010] An input voltage VIN is applied to a first converter 106, which may have an array of capacitors and switches, as for converter 101. Figure 1 As shown in the diagram. The first converter 106 uses the SA routine to switch the switch until the final code is found and stored in the first SAR SAR1 108.

[0011] Then, Figure 1 The residual voltage on the + input of comparator 12 is applied to the inverting (-) input of residual amplifier 22 and amplified to drive the analog voltage input to the second converter 116. Like converter 101, the second converter 116 has an array of capacitors and switches and uses an SA routine to switch the switches until the final code is found and stored in the second SAR SAR2 118.

[0012] Feedback capacitor 104 feeds the output of residual amplifier 22 back to its inverting (-) input, while the non-inverting (+) input of residual amplifier 22 is connected to ground. The closed-loop gain is C1 / C2 > 1, where C1 is the capacitor of the first converter 106 and C2 is the capacitor of feedback capacitor 104. C1 does not change with the code in SAR1 108.

[0013] In the actual circuit, a small non-zero offset error exists in the residual amplifier 22, which can be modeled by the offset voltage 102 connected between the non-inverting (+) input of the residual amplifier 22 and ground. This VOS error may be caused by a mismatch in the residual amplifier 22. Since the VOS occurs within the residual amplifier 22 or before its input, this VOS error is amplified by the closed-loop gain of the residual amplifier 22 and applied to the input of the second converter 116. When this error is large, the second converter 116 may not be able to correct it.

[0014] The circuit design of residual amplifier 22 may increase the offset error VOS within it. A poorly designed amplifier may increase VOS mismatch. Asymmetrical amplifiers or amplifiers with unbalanced or mismatched sides may increase the offset error within residual amplifier 22. Fully differential signals are typically used instead of single-ended signals to reduce offset.

[0015] Figure 3 An amplifier of the prior art is shown. The residual amplifier 22' has a tail current source 240 that draws current from sources in the n-channel transistors 234 and 236. Current mirrors in the p-channel transistors 230 and 232 connect their gates together as a mirror current source. Resistors 242 and 244 are connected in series between the drains of transistors 230 and 232, driving the gates of transistors 230 and 232 at an intermediate node between resistors 242 and 244.

[0016] The drains of transistors 230 and 234 are connected together to drive the VOUTN output, while the drains of transistors 232 and 236 are connected together to drive the VOUTP output. VOUTP and VOUTN form a differential output, while VINP and VINN are differential inputs.

[0017] The input VINP of differential amplifier 22' is applied to the gate of transistor 234, while the input VINN of differential amplifier 22' is applied to the gate of transistor 236. P-channel transistors 230 and 232 can be long-channel devices, while n-channel transistors 234 and 236 can be short-channel fast devices with good Gm. Resistors 242 and 244 can be well-matched resistors, such as thin-film resistors.

[0018] While the differential residual amplifier 22' is useful, a tail current source 240 is still needed to precisely define the bias current for the differential pair of n-channel transistors 234, 236. The tail current source 240 reduces the maximum possible output voltage swing. When using very low supply voltages (e.g., 0.9 volts), the reduction in output voltage swing caused by the tail current source 240 is significant and undesirable.

[0019] Any non-ideal factors in the residual amplifier 22' can affect the accuracy of the entire pipelined SAR ADC. For high-resolution ADCs, the input reference noise of the residual amplifier 22' should meet the noise floor requirements of the entire ADC. This is one of the bottlenecks in amplifier design. The settling speed of the residual amplifier 22' must be fast enough for high-speed ADCs. Low distortion is desired at the output of the residual amplifier 22'. Moderate open-loop gain and large signal sway are desirable. When the ADC converter operates with a low-voltage core supply, then the residual amplifier 22' should be able to operate with the same low-voltage core supply. The equivalent offset of the output of the residual amplifier 22' needs to be less than the allowable redundancy range of the ADC. Good phase margin for stable amplification or auto-zeroing phase is also desirable. Low power consumption is especially desirable, but may be the most difficult to achieve and may be a fundamental limitation.

[0020] A differential residual amplifier without a tail current source is needed. A differential amplifier that operates at a low supply voltage but still has a wide output voltage swing is needed. A high-gain, low-voltage, wide-swing differential amplifier is needed as a residual amplifier between stages in a high-speed, high-resolution pipelined ADC. Summary of the Invention

[0021] This invention provides a differential amplifier, comprising: a differential input having a true input and a supplementary input; an input shifter receiving the differential input for generating an upper differential input and a lower differential input, the input shifter shifting the common-mode voltage of the differential input upward to generate the upper differential input, and the input shifter shifting the common-mode voltage of the differential input downward to generate the lower differential input; a true first-type differential transistor having a control node for receiving the true input of the upper differential input and having a conduction path connected between a power supply and the true upper node; a supplementary first-type differential transistor having a control node for receiving the supplementary input of the upper differential input and having a conduction path connected between the power supply and the supplementary upper node; and a true first-type cascode transistor having a control node connected between the true upper node and the supplementary upper node. The following are considered as separate components: a conduction path between the output nodes; a supplementary first-type cascode transistor having a conduction path connecting the supplementary upper node and the true output node; a true second-type differential transistor having a control node for receiving the true input of the lower differential input and a conduction path connecting ground and the true lower node; a supplementary second-type differential transistor having a control node for receiving the supplementary input of the lower differential input and a conduction path connecting ground and the supplementary lower node; a true second-type cascode transistor having a conduction path connecting the true lower node and the supplementary output node; and a supplementary second-type cascode transistor having a conduction path connecting the supplementary lower node and the true output node; wherein the true output node and the supplementary output node form a differential output.

[0022] The present invention also provides a residual amplifier, comprising: a differential input having a true input and a supplementary input; an input shifter receiving the differential input for generating an upper differential input and a lower differential input, the input shifter shifting the differential input upward in voltage to generate the upper differential input, the input shifter shifting the differential input downward in voltage to generate the lower differential input; a true p-channel differential transistor having its gate receiving the true input of the upper differential input, its source connected to a power supply, and its drain connected to a true upper node; a supplementary p-channel differential transistor having its gate receiving the supplementary input of the upper differential input, its source connected to the power supply, and its drain connected to a supplementary upper node; and a true p-channel cascode transistor having its source connected to the true upper node and its drain connected to a supplementary upper node. A supplementary p-channel cascode transistor is connected to the supplementary upper node, and its drain is connected to the true output node; a true n-channel differential transistor receives the true input of the lower differential input at its gate, its source is connected to ground, and its drain is connected to the true lower node; a supplementary n-channel differential transistor receives the supplementary input of the lower differential input at its gate, its source is connected to ground, and its drain is connected to the supplementary lower node; a true n-channel cascode transistor receives the supplementary input of the lower differential input at its gate, its source is connected to ground, and its drain is connected to the supplementary lower node; a true n-channel cascode transistor receives the true input of the lower differential input at its gate, and its drain is connected to the supplementary output node; and a supplementary n-channel cascode transistor receives the supplementary lower node at its source, and its drain is connected to the true output node; wherein the true output node and the supplementary output node form a differential output.

[0023] The present invention also provides a differential residual amplifier, comprising: a differential input having a VIP input and a VIN input, wherein VIP and VIN are complementary; a voltage shifter receiving the differential input for generating an upper differential input having a VIPN input and a VIPP input, and for generating a lower differential input having a VINP input and a VINN input, the voltage shifter shifting the common-mode voltage of the differential input upward to generate the upper differential input, and the voltage shifter shifting the common-mode voltage of the differential input downward to generate the lower differential input; a true p-channel differential transistor having its gate receiving the VIPP input, its source connected to a power supply, and its drain connected to a true upper node; and a supplementary p-channel differential transistor having its gate receiving the VIPN input, its source connected to the power supply, and its drain connected to a true upper node. The following are additional nodes: a true p-channel cascode transistor with its source connected to the true upper node and its drain connected to the VON output; a supplementary p-channel cascode transistor with its source connected to the supplementary upper node and its drain connected to the VOP output; a true n-channel differential transistor with its gate receiving the VINP input, its source connected to ground, and its drain connected to the true lower node; a supplementary n-channel differential transistor with its gate receiving the VINN input, its source connected to ground, and its drain connected to the supplementary lower node; a true n-channel cascode transistor with its source connected to the true lower node and its drain connected to the VON output; and a supplementary n-channel cascode transistor with its source connected to the supplementary lower node and its drain connected to the VOP output; wherein the VOP output and the VON output form a differential output. Attached Figure Description

[0024] Figure 1 A capacitor array in a prior art ADC is shown.

[0025] Figure 2 A prior art multi-stage ADC with a residual amplifier is shown.

[0026] Figure 3 An amplifier based on existing technology is shown.

[0027] Figure 4 A fully differential multistage pipelined ADC with improved residual amplifiers between stages is shown.

[0028] Figure 5 This is a block diagram of the improved residual amplifier.

[0029] Figure 6 This is a schematic diagram of a main amplifier without a tail current source.

[0030] Figure 7 This is a schematic diagram of an AC-coupled input network.

[0031] Figure 8 This is a schematic diagram of the SCCMFB P circuit.

[0032] Figure 9 This is a schematic diagram of the SCCMFB N circuit.

[0033] Figure 10 This is a schematic diagram of a bias generator.

[0034] Figure 11 This is a schematic diagram of a common-mode voltage generator.

[0035] Figure 12 This is a common-source, common-gate embodiment of the main amplifier. Detailed Implementation

[0036] This invention relates to improvements in differential amplifiers. The following description is provided to enable those skilled in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to preferred embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the invention is not intended to be limited to the specific embodiments shown and described, but is to be given the broadest scope consistent with the principles and novel features disclosed herein.

[0037] Figure 4 A fully differential multistage pipelined ADC with improved residual amplifiers between stages is shown. Operation can be controlled using a simple two-phase clock. Phase P1 is the auto-zero phase of the residual amplifier 30, while phase P2 is the amplification phase of the residual amplifier 30.

[0038] During phase P1, the first capacitor array 32 and the second capacitor array 34 are used to convert the analog signal to digital and to reset or auto-zero the residual amplifier 30. During phase P2, the residual amplifier 30 amplifies the residual output from the first capacitor array 32 to drive the amplified residual into the second capacitor array 34. During phase P1, the first capacitor array 32 and the second capacitor array 34 are reset, equalized, and / or sampled.

[0039] Differential analog inputs AINP and AINN are applied to a first capacitor array 32, which has capacitors switched by a SAR1108. AINP switches to the capacitor connected to VXP, while AINN switches to the capacitor connected to VXN. During phase P1, the SA routine test switches different bits of the SAR1108 with different capacitors in the first capacitor array 32 until a digital value that best matches the MSB is found.

[0040] Switch 54 closes during phase P2 to connect VXP to VIP and the inverting (-) input of the differential residual amplifier 30. Switch 55 also closes during phase P2 to connect VXN to VIN and the non-inverting (+) input of the differential residual amplifier 30. Feedback capacitor 36 connects the -input VIP and +output VOP of the residual amplifier 30, while feedback capacitor 37 connects the +input VIN and -output VON of the residual amplifier 30. Amplifier stage 580 includes feedback capacitors 36 and 37 and switches 38 and 39, which reset or zero the residual amplifier 30 during phase P1.

[0041] Also during phase P2, switches 62 and 63 are closed to connect VOP to AINP2 and VON to AINN2. AINP2 and AINN2 are differential analog inputs to the second capacitor array 34. AINP2 switches to the capacitor connected to VYP, while AINN2 switches to the capacitor connected to VYN. During phase P1, the SA routine tests switching different bits of SAR2 118 with different capacitors in the second capacitor array 34 until a digital value that best matches the LSB is found.

[0042] Figure 5 This is a block diagram of the improved residual amplifier. The residual amplifier 30 has a main amplifier 500 without a tail current source, such as... Figure 6 As shown. Without a tail current source, the main amplifier 500 can simultaneously have p-channel differential pair transistors and n-channel differential pair transistors to achieve a wider output voltage swing at outputs VOP and VON.

[0043] The AC-coupled input network 510 receives the analog differential inputs VIP and VIN from the residual amplifier 30 and generates four inputs to the main amplifier 500. Inputs VIPP and VIPN are generated from VIP, while inputs VINP and VINN are generated from input VIN. Capacitors in the AC-coupled input network 510 provide AC coupling from the two inputs VIP and VIN to the four inputs VIPP, VIPN, VINP, and VINN. During the auto-zeroing phase P1, when the residual amplifier 30 auto-zeros, these capacitors switch to the common-mode voltage VCM and the switched feedback voltages VFB_P and VFB_N. Figure 7 The AC-coupled input network 510 is shown in detail.

[0044] The bias generator 550 is achieved by means of, for example, using Figure 10 The bias circuit shown generates bias voltages VBIASP and VBIAS. The common-mode voltage generator 540 uses, for example, [the following method is used]. Figure 11 The circuit generates a common-mode voltage VCM.

[0045] The Switched-Capacitor Common-Mode Feedback (SCCMFB) circuit 520 generates a switched feedback voltage VFB_P from the outputs VOP and VON and from VCM and the bias voltage VBIASP. The SCCMFB circuit 520 uses a switched capacitor in a ping-pong circuit, and as... Figure 8 As shown. Similarly, the SCCMFB N circuit 530 in... Figure 9 The ping-pong circuit shown uses a switched capacitor to generate a switched feedback voltage VFB_N from the outputs VOP and VON and from VCM and the bias voltage BVIASN.

[0046] Based on the bias generator 550 and the SCCMFB P circuit 520 and SCCMFB N circuit 530, the AC-coupled input network 510 defines appropriate common-mode values ​​for the VIPP, VIPN, VINP, and VINN inputs to the main amplifier 500.

[0047] These defined voltages, VIPP, VIPN, VINP, and VINN, allow the differential pair transistors in the main amplifier 500 to operate in the saturation region. The main amplifier 500 contains one differential pair p-channel transistor and another differential pair n-channel transistor.

[0048] Figure 6 This is a schematic diagram of a main amplifier without a tail current source. The main amplifier 500 has two pairs of differential transistors. The gates of the first differential pair of p-channel differential transistors 120 and 122 receive inputs VIPP and VINP, respectively, and their sources are connected to the VDD power supply. The gates of the second differential pair of n-channel differential transistors 130 and 132 receive inputs VIPN and VINN, respectively, and their sources are connected to the ground power supply. Differential transistors 120, 122, 130, and 132 operate in the saturation region because the AC-coupled input network 510 couples the VIP and VIN inputs to a bias-tuned common-mode voltage to generate the gate voltages of the differential transistors 120, 122, 130, and 132.

[0049] The current through the main amplifier 500 can be proportional to the bias current in the bias generator 550. For example, the size of the p-channel differential transistors 120 and 122 can be the same as that of the p-channel bias transistor 324 in the bias generator 550. Figure 10 The size of the n-channel differential transistors 130 and 132 can be N times that of the n-channel bias transistor 308. Figure 10 N times the size of ).

[0050] Common-source cascode transistors are inserted between the drains of differential transistors 120, 122, 130, and 132 and the outputs VOP and VON. These common-source cascode transistors can have longer gate lengths, thereby increasing the gain in the amplifier without increasing the input reference noise, power consumption, and delay of the main amplifier 500.

[0051] In the upper half of the amplifier, the current from the drain of p-channel differential transistor 120 flows through the channel of p-channel cascode transistor 124 to the output VON. The current from the drain of p-channel differential transistor 122 flows through the channel of p-channel cascode transistor 126 to the output VOP.

[0052] In the lower half of the amplifier, the current from the output VON flows through the channel of the n-channel cascode transistor 134 to the drain of the n-channel differential transistor 130. The current from the output VOP flows through the channel of the n-channel cascode transistor 136 to the drain of the n-channel differential transistor 132.

[0053] The gain boost is provided by differential amplifier 80, which receives the drain of p-channel differential transistor 120 at its non-inverting (+) input and the drain of p-channel differential transistor 122 at its inverting (-) input, and amplifies the voltage difference at its inputs to generate the inverting (-) output of p-channel cascode transistor 124 and the non-inverting (+) output of p-channel cascode transistor 126 applied to the gate.

[0054] The gain boost is also provided by differential amplifier 82 in the lower half of main amplifier 500. Differential amplifier 82 receives the drain of n-channel differential transistor 130 at its non-inverting (+) input and the drain of n-channel differential transistor 132 at its inverting (-) input, and amplifies the voltage difference at its inputs to generate its inverting (-) output applied to the gate of n-channel cascode transistor 134 and its non-inverting (+) output applied to the gate of n-channel cascode transistor 136.

[0055] Because there is no tail current source, differential transistors 120, 122, 130, and 132 can operate in the saturation region. The headroom voltage across differential transistors 120, 122, 130, and 132 is 4 * VDS. (SAT) VDS (SAT) This is the transistor's saturated drain-source voltage. The headroom for this voltage is approximately 500mV. When using a 0.9V supply VDD, the main amplifier 500 can still allow a 250mV peak-to-peak (Vpp) output voltage swing. Total harmonic distortion (THD) can be better than -75dBc.

[0056] The main amplifier 500 is formed with a common source and cascode common source, and has a gain boost that allows the residual amplifier 30 to have the lowest possible circuit noise (e.g., <400μVrms), good phase margin (>60 degrees), and moderate open-loop gain (typically >60dB).

[0057] High bandwidth is achieved by using Class AB push-pull differential transistors 120, 122, 130, and 132 to provide dual transconductance (dual Gm) to establish amplified output signals VOP and VON during phase P2 without tail current sources. The Class AB push-pull PMOS / NMOS differential pair transistors 120, 122, 130, and 132 allow for doubling the gain Gm used for establishment and the open-loop gain N*IBIAS used for the same current bias. Using push-pull differential transistors in conjunction with cascode transistors allows the differential transistors 120, 122, 130, and 132 to dominate circuit noise. This circuit can potentially achieve 60dB of open-loop gain without the need for a two-stage amplifier that might cause stability issues during establishment. The main amplifier 500 has only two current branches, and it can consume up to 90% of the power of the entire residual amplifier. The main amplifier 500 includes two PMOS and two NMOS differential transistors 120, 122, 130, and 132 for achieving rail-to-rail output oscillation. These transistors require only 4*VDS. (SAT) [For example, 500mV], which allows for high swing output at a low supply voltage of 0.9V VDD. The main amplifier 500 is symmetrical, containing identical positive (p-channel) and negative (n-channel) circuitry, which allows for good common-mode rejection and matching (good HD2 performance).

[0058] Figure 7 This is a schematic diagram of the AC-coupled input network. The AC-coupled input network 510 uses switched capacitors to shift the common-mode voltages at the VIPP, VIPN, VINP, and VINN inputs of the main amplifier 500. This voltage shift allows the differential transistors 120, 122, 130, and 132 in the main amplifier 500 to operate in saturation mode.

[0059] The AC-coupled input network 510 receives the common-mode voltage VCM from the common-mode voltage generator 540. The AC-coupled input network 510 also receives an upwardly adjusted common-mode feedback voltage VFB_P from the SCCMFB P circuit 520 and a downwardly adjusted common-mode feedback voltage VFB_N from the SCCMFB N circuit 530.

[0060] During phase P1, while the residual amplifier 30 is auto-zeroing, inputs VIP and VON are connected together via switch 160. All switches in the AC-coupled input network 510 are closed during auto-zeroing phase P1 and open during phase P2 when the residual amplifier 30 is amplifying. Therefore, capacitors 146, 148, 156, and 158 are applied to the AC-coupled input network 510 during auto-zeroing phase P1. The voltage difference applied to capacitors 146, 148, 156, and 158 during phase P1 is then applied to inputs VIP and VIN, causing their voltages to shift during amplification phase P2.

[0061] Capacitor 146 is connected between input VIP and output VIPP. During phase P1, switches 142 and 140 are closed to connect capacitor 146 between VFB_P and VCM. Therefore, during phase P1, capacitor 146 is pre-charged using VFB_P-VCM, which is applied to VIPP and main amplifier 500 during amplification phase P2. Thus, VIP is shifted upward by VFB_P-VCM via the AC-coupled input network 510.

[0062] Capacitor 148 is connected between input VIP and output VIPN. During phase P1, switches 140 and 144 are closed to connect capacitor 148 between VCM and VFB_N. Therefore, during phase P1, capacitor 148 is pre-charged using VCM-VFB_N, which is applied to VIPN and main amplifier 500 during amplification phase P2. This shifts VIP down by VCM-VFB_N.

[0063] On the right half of the AC-coupled input network 510, capacitor 156 is connected between input VIN and output VINP. During phase P1, switches 152 and 150 are closed to connect capacitor 156 between VFB_P and VCM. Therefore, during phase P1, capacitor 156 is pre-charged using VFB_P-VCM, which is applied to VINP and main amplifier 500 during amplification phase P2. Thus, VIN is shifted upward by VFB_P-VCM through the AC-coupled input network 510.

[0064] Capacitor 158 is connected between input VIN and output VINN. During phase P1, switches 150 and 154 are closed to connect capacitor 158 between VCM and VFB_N. Therefore, during phase P1, capacitor 158 is pre-charged using VCM-VFB_N, which is applied to VINN and main amplifier 500 during amplification phase P2. Thus, VIN is shifted down by VCM-VFB_N through capacitor 158.

[0065] Figure 8 This is a schematic diagram of the SCCMFB P circuit. The SCCMFB P circuit 520 generates an upwardly adjusted common-mode feedback voltage VFB_P, which is applied to the AC-coupled input network 510 to shift the voltage of the input VIP upwards.

[0066] The SCCMFB P circuit 520 receives the common-mode voltage VCM and VBIASP from the bias generator 550 as inputs. VBIASP can be higher than the bias voltage of VCM. The SCCMFB P circuit 520 also receives the outputs VOP and VON from the main amplifier 500, samples VOP onto capacitors 171 and 191, and samples VON onto capacitors 181 and 195. The other terminals of capacitors 171, 191, 181, and 195 are connected together to output VFB_P. Therefore, VFB_P will be the average midpoint voltage of VOP-VON, but its voltage is shifted upwards by other components in the SCCMFB P circuit 520. Ideally, this upward voltage shift is a function of VBIASP-VCM.

[0067] During phase P1, switches 162 and 164 are closed to apply VCM and VBIASP to the terminals of capacitor 170. Then, in phase P2, switches 166 and 168 are closed to transfer charge from capacitor 170 to capacitor 171. A portion of the VBIASP-VCM voltage difference stored on capacitor 170 is applied to capacitor 171 to add to VOP when capacitor 171 generates VFB_P. The amount of the transferred voltage difference VBIASP-VCM depends on the capacitance ratio of capacitors 170 and 171.

[0068] Similarly, during phase P1, switches 172 and 174 are closed to apply VCM and VBIASP to the terminals of capacitor 180. Then, in phase P2, switches 176 and 178 are closed to transfer charge from capacitor 180 to capacitor 181. A portion of the VBIASP-VCM voltage difference stored on capacitor 180 is applied to capacitor 181 to be added to VON when capacitor 181 generates VFB_P.

[0069] The ping circuit 400 includes capacitors 170, 171, 180, and 181, and switches 162-168 and 172-178, thereby driving capacitors 171 and 181 during phase P2. The pong circuit 402 is identical to the ping circuit 400, but with the opposite clock timing. During phase P2, switches 182, 184, 192, and 194 are closed to pre-charge capacitors 190 and 197 using the VBIASP-VCM. Then, during phase P1, switches 186, 188, 196, and 198 are closed to share charge for capacitors 191 and 195.

[0070] Therefore, the ping circuit 400 loads capacitors 171 and 181 during phase P2, while the pong circuit 402 loads capacitors 191 and 195 during phase P1. The capacitors 171, 191, 181, and 195 are charged alternately in a ping-pong manner by the ping circuit 400 and the pong circuit 402. This ping-pong action provides a more stable output for VFB_P.

[0071] Figure 9 This is a schematic diagram of the SCCMFB N circuit. The SCCMFB N circuit 530 generates a down-adjusted common-mode feedback voltage VFB_N, which is applied to the AC-coupled input network 510 to shift the voltage of the input VIN down.

[0072] The SCCMFB N circuit 530 has the same structure and operation as the SCCMFB P circuit 520, but receives a VBIASN that may be lower than the VCM and generates a VFB_N that may also be lower than the VCM.

[0073] The ping circuit 400' receives VCM and BVIASN and adjusts VOP down a portion of VCM-VBIASN to generate a stable VFB_N during phase P1. The pong circuit 402' also receives VCM and BVIASN and adjusts VOP down a portion of VCM-VBIASN to generate a stable VFB_N during phase P2.

[0074] The SCCMFB P circuit 520 and SCCMFB N circuit 530 help define the appropriate output common-mode of the main amplifier 500 as a constant VCM to properly bias the differential transistors 120, 122, 130, and 132. Tail current sources, common in the prior art, are not required. The main amplifier 500 provides maximum output swing to the residual amplifier 30 with moderate open-loop gain.

[0075] The ping circuit 400 and the pong circuit 402 work together to provide a constant and well-defined output common-mode voltage. The bias currents and gain Gm of these two phases P1 and P2 are also stable and constant.

[0076] Figure 10 This is a schematic diagram of a bias generator. The bias generator 550 generates bias voltages VBIASP and VBIASN from the power supply voltage VDD and ground.

[0077] Current source 338 drives current to ground through series-connected n-channel transistors 330, 332, 334, and 336. The gates of these transistors are connected together and then connected to the drain of the upper n-channel transistor 330 to generate VB1. VB1 drives the gates of n-channel transistors 320, 328, and 302 in other branches. Capacitor 348 filters the voltage VB1.

[0078] In the second branch, current source 340 drives current from VDD to the drain of n-channel transistor 320, which is connected in series with n-channel transistor 322 to ground. The drain of n-channel transistor 320 generates a low bias voltage BVIASN, which is filtered by capacitor 346 connected to ground. BVIASN is applied to the gates of n-channel transistors 322, 308, and 304.

[0079] In the fourth branch, p-channel transistors 310, 312, 314, and 316 are connected in series, and their gates are connected together and connected to the drain of the lower p-channel transistor 316 to generate VB2. A capacitor 344 to VDD filters the voltage VB2. The drain of the lower p-channel transistor 316 is connected to the drain of the n-channel transistor 302, and n-channel transistors 302 and 304 are connected in series to ground.

[0080] In the third branch, p-channel transistors 324 and 326 and n-channel transistors 328 and 308 are connected in series between VDD and ground. The drains of p-channel transistor 326 and n-channel transistor 328 are connected together to drive the upper bias voltage VBIASP. The upper bias voltage VBIASP is filtered by capacitor 342 and drives the gate of the upper p-channel transistor 324. The gate of the lower p-channel transistor 326 is driven by VB2.

[0081] Figure 11This is a schematic diagram of a common-mode voltage generator. The common-mode voltage generator 540 has resistors 702 and 704 connected in series between the analog power supply AVDD and ground to generate VCM1, which is filtered by a capacitor 706 to ground. Resistors 702 and 704 may have the same resistance for VCM = AVDD / 2. Operational amplifier 708 receives VCM1 at its non-inverting (+) input and feeds its output back to its inverting (-) input to generate the common-mode voltage VCM. Operational amplifier 708 may be large enough to keep VCM stable when many devices are connected to it and VCM has a large load.

[0082] Figure 12 This is a cascode-only implementation of the main amplifier. Main amplifier 500 ( Figure 6 The differential amplifiers 80 and 82 provide a gain boost but draw additional power. Only the cascode main amplifier 500' eliminates the need for differential amplifiers 80 and 82. The gates of the p-channel cascode transistors 124 and 126 are fed from the bias generator 550. Figure 10 The gates of the n-channel cascode transistors 134 and 136 are driven by the bias voltage VB2, while the gates of the cascode transistors 134 and 136 are driven by the bias voltage VB1.

[0083] By using a cascode-only master amplifier 500', power and area are saved. Some applications may not require gain boost, and a more modest open-loop gain can be achieved with the residual amplifier 30.

[0084] Alternative embodiments

[0085] The inventors have envisioned several other embodiments. For example, a level shifter can be added between, for instance, the core reference buffer and the plurality of ADC channels. The voltage levels assigned to power and ground can be shifted to define the common-mode or intermediate range of the power supply as ground with positive and negative power supply terminals, wherein the negative power supply terminal is the old ground.

[0086] Many circuit implementations and variations are possible. For example, different numbers of series transistors can be used in the bias generator 550 for different VDD values ​​and different processes and environments. Numerous variations are possible in the bias generator 550, common-mode voltage generator 540, and other circuits. The size or proportions of components can be adjusted for different power requirements or other reasons.

[0087] The capacitance ratio of the capacitors in the AC-coupled input network 510, SCCMFB P circuit 520, and SCCMFB N circuit 530 can be adjusted to change filtering, charge sharing, or other parameters. Other types of voltage shifters or level shifters can be used to replace the capacitor-based AC level shifter in the AC-coupled input network 510, SCCMFB P circuit 520, and SCCMFB N circuit 530. Capacitors perform ideally at high frequencies, but at lower frequencies, significant transcapacitor losses and inefficient voltage shifting may occur in the AC-coupled input network 510, SCCMFB P circuit 520, and SCCMFB N circuit 530. Therefore, designs using capacitors for AC voltage shifting are best suited for high-frequency ADCs, rather than static or very low-frequency ADCs.

[0088] Equalization can be performed by a single switch that connects the P and N lines together, or by multiple switches that connect the P and N lines to a fixed voltage (such as ground or VCM). As an example, switch 41 between VOP and VON can also have an additional switch connecting to VCM.

[0089] Instead of generating VCM from AVDD, the common-mode voltage generator 540 can generate VCM from VDD, or from VOP or VON. Various simplifications are possible, such as removing the common-mode voltage generator 540 and instead having the SCCMFB P circuit 520 or SCCMFBN circuit 530 generate VCM from VOP or VON. When feedback is not required, the SCCMFB P circuit 520 and SCCMFB N circuit 530 can be removed. VIBASP can be applied as VFB_P to the AC-coupled input network 510, and VIBASN or another bias can be applied as VFB_N to the AC-coupled input network 510. The ping circuit 400 and pong circuit 402 are not simultaneously present; redundancy can be eliminated by having only the ping circuit 400 and a capacitor for filtering.

[0090] While VBIASP may be higher than the common-mode voltage VCM, and VBIASN may be lower than VCM, this is not necessary. As an example, some advanced processes with very low supply voltages may have a VBIASN higher than VCM.

[0091] Multiple variations of the ADC stage are possible. The analog inputs AINP and AINN to the first capacitor array 32 can be connected to... Figure 1 The outputs of switches 62 and 63 can be connected to ANP and ANN respectively. Figure 1 The circuit implementation of the second capacitor array 34 is another example of AINP and AINN. Figure 1The inputs to comparator 12 can be the combined nodes VXP and VXN of the first capacitor array 32 and the combined nodes VYP and VYN of the second capacitor array 34. This is sometimes referred to as substrate sampling.

[0092] Another alternative is top-plate sampling, where the analog inputs AINP and AINN to the first capacitor array 32 can be connected to the combination nodes VXP and VXN to the comparator 12. Figure 1 ). Figure 1 The circuit is modified to switch ANINP or VINP to VXP at the upper input of comparator 12, and switch ANIN or VINN to VXN at the lower input of comparator 12. Top-plate sampling can reduce signal loss, but may require additional calibration. Other variations are also possible.

[0093] Although a switched-capacitor SAR ADC stage is shown, a flash-ADC stage can replace a pipelined flash ADC. A hybrid ADC can have a flash ADC for one stage and a SAR-ADC for another. While a first capacitor array 32 with 5-bit resolution and a second capacitor array 34 with 8-bit resolution are described, other resolutions such as 3-bit / 5-bit, 7-bit / 10-bit, etc., can also be used. Various redundancies and calibrations are possible.

[0094] Although two stages with SAR1 108, first capacitor array 32 and SAR2 118, second capacitor array 34 are shown, more stages can be added by, for example, having the second capacitor array 34 output its residual voltage to another residual amplifier 30, and then the other residual amplifier 30 driving the third capacitor array after third SAR conversion.

[0095] Terms such as top, bottom, up, down, up, and down are relative and not limiting. Inversion can be added by swapping the + and - inputs or outputs or by adding inverters. Although a simple two-phase clock timing scheme with phases P1 and P2 is described, more complex clock timing can be used, and three, four, or more phases can be employed. For some switches, the clock signal may be delayed. Timing bias can be added. Additional equalization or bias switches such as VIN and VIP can be added. Although analog voltage is described, analog current can also be converted, and the residual can be residual current.

[0096] Although n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and p-channel transistors are described, other types of transistors can be substituted, such as bipolar NPN, PNP, FinFET, or junction FET.

[0097] The current source can be approximated or implemented as a transistor with its gate and drain connected together, or a depletion-type transistor or a native transistor. A self-biased or bandgap reference voltage can be used.

[0098] Additional components, such as resistors, capacitors, inductors, and transistors, can be added at various nodes, and parasitic components may also exist. Enabling and disabling the circuit can be achieved using additional transistors or other methods. Pass-gate transistors or transmission gates can be added for isolation. Inverting or additional buffers can be added. Capacitors can be connected in parallel to form a larger capacitance that has the same margin or perimeter effect across several capacitor sizes. Switches can be n-channel transistors, p-channel transistors, or transmission gates with parallel n-channel and p-channel transistors, or more complex circuits (whether passive or active, amplifying or non-amplifying). Switches can use a boosted gate voltage for lower ON resistances, where a high gate voltage is boosted to greater than VDD.

[0099] The background section of this invention may include background information about the problems or circumstances surrounding the invention, rather than describing prior art. Therefore, the inclusion of material in the background section does not imply that the applicant acknowledges prior art.

[0100] Any methods or processes described herein are implemented by machines or computers and are intended to be performed by machines, computers, or other devices, not by humans alone without the assistance of such machines. Tangible results may include reports or machine-generated displays on display devices such as computer monitors, projection devices, audio generating devices, and related media devices, and may include hard-copy printouts also generated by machines. Computer control of other machines is another tangible result.

[0101] Any advantages and benefits described may not apply to all embodiments of the invention. When the word "component" is recited in a claim element, the applicant intends that the claim element to be incorporated into paragraph 6 of 35 USC Sect. Typically, one or more words precede the word "component." These one or more words preceding the word "component" are intended to facilitate reference to the claim element rather than to convey structural limitations. Such component-plus-function claims are intended to cover not only the structure described herein for performing the function and its structural equivalents, but also equivalent structures. For example, although nails and screws have different structures, they are equivalent structures because they both perform the function of fastening. Claims that do not use the word "component" are not intended to be incorporated into paragraph 6 of 35 USC Sect. Signals are typically electronic signals, but can also be optical signals, such as those carried via fiber optic lines.

[0102] The above description of embodiments of the invention has been presented for illustrative and descriptive purposes. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. It is intended that the scope of the invention be limited not by this detailed description, but by the appended claims.

Claims

1. A residual amplifier, comprising: Differential input with true input and supplementary input; An input shifter receives the differential input to generate an upper differential input and a lower differential input, the input shifter shifting the differential input upward in terms of voltage to generate the upper differential input, and the input shifter shifting the differential input downward in terms of voltage to generate the lower differential input; A true p-channel differential transistor whose gate receives the true input of the upper differential input, whose source is connected to a power supply, and whose drain is connected to the true upper node. A supplementary p-channel differential transistor is provided, wherein its gate receives the supplementary input of the upper differential input, its source is connected to the power supply, and its drain is connected to the supplementary upper node. A true p-channel cascode transistor, the source of which is connected to the true upper node and the drain of which is connected to the supplementary output node; A supplementary p-channel cascode transistor is provided, with its source connected to the supplementary upper node and its drain connected to the true output node. A true n-channel differential transistor whose gate receives the true input of the lower differential input, whose source is connected to ground, and whose drain is connected to the true lower node; A supplementary n-channel differential transistor is provided, wherein its gate receives the supplementary input of the lower differential input, its source is connected to the ground, and its drain is connected to the supplementary lower node. A true n-channel cascode transistor, the source of which is connected to the true lower node and the drain of which is connected to the supplementary output node; and A supplementary n-channel cascode transistor is provided, with its source connected to the supplementary lower node and its drain connected to the true output node. Switched-capacitor common-mode feedback (SCCMFB) circuit; The true output node and the supplementary output node form a differential output; The input shifter includes an AC-coupled input network, the AC-coupled input network comprising: A true upper capacitor connected between the true input of the differential input and the true input of the upper differential input; A true upper switch, which closes during the zero-adjustment phase of the residual amplifier, to connect the upper shift voltage to the true upper capacitor; A supplementary capacitor is connected between the supplementary input of the differential input and the supplementary input of the upper differential input; An additional switch is provided, which is closed during the zero-adjustment phase of the residual amplifier to connect the upper shift voltage to the additional capacitor. A true lower capacitor connected between the true input of the differential input and the true input of the lower differential input; A true down switch, which closes during the zero-adjustment phase of the residual amplifier, to connect the down-shift voltage to the true down capacitor; A supplementary lower capacitor connected between the supplementary input of the differential input and the supplementary input of the lower differential input; A supplementary lower switch is provided, which is closed during the zero-adjustment phase of the residual amplifier to connect the lower shift voltage to the supplementary lower capacitor. The upper shift voltage is higher than the lower shift voltage in terms of voltage. The upper-switch capacitor common-mode feedback circuit includes: The first true capacitor is connected between the true output node and the upper shift voltage; The first true segment capacitor; A plurality of upper first true switches, wherein the plurality of said upper first true switches connect said upper first true segmented capacitor to said upper first true capacitor during the second phase, and load said upper first true segmented capacitor with upper bias voltage during the first phase; A first supplementary capacitor is connected between the supplementary output node and the upper shift voltage; The first supplementary segment capacitor; and A plurality of upper first supplementary switches connect the upper first supplementary segment capacitor to the upper first supplementary capacitor during the second phase and load the upper first supplementary segment capacitor using the upper bias voltage during the first phase.

2. The residual amplifier as described in claim 1, wherein, The gate of the true p-channel cascode transistor and the gate of the supplementary p-channel cascode transistor receive an on-bias voltage; The gate of the true n-channel cascode transistor and the gate of the supplementary n-channel cascode transistor receive the down-bias voltage. The upper bias voltage is higher than the lower bias voltage in terms of voltage.

3. The residual amplifier of claim 1, further comprising: An upper differential amplifier having a first input connected to the true upper node and a second input connected to the supplementary upper node, the upper differential amplifier generating a first output driving the gate of the supplementary p-channel cascode transistor and generating a second output driving the gate of the true p-channel cascode transistor; A lower differential amplifier having a first input connected to the true lower node and a second input connected to the supplementary lower node, the lower differential amplifier generating a first output driving the gate of the supplementary n-channel cascode transistor and generating a second output driving the gate of the true n-channel cascode transistor; This provides an increase in gain.

4. The residual amplifier of claim 1, further comprising: An input equalization switch is closed during the zero-adjustment phase of the residual amplifier to connect the true input of the differential input to the supplementary input of the differential input.

5. The residual amplifier as described in claim 3, wherein, The upper SCCMFB circuit further includes: The upper second true capacitor is connected between the true output node and the upper shift voltage; The second true segmented capacitor; A plurality of upper second true switches, wherein the plurality of said upper second true switches connect said upper second true segmented capacitor to said upper second true capacitor during the first phase, and load said upper second true segmented capacitor using said upper bias voltage during the second phase; A second supplementary capacitor is connected between the supplementary output node and the upper shift voltage; The second supplementary segment capacitor; A plurality of upper second supplementary switches connect the upper second supplementary segmented capacitor to the upper second supplementary capacitor during the first phase and load the upper second supplementary segmented capacitor using the upper bias voltage during the second phase.

6. The residual amplifier as described in claim 5, wherein, The first true switch further includes: A first load switch, wherein the first load switch connects the first terminal of the first true segmented capacitor and the common-mode voltage during the first phase; A second load switch, which connects the second terminal of the upper first true segmented capacitor and the upper bias voltage during the first phase; A third load switch, which connects the first terminal of the upper first true segment capacitor and the first terminal of the upper first true segment capacitor connected to the true output node during the second phase; A fourth load switch, which connects the second terminal of the upper first true segmented capacitor and the second terminal of the upper first true segmented capacitor connected to the upper shift voltage during the second phase.

7. The residual amplifier of claim 5, further comprising: The lower SCCMFB circuit is a replica of the upper SCCMFB circuit, wherein the lower shift voltage replaces the upper shift voltage, and the lower bias voltage replaces the upper bias voltage. Wherein, the lower bias voltage is less than the upper bias voltage.

8. The residual amplifier of claim 1, further comprising: A first ADC stage is configured to convert an analog input into a first M digital bits representing an analog value of the analog input, wherein M is an integer of at least 3, and the first ADC stage outputs a residual after quantizing the analog input into the first M digital bits. A differential residual amplifier is used to receive the residual from the first ADC stage as the differential input and generate the differential output; A pair of feedback capacitors connected between the differential input and the differential output of the residual amplifier; and A second ADC stage is used to convert the differential output from the residual amplifier into a second N digital bits representing an analog value of the differential output from the residual amplifier, where N is an integer of at least 5.

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