Clock and data recovery circuit

Abstract

A clock and data recovery circuit includes a voltage-controlled oscillator (VCO), a frequency detector, and a control circuit. The VCO generates a clock signal based on a voltage signal. The frequency detector detects whether the frequency of the clock signal needs to be increased based on multiple sampling results of the input data signal and generates a first rising control signal accordingly. The control circuit is coupled to the VCO and the frequency detector and adjusts the voltage signal based on the first rising control signal. After detecting that the frequency of the clock signal is locked, the clock and data recovery circuit operates in a data recovery mode, and the frequency detector detects whether the frequency of the clock signal needs to be increased in the data recovery mode.

Description

Technical Field

[0001] This invention relates to a clock and data recovery (CDR) circuit, and more particularly to a CDR circuit with frequency control capability in data recovery mode. Background Technology

[0002] To transmit data from one device to another, the receiving device must know when to sample the data signal it receives from the transmitting device. Typically, a phase-locked loop (PLL) is used to generate the necessary frequency waveform. The receiving device requires clock alignment and regeneration circuitry, such as a PLL and / or a delay-locked loop (DLL), to regenerate the correct clock frequency from a reference clock signal and synchronize the clock with the input data. Clock and data recovery (CDR) circuits with PLL circuitry are commonly used to output data and synchronize the clock using a reference clock signal.

[0003] However, the frequency accuracy of the reference clock signal provided to the PLL circuit and / or CDR circuit is a critical factor affecting the correctness of data recovery. If the reference clock frequency drifts, unwanted sampling errors will occur, and data cannot be recovered correctly. The frequency drift problem is more severe when the reference clock signal is provided by an oscillator circuit rather than a crystal oscillator.

[0004] Therefore, there is an urgent need for an innovative CDR circuit that has frequency control capabilities (including frequency drift detection and adjustment) in data recovery mode to compensate for reference clock frequency drift. Summary of the Invention

[0005] The purpose of this invention is to provide an innovative CDR circuit with frequency control capability in data recovery mode to compensate for the frequency drift of the reference clock.

[0006] An embodiment of the present invention discloses a clock and data recovery circuit for recovering clock and data information from an input data signal. The clock and data recovery circuit includes a voltage-controlled oscillator (VCO), a frequency detector, and a control circuit. The VCO generates a clock signal based on a voltage signal. The frequency detector detects whether the frequency of the clock signal needs to be increased based on multiple sampling results of the input data signal and generates a first rising control signal accordingly. The control circuit is coupled to the VCO and the frequency detector and adjusts the voltage signal based on the first rising control signal. After detecting that the frequency of the clock signal is locked, the clock and data recovery circuit operates in a data recovery mode, and the frequency detector detects whether the frequency of the clock signal needs to be increased in the data recovery mode.

[0007] Another embodiment of the present invention discloses a clock and data recovery circuit for recovering clock and data information from an input data signal. The clock and data recovery circuit includes a voltage-controlled oscillator (VCO), a frequency detector, a phase detector, a charge pump circuit, and a control circuit. The VCO generates a clock signal based on a voltage signal. The frequency detector detects whether the frequency of the clock signal needs to be increased based on multiple sampling results of the input data signal and generates a first rising control signal accordingly. The phase detector receives the input data signal and the clock signal, detects whether the clock signal is phase-leading or phase-lagging based on the sampling results of the input data signal, and generates a second rising control signal and a first falling control signal. The charge pump circuit is coupled to the VCO and the phase detector and adjusts the voltage signal based on the second rising control signal and the first falling control signal. The control circuit is coupled to the VCO and the frequency detector and adjusts the voltage signal based on the first rising control signal. After detecting that the frequency of the clock signal is locked, the clock and data recovery circuit operates in data recovery mode, and the frequency detector and the phase detector also operate in data recovery mode.

[0008] Another embodiment of the present invention discloses a clock and data recovery circuit for recovering clock and data information from an input data signal. The clock and data recovery circuit includes a clock recovery module and a data recovery module. The clock recovery module is used to lock the frequency of the clock signal in a clock recovery mode, and the data recovery module is used to operate in a data recovery mode and recover data information based on the input data signal. After detecting that the frequency of the clock signal is locked, the clock and data recovery circuit switches from the clock recovery mode to the data recovery mode. The data recovery module includes a voltage-controlled oscillator (VCO), a charge pump circuit, a frequency detector, and a control circuit. The VCO generates the clock signal based on a voltage signal. The charge pump circuit is coupled to the VCO and adjusts the voltage signal based on a rising control signal and a falling control signal. The frequency detector detects whether the frequency of the clock signal needs to be increased based on multiple sampling results of the input data signal and generates a supplementary rising control signal accordingly. The control circuit is coupled to the VCO and the frequency detector and further adjusts the voltage signal based on the supplementary rising control signal. Attached Figure Description

[0009] Figure 1 This is an exemplary block diagram of a clock and data recovery (CDR) circuit according to an embodiment of the present invention.

[0010] Figure 2 This is a schematic diagram illustrating the sampling of an input data signal based on clock signals with different clock phases according to an embodiment of the present invention.

[0011] Figure 3 This is a flowchart illustrating a method for recovering clock and data information from an input data signal using a clock and data recovery circuit with frequency control capability in data recovery mode, according to an embodiment of the present invention.

[0012] Figure 4 This is a schematic diagram illustrating the change process of the frequency CLK_F of the clock signal CLK_Sig in data recovery mode according to an embodiment of the present invention.

[0013] The labels in the diagram are explained as follows:

[0014] 100: Clock and Data Recovery Circuit (CDR)

[0015] 110: Phase-Frequency Detector (PFD)

[0016] 120: Charge pump circuit

[0017] 130: Voltage-controlled oscillator (VCO)

[0018] 140: Frequency divider

[0019] 150: Low-pass filter (LPF)

[0020] 160: Multiplexer

[0021] 170: Phase Detector (PD)

[0022] 180: Frequency Detector (FD)

[0023] 190: Control Circuit

[0024] 200: Lock detector

[0025] S302, S304, S306, S308: Steps Detailed Implementation

[0026] Figure 1 This is an exemplary block diagram of a clock and data recovery (CDR) circuit according to an embodiment of the present invention. The CDR circuit 100 can switch between a clock recovery mode and a data recovery mode, and is used to recover clock and data information from an input data signal. The CDR circuit 100 can initially operate in clock recovery mode to lock the frequency of the clock signal CLK_Sig according to a reference signal Ref_CLK, and after a lock indication signal PLL_LOCK indicates that the frequency of the clock signal CLK_Sig is locked, it switches to data recovery mode to recover data information.

[0027] The CDR circuit 100 may include a clock recovery module and a data recovery module. The clock recovery module includes multiple circuits operating in clock recovery mode to lock the frequency of the clock signal CLK_Sig. The data recovery module also includes multiple circuits operating in data recovery mode to recover data information based on the input data signal. It is worth noting that the clock recovery module and the data recovery module may share one or more circuits included in the CDR circuit 100. For example, the charge pump circuit 120, voltage controlled oscillator (VCO) 130, low-pass filter (LPF) 150, and / or multiplexer 160 of the CDR circuit 100 may be shared by the clock recovery module and the data recovery module. Therefore, the charge pump circuit 120, VCO 130, LPF 150, and multiplexer 160 may be part of either the clock recovery module or the data recovery module.

[0028] In embodiments of the present invention, the clock recovery module may include a phase frequency detector (PFD) 110, a charge pump circuit 120, a VCO 130, a frequency divider 140, an LPF 150, and a multiplexer 160, and the data recovery module may include a phase detector (PD) 170, a frequency detector (FD) 180, a control circuit 190, a multiplexer 160, a charge pump circuit 120, an LPF 150, and a VCO 130.

[0029] At the start of the clock and data recovery process, the clock recovery module can activate the clock recovery loop to lock the frequency of the clock signal CLK_Sig generated by VCO 130 based on the reference signal Ref_CLK. PFD 110 receives the reference signal Ref_CLK and the feedback signal FB generated by the frequency divider 140, detects the phase difference (or frequency difference) between the reference signal Ref_CLK and the feedback signal FB, and generates a rising control signal PFD_UP and a falling control signal PFD_DN accordingly. The rising control signal PFD_UP and the falling control signal PFD_DN can be pulse signals with adjustable pulse widths. When it is detected that the phase of the reference signal Ref_CLK leads the phase of the feedback signal FB (or when it is detected that the frequency of the reference signal Ref_CLK is higher than the frequency of the feedback signal FB), PFD 110 can generate an "up" pulse in the rising control signal PFD_UP. When the phase of the reference signal Ref_CLK is detected to be lagging behind the phase of the feedback signal FB (or when the frequency of the reference signal Ref_CLK is detected to be lower than the frequency of the feedback signal FB), the PFD 110 can generate a "down" pulse in the down control signal PFD_DN.

[0030] Multiplexer 160 is coupled to PFD 110, PD 170, and charge pump circuit 120, and is used to select the rising and falling control signals generated by PFD 110 or PD 170 as multiplexing signals UP_mux and DN_mux in response to the lock indication signal PLL_LOCK, and outputs the multiplexing signals UP_mux and DN_mux to charge pump circuit 120. The lock indication signal PLL_LOCK is generated by lock detector 200. Lock detector 200 detects whether the frequency of clock signal CLK_Sig is locked based on reference signal Ref_CLK and feedback signal FB, and generates the lock indication signal PLL_LOCK accordingly. For example, the value of lock indication signal PLL_LOCK can be initially set to 0 to indicate that the frequency of clock signal CLK_Sig is not yet locked. When PLL_LOCK = 0, CDR circuit 100 is operated in clock recovery mode, and the clock recovery loop is performed by the clock recovery module as described above. In response to the condition that PLL_LOCK = 0, which is not yet locked, the multiplexer 160 outputs the rising control signal PFD_UP and the falling control signal PFD_DN generated by PFD110 as multiplexing signals UP_mux and DN_mux.

[0031] A charge pump circuit 120 is coupled to a voltage-controlled oscillator 130 and is used to adjust the voltage signal of the voltage-controlled oscillator 130 according to multiplexing signals UP_mux and DN_mux. For example, the charge pump circuit 120 may include one or more current sources in the charging path and the discharging path, respectively. When the multiplexing signal UP_mux has an "up" pulse (e.g., when the value of the multiplexing signal UP_mux is "1"), the charging current IUP is conducted to the charging path to adjust the voltage signal provided at the input of the VCO 130 (e.g., increase its voltage). On the other hand, when the multiplexing signal DN_mux has a "down" pulse (e.g., when the value of the multiplexing signal DN_mux is "1"), the discharging current IDN is conducted to the discharging path to adjust the voltage signal provided at the input of the VCO 130 (e.g., decrease its voltage).

[0032] VCO 130 generates a clock signal CLK_Sig with multiple clock phases (e.g., 0°, 90°, 180°, and 270°) based on the voltage signal supplied to its input. The clock signal CLK_Sig (with any phase) is then provided to frequency divider 140. Frequency divider 140 is coupled between voltage-controlled oscillator 130 and PFD 110 and generates a feedback signal FB based on the clock signal CLK_Sig and a frequency scale factor. The clock recovery module can be implemented as a phase-locked loop (PLL) circuit, and LPF 150 is configured to provide filtering to increase the stability of the PLL circuit.

[0033] According to an embodiment of the present invention, the reference signal Ref_CLK can be generated by an oscillator circuit ( Figure 1 The frequency of the reference clock Ref_CLK (not shown) is generated by the oscillator circuit. To compensate for unwanted frequency drift in the reference clock Ref_CLK generated by the oscillator circuit, the CDR circuit 100 is designed to have frequency control capabilities (including frequency drift detection and adjustment) in data recovery mode. By introducing an additional charging path at the input of VCO 130, the frequency of the clock signal CLK_Sig generated by VCO 130 can be further adjusted in data recovery mode. In this way, the frequency drift of the reference clock Ref_CLK can be compensated by adjusting the frequency of the clock signal CLK_Sig, thus solving the problem of incorrect data recovery caused by the frequency drift of the reference clock Ref_CLK.

[0034] As described above, the lock detector 200 detects whether the frequency of the clock signal CLK_Sig is locked and generates a lock indication signal PLL_LOCK accordingly. When the lock detector 200 detects that the frequency of the clock signal CLK_Sig is locked to the frequency of the reference clock Ref_CLK, the lock detector 200 sets the value of the lock indication signal PLL_LOCK to 1. When PLL_LOCK = 1, the CDR circuit 100 is operated in data recovery mode, and the data recovery module conducts the data recovery loop. In response to the lock condition PLL_LOCK = 1, the multiplexer 160 outputs the up control signal PD_UP and the down control signal PD_DN generated by PD 170 as multiplexing signals UP_mux and DN_mux.

[0035] Please note that when the frequency of the clock signal CLK_Sig is locked, the frequency of the clock signal CLK_Sig (denoted as CLK_F) is essentially equal to the frequency of the reference clock Ref_CLK (denoted as Ref_F) multiplied by the frequency scaling factor of the divider 140 (denoted as SF), i.e., CLK_F = Ref_F * SF. In an embodiment of the present invention, it is assumed that the purpose of the CDR circuit 100 is to eventually lock the frequency of the clock signal CLK_Sig to the target clock frequency (denoted as Target_F) to correctly recover data information from the input data signal. The target clock frequency is related to the data rate of the input data signal, or it can be the frequency required for the VCO to receive the input data. The frequency scaling factor SF of the divider 140 can be well designed so that when the CDR circuit 100 leaves the clock recovery mode, the frequency CLK_F of the clock signal CLK_Sig is close to but lower than the target clock frequency Target_F. For example, when the lock detector 200 detects that the frequency CLK_F of the clock signal CLK_Sig is locked, the frequency CLK_F of the clock signal CLK_Sig can be lower than the target clock frequency Target_F.

[0036] For example, assuming the input data signal has a data rate of 10 GHz and the VCO 130 of the CDR circuit 100 is designed as a half-rate VCO, the target clock frequency Target_F can be 5 GHz. In one embodiment of the present invention, if the relationship between the target clock frequency Target_F and the frequency Ref_F of the reference clock Ref_CLK is expressed as: Target_F = Ref_F * SF_A, where SF_A can represent the actual required frequency scaling factor, and the frequency scaling factor SF of the frequency divider 140 can be set to a value lower than the actual required frequency scaling factor SF_A. In one embodiment of the present invention, SF = 0.9 * SF_A. Therefore, in this embodiment, the locking condition of the clock recovery module (or PLL circuit) can be CLK_F = Ref_F * SF = 0.9 * Target_F.

[0037] Therefore, in the embodiments of the present invention, the CDR circuit 100 is used to lock the frequency of the clock signal CLK_Sig to a frequency close to but lower than the target clock frequency in the clock recovery mode, and then further lock the frequency of the clock signal CLK_Sig to the target clock frequency (i.e., restore the clock information) at the start of the data recovery mode, and also restore the data information in the data recovery mode.

[0038] As described above, the CDR circuit 100 switches from clock recovery mode to data recovery mode after detecting that the frequency of the clock signal CLK_Sig is locked. In data recovery mode, the PD 170 is used to receive input data signals (such as...) Figure 1 The differential input data signals DATA+ and DATA- shown receive the clock signal CLK_Sig from VCO130. Based on the sampling result of the input data signal, the phase of the clock signal CLK_Sig is detected as leading or lagging, and the rising control signal PD_UP and falling control signal PD_DN are generated accordingly.

[0039] Specifically, in an embodiment of the present invention, PD 170 can receive a clock signal CLK_Sig with different clock phases from VCO 130 to sample the input data signal. Figure 2 This is a schematic diagram illustrating the sampling of an input data signal based on clock signals with different clock phases according to an embodiment of the present invention. The data signal DATA represents the input data signal, which can be either DATA+ or DATA-. The clock signal CKI represents a clock signal with the same phase (e.g., a clock signal CLK_Sig with a 0-degree clock phase), and the clock signal CKQ represents a clock signal with a quadrature phase (e.g., a clock signal CLK_Sig with a 90-degree clock phase). Typically, the clock signal CKI is used to sample the data portion of the data signal DATA, while the clock signal CKQ is used to sample the edges of the corresponding data. PD 170 can detect whether the phase of the clock signal CLK_Sig is ahead or behind the phase of the target clock signal (e.g., a clock signal with a target clock frequency) that can be used to correctly recover the data information based on the data sampling results and the edge sampling results.

[0040] Figure 2 The notation Ax in the figure represents the x-th data sample result in the current clock cycle (e.g., Clock_Cycle[n] shown in the figure). Figure 2The notation Tx in the diagram represents the x-th edge sample result of the current clock cycle, and the notation Ax' represents the x-th data sample result of the next clock cycle, and so on. Since the phase difference between clock signals CKI and CKQ is 90 degrees, clock signal CKQ is a 90-degree lagging version of clock signal CKI within the same clock cycle. The PD 170 can detect whether the clock signal CLK_Sig is leading or lagging by detecting the occurrence of a transition between two consecutive samples (i.e., from logic "0" to logic "1" or from logic "1" to logic "0"). For example, the PD 170 can perform some logical operations on at least two samples (such as samples Ax and Tx, A(x+1) and T(x+1), A(x+1) and Tx, and / or any combination thereof) to detect the occurrence of a transition between two consecutive samples.

[0041] In one embodiment of the present invention, PD 170 can perform logical operations (such as a mutual exclusion OR (XOR) operation) on the x-th data and edge sampling results (e.g., the x-th data sampling result and its subsequent edge sampling results) obtained in the same clock cycle to obtain a calculation result, collect one or more of the above calculation results (e.g., the calculation results corresponding to the x-th and (x+1)-th sampling results), and generate a rising control signal PD_UP based on the collected calculation results (e.g., PD 170 can perform an OR operation on the corresponding calculation results collected in the current clock cycle to generate a rising control signal PD_UP). Furthermore, PD 170 can obtain a calculation result on data sampling results and edge sampling results (e.g., the x-th edge sampling result and its subsequent data sampling results, where the edge sampling result and its subsequent data sampling results may be in the same or different clock cycles) obtained in the same clock cycle or different clock cycles (e.g., adjacent clock cycles), collect one or more of the above calculation results, and generate a falling control signal PD_DN based on the collected calculation results.

[0042] Taking data sampling results A1, A2, A1' and edge sampling results T1 and T2 as examples, PD 170 can perform a mutual exclusive OR (XOR) operation on sampling results A1 and T1 to obtain a first calculation result, perform a mutual exclusive OR (XOR) operation on sampling results A2 and T2 to obtain a second calculation result, and perform an OR (OR) operation on the first and second calculation results to generate a rising control signal PD_UP. Additionally, PD 170 can perform a mutual exclusive OR (XOR) operation on sampling results T1 and A2 to obtain a third calculation result, perform a mutual exclusive OR (XOR) operation on sampling results T2 and A1' to obtain a fourth calculation result, and perform an OR (OR) operation on the third and fourth calculation results to generate a falling control signal PD_DN. The rising control signal PD_UP and the falling control signal PD_DN can be pulse signals with adjustable pulse widths. When the phase of the clock signal CLK_Sig is detected to lag behind the phase of the target clock signal, an "up" pulse can be generated in the rising control signal PD_UP (e.g., through the logic operation described above). When the phase of the clock signal CLK_Sig is detected to lead the phase of the target clock signal, a "down" pulse can be generated in the falling control signal PD_DN (e.g., through the logic operation described above).

[0043] In embodiments of the present invention, the data sampling results and edge sampling results (such as...) are further... Figure 2 The data sampling results A1, A2, A1' and edge sampling results T1 and T2 shown are provided to the frequency detector (FD) 180. FD 180 is used to detect whether the frequency of the clock signal CLK_Sig needs to be increased based on the sampling results of the input data signal obtained from PD 170, and accordingly generates a supplementary up control signal FD_UP. For example, when FD 180 detects that the phase of the clock signal CLK_Sig lags behind the phase of the target clock signal based on the sampling results of the input data signal, FD 180 generates a supplementary up control signal FD_UP with an "up" pulse, thereby controlling the control circuit 190 to provide an additional charging current IFD_UP at the input of VCO 130 to increase the frequency CLK_F of the clock signal CLK_Sig. It should be noted that in some embodiments of the present invention, a deserializer can be added before FD 180 to deserialize the data sampling results and edge sampling results.

[0044] Assuming that FD 180 obtains multiple data sampling results D[0]~D[N] and multiple edge sampling results E[0]~E[N] within one clock cycle, FD 180 can perform some logical operations on at least two consecutive data sampling results (e.g. D[y] and D[y+1]) and related edge sampling results (e.g. E[y]) to obtain calculation results related to the y-th sampling result, collect one or more calculation results related to the same clock cycle, and generate a supplementary uplink control signal FD_UP based on the collected calculation results.

[0045] For example, FD 180 can perform a mutually exclusive OR (XOR) operation on sampling results D[y] and E[y] to obtain a first calculation result, perform a mutually exclusive OR (XOR) operation on sampling results E[y] and D[y+1] to obtain a second calculation result, and perform an AND operation on the first and second calculation results to obtain the calculation result FD_UP[y] related to the y-th sampling result. As another example, FD 180 can perform a mutually exclusive OR (XOR) operation on sampling results D[y+1] and E[y+1] to obtain a third calculation result, perform a mutually exclusive OR (XOR) operation on sampling results E[y+1] and D[y+2] to obtain a fourth calculation result, and perform an AND operation on the third and fourth calculation results to obtain the calculation result FD_UP[y+1] related to the (y+1)-th sampling result. FD 180 can further collect one or more calculation results related to the same clock cycle, such as FD_UP[0] to FD_UP[N], and perform an OR operation on the calculation results related to the same clock cycle to generate a supplementary rise control signal FD_UP. For example, in one embodiment of the present invention, FD_UP = FD_UP[0] + FD_UP[1] + ... + FD_UP[N], where the operator "+" represents a logical OR operation. In this embodiment of the present invention, the supplementary rise control signal FD_UP can be a pulse signal with adjustable pulse width. When it is detected that the frequency of the clock signal CLK_Sig needs to be increased, an "up" pulse can be generated in the supplementary rise control signal FD_UP through the above OR operation.

[0046] Please refer back to this. Figure 1In an embodiment of the invention, control circuit 190 is coupled to voltage-controlled oscillator 130 and FD 180, and may include at least one current source IFD_UP. Control circuit 190 provides an additional charging path to further adjust the voltage signal supplied at the input of voltage-controlled oscillator 130 according to a supplementary rising control signal FD_UP. For example, when the supplementary rising control signal FD_UP has an "up" pulse (e.g., when the value of the supplementary rising control signal FD_UP is "1"), charging current IFD_UP is turned on in response to the supplementary rising control signal FD_UP to provide an additional charging path to adjust the voltage signal supplied at the input of voltage-controlled oscillator 130 (e.g., increase its voltage). In one embodiment of the invention, with the help of the charging current IFD_UP conducted in the additional charging path by control circuit 190 in response to the supplementary rising control signal FD_UP provided by FD 180, the frequency CLK_F of clock signal CLK_Sig can be further adjusted from clock frequency Target_F*0.9 and increased to near the target clock frequency Target_F. For example, in data recovery mode, the frequency CLK_F of the clock signal CLK_Sig can be gradually increased from 0.9*Target_F in response to the supplementary rise control signal FD_UP provided by FD 180.

[0047] It should be noted that in embodiments of the present invention, FD 180 can be enabled at the start of the data recovery mode and disabled after a predetermined period of time. Therefore, in embodiments of the present invention, at the start of the data recovery mode, the voltage signal provided at the input of VCO 130 and FD 180 can be controlled (or adjusted) simultaneously in response to the control signal output by PD 170 (e.g., rising control signal PD_UP or falling control signal PD_DN) and the control signal output by FD 180 (e.g., supplementary rising control signal FD_UP). After the predetermined period of time, FD 180 can be disabled, and the voltage signal provided at the input of VCO 130 can be controlled (or adjusted) only in response to the control signal output by PD 170. In embodiments of the present invention, the predetermined period of time can be set to a sufficiently long value so that the clock signal CLK_Sig is locked to the target clock frequency; the locking condition can be, for example, CLK_F = Target_F. Continuing with the previous example, where SF = 0.9 * SF_A, the locking condition of the clock recovery module is set as CLK_F = Ref_F * SF = 0.9 * Target_F. When entering the data recovery mode, and from the beginning of the data recovery mode, the frequency CLK_F of the clock signal CLK_Sig can be further adjusted, increasing from 0.9 * Target_F to the target clock frequency Target_F within the predetermined time period.

[0048] Figure 4 This is a schematic diagram illustrating the frequency change process of the clock signal CLK_Sig, CLK_F, according to an embodiment of the present invention. Figure 4 As shown, in data recovery mode, the frequency CLK_F of the clock signal CLK_Sig is increased from 0.9*Target_F to a value close to the target clock frequency Target_F (e.g., the frequency required for the VCO to receive input data). In one embodiment of the invention, in data recovery mode, the frequency CLK_F of the clock signal CLK_Sig is increased to approach but not exceed the target clock frequency Target_F.

[0049] In this way, the frequency drift of the reference clock Ref_CLK can be compensated by further adjusting the frequency of the clock signal CLK_Sig in the data recovery mode, and the problem of incorrect data recovery caused by the frequency drift of the reference clock Ref_CLK can be solved.

[0050] Please refer to Figure 2 The exemplary waveform shown in this example indicates that the frequency CLK_F of the clock signal CLK_Sig is slower than the target clock frequency Target_F. Therefore, at the start of data recovery mode, the frequency CLK_F of the clock signal CLK_Sig will be further increased under the control of the FD180.

[0051] Figure 3 This is a flowchart illustrating a method for recovering clock and data information from an input data signal using a clock and data recovery circuit with frequency control capability in data recovery mode, according to an embodiment of the present invention. The method may include the following steps:

[0052] Step S302: In clock recovery mode, the frequency of the clock signal is locked by the clock recovery module of the CDR circuit. In one embodiment of the present invention, the condition for leaving clock recovery mode can be set to when the frequency of the clock signal is locked at a value close to but lower than the target clock frequency Target_F, wherein the target clock frequency Target_F can be used to accurately sample the input data signal and correctly recover the data information.

[0053] Step S304: When it is detected that the conditions for leaving the clock recovery mode have been met, leave the clock recovery mode and enter the data recovery mode.

[0054] Step S306: Operate in a data recovery mode with frequency control to further adjust (e.g., increase) the frequency of the clock signal and (optionally) recover data information via the data recovery module of the CDR circuit. In one embodiment of the invention, the condition for stopping the adjustment of the clock signal frequency in the data recovery mode can be set to when it is determined that it is no longer necessary to increase the frequency of the clock signal, or it can be set to when a predetermined period expires.

[0055] Step S308: When it is detected that the condition for stopping the adjustment of the clock signal frequency has been met, the data recovery mode is operated to recover the data information without frequency control.

[0056] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention.

Claims

1. A clock and data recovery circuit for recovering clock and data information from an input data signal, the clock and data recovery circuit comprising: A voltage-controlled oscillator is used to generate a clock signal based on a voltage signal; A frequency detector is used to detect whether the frequency of the clock signal needs to be increased based on multiple samples of the input data signal, and accordingly generate a first rising control signal; and A control circuit, coupled to the voltage-controlled oscillator and the frequency detector, is used to adjust the voltage signal according to the first rising control signal. The frequency of the clock signal is equal to the product of the frequency of the reference signal and the frequency scaling factor of the divider. The frequency of the clock signal is locked and is lower than the target clock frequency. After detecting that the frequency of the clock signal is locked, the clock and data recovery circuit operates in data recovery mode, and the frequency detector is used to detect whether it is necessary to increase the frequency of the clock signal in the data recovery mode to further lock to the target clock frequency.

2. The clock and data recovery circuit as described in claim 1, further comprising: A phase detector is used to receive the input data signal and the clock signal, and to detect whether the clock signal is phase-leading or phase-lagging based on the multiple sampling results of the input data signal, and thereby generate a second rising control signal and a first falling control signal. as well as A charge pump circuit, coupled to the voltage-controlled oscillator and the phase detector, is used to adjust the voltage signal according to the second rising control signal and the first falling control signal.

3. The clock and data recovery circuit as claimed in claim 2, wherein the phase detector is used to detect whether the clock signal is phase-leading or phase-lagging in the data recovery mode.

4. The clock and data recovery circuit as described in claim 3, further comprising: A phase-frequency detector is used to receive the reference signal and the feedback signal, detect the phase difference between the reference signal and the feedback signal, and correspondingly generate a third rising control signal and a second falling control signal. The phase frequency detector is used to detect the phase difference in clock recovery mode, so that the clock and data recovery circuit can lock the frequency of the clock signal. The charge pump circuit is also coupled to the phase frequency detector and is used to adjust the voltage signal according to the third rising control signal and the second falling control signal in the clock recovery mode.

5. The clock and data recovery circuit as described in claim 4, further comprising: A multiplexer, coupled to the phase detector, the phase frequency detector, and the charge pump circuit, is used to output the third rising control signal and the second falling control signal to the charge pump circuit in the clock recovery mode, and to output the second rising control signal and the first falling control signal to the charge pump circuit in the data recovery mode.

6. The clock and data recovery circuit as described in claim 4, further comprising: The frequency divider is coupled between the voltage-controlled oscillator and the phase-frequency detector, and is used to generate the feedback signal based on the clock signal and the frequency scaling factor.

7. The clock and data recovery circuit of claim 2, wherein the frequency detector is enabled at the start of the data recovery mode and disabled after a predetermined period of time.

8. A clock and data recovery circuit for recovering clock and data information from an input data signal, the clock and data recovery circuit comprising: A voltage-controlled oscillator is used to generate a clock signal based on a voltage signal; A frequency detector is used to detect whether the frequency of the clock signal needs to be increased based on multiple sampling results of the input data signal, and accordingly generate a first rising control signal. A phase detector is used to receive the input data signal and the clock signal, and to detect whether the clock signal is phase-leading or phase-lagging based on the multiple sampling results of the input data signal, and thereby generate a second rising control signal and a first falling control signal. A charge pump circuit is coupled to the voltage-controlled oscillator and the phase detector, and is used to adjust the voltage signal according to the second rising control signal and the first falling control signal; as well as A control circuit, coupled to the voltage-controlled oscillator and the frequency detector, is used to adjust the voltage signal according to the first rising control signal. The frequency of the clock signal is equal to the product of the frequency of the reference signal and the frequency scaling factor of the divider. The frequency of the clock signal is locked and is lower than the target clock frequency. After detecting that the frequency of the clock signal is locked, the clock and data recovery circuit operates in data recovery mode, and the frequency detector and the phase detector operate in data recovery mode to further lock to the target clock frequency.

9. The clock and data recovery circuit as described in claim 8, further comprising: A phase-frequency detector is used to receive a reference signal and a feedback signal, detect the phase difference between the reference signal and the feedback signal, and correspondingly generate a third rising control signal and a second falling control signal. The phase frequency detector is used to detect the phase difference in clock recovery mode, so that the clock and data recovery circuit can lock the frequency of the clock signal. The charge pump circuit is also coupled to the phase frequency detector and is used to adjust the voltage signal according to the third rising control signal and the second falling control signal in the clock recovery mode.

10. The clock and data recovery circuit of claim 9, further comprising: A multiplexer, coupled to the phase detector, the phase frequency detector, and the charge pump circuit, is used to output the third rising control signal and the second falling control signal to the charge pump circuit in the clock recovery mode, and to output the second rising control signal and the first falling control signal to the charge pump circuit in the data recovery mode.

11. The clock and data recovery circuit of claim 9, further comprising: The frequency divider is coupled between the voltage-controlled oscillator and the phase-frequency detector, and is used to generate the feedback signal based on the clock signal and the frequency scaling factor.

12. The clock and data recovery circuit of claim 9, wherein the frequency detector is enabled at the start of the data recovery mode and disabled after a predetermined period of time.

13. A clock and data recovery circuit for recovering clock and data information from an input data signal, the clock and data recovery circuit comprising: The clock recovery module is used to lock the frequency of the clock signal in clock recovery mode; as well as The data recovery module is used to operate in data recovery mode and recover data information based on the input data signal. The clock signal frequency is equal to the product of the reference signal frequency and the frequency scaling factor of the divider. The clock signal frequency is locked and is lower than the target clock frequency. After detecting that the clock signal frequency is locked, the clock and data recovery circuit switches from the clock recovery mode to the data recovery mode to further lock to the target clock frequency. The data recovery module includes: A voltage-controlled oscillator is used to generate the clock signal based on a voltage signal; A charge pump circuit is coupled to the voltage-controlled oscillator and is used to adjust the voltage signal according to the rising control signal and the falling control signal; A frequency detector is used to detect whether the frequency of the clock signal needs to be increased based on multiple samples of the input data signal, and accordingly generates a supplementary rise control signal; and The control circuit is coupled to the voltage-controlled oscillator and the frequency detector, and is used to further adjust the voltage signal according to the supplementary rise control signal.

14. The clock and data recovery circuit of claim 13, wherein the frequency detector is enabled at the start of the data recovery mode and disabled after a predetermined period of time.

15. The clock and data recovery circuit of claim 13, wherein the control circuit includes a current source, and the control circuit provides current to adjust the voltage signal by controlling the current source in response to the supplementary rising control signal.

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