A high sampling rate single acquisition channel vector network analysis implementation method and system

Abstract

The present invention discloses a high sampling rate single acquisition channel vector network analysis implementation method and system, the implementation method includes the following process: (1) when collecting signals, the channel switch is switched to one of the three intermediate frequency signals R, A, and B; (2) the ADC is sampled, and the collected intermediate frequency signal is mixed with the external input digital local oscillator NCO, and the mixed signal is low-pass filtered, and then data processed and stored; (3) after reaching the set sampling time or storage amount, the channel switch is switched to another intermediate frequency signal, and step (2) is executed; (4) the channel switch is switched to the last intermediate frequency signal, and step (2) is executed; (5) finally, the corresponding amplitude and phase information are calculated according to the three-way data. The implementation method and system disclosed by the present invention can effectively remove the noise in the band, improve the signal-to-noise ratio of the entire test system, and reduce the use of resources.

Description

Technical Field

[0001] The present invention relates to the field of vector network analysis, and in particular to a method and system for realizing high sampling rate single acquisition channel vector network analysis. Background Art

[0002] With the advancement of modern technology, test indicators and functions are becoming increasingly diverse, placing higher demands on the integration and miniaturization of test instruments. Test instruments with simultaneous transceiver systems, such as vector signal transceivers, no longer solely perform traditional signal transmission and reception functions but also integrate with RF front-ends to implement vector network analysis. Many signal transceivers only have a single acquisition channel, making conventional vector network analysis methods infeasible. Therefore, research on single-channel vector network analysis implementation methods is essential.

[0003] At present, the traditional implementation method of single acquisition channel vector network analysis based on the signal transceiver integrated hardware structure is to use a single ADC to sample the three intermediate frequency signals R, A, and B in time-sharing mode. During the whole process, single data points of the three intermediate frequency signals R, A, and B are collected in sequence at fixed time intervals. The data are switched in cycles for multiple rounds until the required number of data points for each channel are collected, and then data processing is performed. The specific implementation method is as follows: Figure 1 As shown in the figure, the time-sharing sampler performs counting control based on the data clock provided by the ADC. It generates switch control signals at fixed counting intervals to switch the three intermediate frequency signals R, A, and B. During the fixed counting interval, the signal must be stable after channel switching. Then, the sampled value of each channel point is acquired at each fixed time. This process is repeated multiple times to obtain the three collected signals R, A, and B. The three collected signals are mixed with three digital local oscillators (NCOs). The three NCOs must maintain the same initial phase. As each signal is enabled, the phases are superimposed to ensure accurate phase measurement. After mixing, the data enters a low-pass filter to remove the high-frequency signals introduced by the mixing. Subsequent data processing includes decimation and filtering as needed to obtain the processed intermediate frequency data for R, A, and B. The corresponding amplitude and phase information can be calculated from these three data channels.

[0004] The above method is not suitable for vector signal transceiver systems with large-bandwidth channels. In this technology, the three-way sampling period is an integer multiple of the ADC sampling period. This sampling period includes channel switching, stabilization time, and signal acquisition time, and is much longer than the ADC sampling period. For vector signal transceiver systems with large-bandwidth channels, the anti-aliasing analog filter bandwidth of the ADC front end is very large, often reaching hundreds of MHz or even higher. Using this method will introduce broadband channel noise into the signal bandwidth, causing aliasing and affecting test performance. Furthermore, the above method requires frequent and repeated switching of switches, placing high demands on channel switching time and system stability. Furthermore, the existing data processing technology is complex. Considering real-time requirements, the three-way data processing process cannot be reused, requiring three independent digital local oscillator (NCO) and decimation filter channels, resulting in a relatively complex circuit structure. Summary of the Invention

[0005] To solve the above technical problems, the present invention provides a high sampling rate single acquisition channel vector network analysis implementation method and system, so as to effectively remove the noise in the band, improve the signal-to-noise ratio of the entire test system, and reduce resource usage.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] A high sampling rate single acquisition channel vector network analysis implementation method includes the following process:

[0008] (1) When collecting signals, the channel switch switches to one of the three intermediate frequency signals R, A, and B;

[0009] (2) The ADC samples and collects one of the intermediate frequency signals and mixes it with the external digital local oscillator (NCO). The mixed signal is low-pass filtered, processed, and then stored.

[0010] (3) After reaching the set sampling time or storage amount, the channel switch switches to another intermediate frequency signal and executes step (2);

[0011] (4) After the set sampling time or storage amount is reached, the acquisition of the second intermediate frequency signal is completed, and the channel switch is switched to the last intermediate frequency signal, and step (2) is executed, thus completing the acquisition of the three intermediate frequency signals;

[0012] (5) Finally, the corresponding amplitude and phase information are calculated based on the three-way data.

[0013] In the above scheme, the three intermediate frequency signals R, A, and B all maintain a fixed phase difference with the ADC acquisition clock and also maintain a fixed phase difference with the ADC digital output clock.

[0014] In the above solution, the three intermediate frequency signals R, A, and B also maintain a fixed phase difference with the digital local oscillator NCO constructed using the ADC digital output clock.

[0015] In the above scheme, the data processing in step (2) includes extraction and filtering.

[0016] In the above solution, the digital local oscillator NCO keeps running throughout the entire process from step (1) to step (5).

[0017] In the above solution, the controller generates a switch control signal to control the switching of the channel switch according to the data storage situation and the sampling time.

[0018] A high sampling rate single acquisition channel vector network analysis implementation system includes a channel switch, an ADC, a mixer, a low-pass filter, a data processor and a data storage device connected in sequence. The mixer is also connected to a digital local oscillator (NCO). The channel switch is connected to a radio frequency front end. A controller is connected to the data storage device and the channel switch.

[0019] Through the above technical solution, the high sampling rate single acquisition channel vector network analysis implementation method and system provided by the present invention have the following beneficial effects:

[0020] 1. The present invention does not require frequent acquisition of the R, A, and B intermediate frequency signals at fixed times. Instead, the three signals are acquired in sequence using ADCs. Subsequent data processing can effectively remove in-band noise and improve the signal-to-noise ratio of the entire test system.

[0021] 2. Since the present invention uses ADCs to collect three signals in sequence, the three data are multiplexed and mixed based on a pipeline structure and a subsequent data processor, which can reduce resource usage.

[0022] 3. The present invention can be applied to a hardware system integrating transceiver and transmitter of large bandwidth signals. The data rate of the three-way intermediate frequency acquisition is consistent with the ADC sampling rate, which can effectively remove in-band noise.

[0023] 4. The present invention completes the processing process once, and the channel switch only needs to be switched three times, without the need for frequent switching, thereby improving the stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for describing the embodiments or the prior art.

[0025] Figure 1 This is a flow chart of a method for implementing vector network analysis in the prior art;

[0026] Figure 2This is a flow chart of a method for implementing high sampling rate single acquisition channel vector network analysis disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0028] The present invention provides a high sampling rate single acquisition channel vector network analysis implementation method, such as Figure 2 As shown, the process includes the following:

[0029] (1) When collecting signals, the channel switch switches to one of the three intermediate frequency signals R, A, and B;

[0030] (2) The ADC performs sampling and collects one of the intermediate frequency signals to mix with the external digital local oscillator (NCO). The mixed signal is low-pass filtered and then processed by decimation and filtering before being stored.

[0031] (3) After reaching the set sampling time or storage amount, the channel switch switches to another intermediate frequency signal and executes step (2);

[0032] (4) After the set sampling time or storage amount is reached, the acquisition of the second intermediate frequency signal is completed, and the channel switch is switched to the last intermediate frequency signal, and step (2) is executed, thus completing the acquisition of the three intermediate frequency signals;

[0033] (5) Finally, the corresponding amplitude and phase information are calculated based on the three-way data.

[0034] In the present invention, the three intermediate frequency signals R, A, and B all maintain a fixed phase difference with the ADC acquisition clock and the ADC digital output clock. The three intermediate frequency signals R, A, and B also maintain a fixed phase difference with the digital local oscillator (NCO) constructed using the ADC digital output clock.

[0035] During the entire process from step (1) to step (5), the digital local oscillator NCO keeps running without interruption to ensure the correctness of the phase test.

[0036] In the present invention, the controller generates a switch control signal to control the switching of the channel switch according to the data storage situation and the sampling time. In the present invention, there is no need to frequently switch the switch, and only three switches are needed to complete a processing process.

[0037] A high sampling rate single acquisition channel vector network analysis implementation system includes a channel switch, an ADC, a mixer, a low-pass filter, a data processor and a data storage device connected in sequence. The mixer is also connected to a digital local oscillator (NCO). The channel switch is connected to a radio frequency front end. The controller is connected to the data storage device and the channel switch.

[0038] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A high sampling rate single acquisition channel vector network analysis implementation method, characterized in that: The process includes the following: (1) When collecting signals, the channel switch is switched to one of the three intermediate frequency signals R, A, and B; (2) The ADC samples and collects one of the intermediate frequency signals and mixes it with the external digital local oscillator NCO. The mixed signal is low-pass filtered, processed and stored. (3) When the set sampling time or storage volume is reached, the channel switch switches to another intermediate frequency signal and executes step (2); (4) After the set sampling time or storage amount is reached, the acquisition of the second intermediate frequency signal is completed, and the channel switch is switched to the last intermediate frequency signal, and step (2) is executed, thus completing the acquisition of the three intermediate frequency signals; (5) Finally, the corresponding amplitude and phase information are calculated based on the three-way data.

2. A high sampling rate single acquisition channel vector network analysis implementation method according to claim 1, characterized in that: The three intermediate frequency signals R, A, and B all maintain a fixed phase difference with the ADC acquisition clock, and also maintain a fixed phase difference with the ADC digital output clock.

3. A high sampling rate single acquisition channel vector network analysis implementation method according to claim 2, characterized in that: The three intermediate frequency signals R, A, and B also maintain a fixed phase difference with the digital local oscillator NCO constructed using the ADC digital output clock.

4. The method for realizing high sampling rate single acquisition channel vector network analysis according to claim 1, characterized in that: The data processing in step (2) includes decimation and filtering.

5. The high sampling rate single acquisition channel vector network analysis implementation method according to claim 1, characterized in that: During the entire process from step (1) to step (5), the digital local oscillator NCO keeps running.

6. The high sampling rate single acquisition channel vector network analysis implementation method according to claim 1, characterized in that: The controller generates a switch control signal to control the switching of the channel switch according to the data storage situation and the sampling time.

7. A high sampling rate single acquisition channel vector network analysis implementation system using the method as claimed in claim 1, characterized in that: It includes a channel switch, an ADC, a mixer, a low-pass filter, a data processor and a data storage device which are connected in sequence. The mixer is also connected to a digital local oscillator NCO. The channel switch is connected to a radio frequency front end. The controller is connected to the data storage device and the channel switch.

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