Precharge techniques for improving sequential memory access in a memory device

Abstract

Apparatuses and techniques for improving memory access operations of a memory device are provided. In an example, a method can include loading a plurality of L2P regions of an L2P table from a memory array of a memory device to a mapping cache in response to determining that an LBA of a memory access command is not within the L2P regions including the mapping cache. The plurality of L2P regions loaded to the mapping cache can provide improved memory access performance when the memory access command is a contiguous command.

Description

[0001] Priority application

[0002] This application claims priority to international application PCT / CN2020 / 07414, filed on March 15, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments described herein generally relate to systems and methods for improving the processing volume of access commands for flash memory devices. Background Technology

[0004] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and includes various forms of random access memory (RAM), such as dynamic random access memory (DRAM) or synchronous dynamic random access memory (SDRAM). Non-volatile memory can retain stored data when no power is supplied (in some cases, it can be implemented as read-only memory (ROM)) and can incorporate one or more memory technologies, such as flash memory (e.g., NAND or NOR flash), electrically erasable programmable ROM (EEPROM), static RAM (SRAM), ferroelectric RAM (FeRAM), erasable programmable ROM (EPROM), resistive variable memory (e.g., phase-change random access memory (PCRAM)), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or 3D XPoint. TM Memory, etc.

[0005] Flash memory is used as non-volatile memory in a variety of electronic applications. Flash memory devices typically contain one or more groups of single transistors, floating-gate, or charge-trapping memory cells that allow for high storage density, high reliability, and low power consumption. Two common types of flash memory array architectures include NAND and NOR architectures, named after the logical form of the basic memory cell configuration in which each is arranged. The memory cells of a memory array are typically arranged in a matrix. In one example, the gate of each floating-gate memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drain of each memory cell in a string of the array is coupled together with the source-drain series coupling between the source line and the bit line.

[0006] Memory device access speed is a common problem, especially as current and newer electronic devices incorporate increasingly faster processors and applications require faster and more accurate real-time information feedback. Therefore, improvements that enhance the speed of memory devices can offer significant technical and practical advantages. Attached Figure Description

[0007] In drawings that are not necessarily drawn to scale, the same element symbols may describe similar components in different views. The same element symbols with different letter suffixes may represent different examples of similar components. The drawings generally illustrate the various embodiments discussed in this invention by way of example rather than limitation.

[0008] Figure 1 A conceptual diagram illustrating an example of an environment including a memory device according to the present invention.

[0009] Figure 2 A block diagram illustrating, generally speaking, the mapping table data that can be located during operation of a memory device (e.g., a UFS device) according to the present invention.

[0010] Figure 3A This section broadly describes the three main delays associated with read commands in a conventional flash device.

[0011] Figure 3B This section generally describes an instance read sequence containing an L2P region preload according to the present invention.

[0012] Figure 4 An example method of operating a flash memory device according to the present invention is generally described.

[0013] Figure 5 The flowchart illustrates an example method according to the present invention for loading multiple L2P areas into an L2P cache after an L2P cache miss.

[0014] Figure 6 It is a block diagram illustrating an example of a machine on which one or more embodiments may be implemented. Detailed Implementation

[0015] Memory devices comprise individual memory dies, which may, for example, include memory regions comprising one or more memory cell arrays implementing one or more selected memory technologies. These memory dies typically include supporting circuitry for operating the memory array. Other examples (sometimes commonly referred to as “managed memory devices”) comprise combinations of one or more memory dies associated with memory controller functionality configured to control the operation of one or more memory dies. This memory controller functionality simplifies interoperability with external devices (such as “hosts” discussed later herein) and further facilitates the management of (typically) multiple discrete memory devices. In such managed memory devices, the controller functionality may be implemented on one or more dies also incorporated into the memory array or on a single die. In other memory devices, one or more memory devices may be combined with memory controller functionality to form a solid-state drive (SSD) storage volume.

[0016] The exemplary embodiments of this disclosure are described in the examples of managed memory devices (referred to as “managed NAND” devices) that implement NAND flash memory cells. However, these examples do not limit the scope of this disclosure, which can be implemented in memory devices that implement other memory storage technologies (such as the non-limiting examples discussed earlier herein). Managed NAND devices can be used as primary or secondary memory in various forms of electronic devices and are commonly used in mobile devices.

[0017] In an array of NOR or NAND architecture semiconductor memory, each flash memory cell can be programmed to two or more programming states. For example, a single-level cell (SLC) can represent one of two programming states (e.g., 1 or 0), representing one data bit. Flash memory cells can also represent more than two programming states, allowing for the fabrication of higher-density memories without increasing the number of memory cells, since each cell can represent more than one binary digit (e.g., more than one bit). Such cells may be called multi-state memory cells, multi-digit cells, or multi-level cells (MLC). In some instances, MLC may refer to a memory cell that can store two data bits per cell (e.g., one of four programming states), TLC may refer to a memory cell that can store three data bits per cell (e.g., one of eight programming states), and QLC may store four data bits per cell. MLC is used more broadly in this document to refer to any memory cell that can store more than one data bit per cell (i.e., that can represent more than two programming states; therefore, the term MLC is used more broadly in this document to refer to a memory cell that stores 2, 3, 4 or more data bits per cell).

[0018] Managed memory devices can be configured and operated according to recognized industry standards. For example, a managed NAND device can be (as a non-limiting example) Universal Flash Storage (UFS). TM ) device, embedded MMC device (eMMC) TM For example, in the above instances, UFS devices can be configured according to Joint Electronic Devices Engineering Committee (JEDEC) standards (e.g., JEDEC standard JESD223D entitled "JEDEC UFS Flash Storage 3.0" and / or later or subsequent versions of this standard). Similarly, identified eMMC devices can be configured according to JEDEC standard JESD84-A51 entitled "JEDEC eMMC standard 5.1" and / or later or subsequent versions of this standard. Identified standards are provided only for instance environments in which the described methods and structures can be utilized, but such methods and structures can be used in various environments other than identified standards (or any other actual or proposing standards), except as expressly indicated herein.

[0019] SSDs are particularly useful as primary storage devices for computers, offering advantages over traditional hard drives with moving parts in areas such as performance, size, weight, durability, operating temperature range, and power consumption. For example, SSDs can have reduced seek time, latency, or other delays compared to conventional disk drives. SSDs use non-volatile memory cells (such as flash memory cells), thus allowing for more versatile and compact drives.

[0020] Both SSDs and managed memory devices may contain several memory devices (comprising several dies or logical units (e.g., logical unit numbers or LUNs)) and typically include a memory controller comprising a processing circuitry system, which will typically include one or more processors that perform logical functions to operate the memory devices or interface with external systems. Such SSDs and managed memory devices may contain one or more flash memory dies on which several memory arrays and peripheral circuitry are contained. Flash memory arrays may contain several memory cell blocks organized into several physical pages or blocks. In some instances, SSDs may also contain DRAM or SRAM (or other forms of memory dies or other memory structures) as part of the controller, for example. Similarly, managed NAND devices may contain one or more volatile and / or non-volatile memory arrays that are separate from or within the controller, and separate from the NAND memory array. Both the SSD and the managed NAND device can receive commands from the host associated with memory operations, such as read or write operations that transfer data (e.g., user data and associated integrity data, such as error data and address data) between the memory device and the host, or erase operations that erase data from one or more memory devices.

[0021] The embodiments of this invention will be described primarily with reference to managed NAND devices constructed and operated according to the UFS standard. Although such managed NAND devices and the UFS standard only represent relevant instance configurations, the methods and structures of this invention can be implemented in memory devices that implement other storage technologies and / or other standards or operating protocols.

[0022] This description relates to memory devices, methods, and examples of machine-readable media for managing memory devices including memory controllers configured to receive instructions from host devices. The memory controller is configured to perform operations including: placing the memory controller in a low-power mode during memory management operations; and in many instances, setting a wake-up time based on a predicted completion time of the memory management operation (which may be provided by, for example, a memory communication interface communicating with a memory array). The memory controller also operates to switch the memory controller out of low-power mode after at least one of, for example: receiving another memory management operation; the wake-up time expiring; and receiving an interrupt from one or more selected hardware resources. In sample embodiments, the memory array is a NAND memory array and the memory management operation is one of: programming a portion of the NAND memory array, erasing a portion of the NAND memory array, and reading from the NAND memory array.

[0023] Figure 1The description includes an example of an environment 100 containing a host device 105 and a memory device 110 configured to communicate via a communication interface 111. The host device 105 or the memory device 110 may be included in various products 150 (e.g., Internet of Things (IoT) devices such as refrigerators or other appliances, sensors, motors or actuators, mobile communication devices, automobiles, drones, etc.)) to support the processing, communication, or control of the product 150.

[0024] Memory device 110 includes a memory controller 115 and a memory array 120, which includes, for example, several individual memory dies (e.g., a stack of 3D NAND dies). In one example, memory device 110 may be a discrete memory or storage device component of host device 105. In other examples, memory device 110 may be a portion of an integrated circuit (e.g., a system-on-a-chip (SoC)) stacked or otherwise included with one or more other components of host device 105. In these examples, memory device 110 communicates with components of host device 105 via communication interface 111. Therefore, as described herein, even though memory device 110 is integrated into host device 105, the operation of the host or host device 105 differs from the operation of memory device 110.

[0025] Various communication interfaces can be used to transfer data between the memory device 110 and one or more other components of the host device 105, such as the Serial Advanced Technology Attachment (SATA) interface, the Peripheral Component Interconnect High Speed ​​(PCIe) interface, the Universal Serial Bus (USB) interface, the Universal Flash Memory (UFS) interface, and eMMC. TM An interface or one or more other connectors or interfaces. Host device 105 may include a host system, electronic devices, a processor, a memory card reader, or one or more other electronic devices external to memory device 110. In some instances, host 105 may be a device with a reference... Figure 6 The machine 600 is a component of the machine, either part or all of it.

[0026] The memory controller 115 may receive instructions from the host 105 and may communicate with the memory array 120 to (e.g.) transfer (e.g., write) data to or from one or more memory cells, planes, sub-blocks, blocks, or pages of the memory array 120, or to erase one or more memory cells, planes, sub-blocks, blocks, or pages of the memory array 120. For example, the memory controller 115 includes a processing circuitry system comprising one or more processors, which, when present, operate to execute instructions stored in the memory device. For the purposes of this invention, although the instructions may also exist as software, they will be discussed as firmware; and all or part of the described functionality may also be implemented in a circuitry system comprising one or more components or integrated circuits.

[0027] For example, memory controller 115 may include one or more memory control units, circuitry, or components configured to control access across memory array 120 and provide a translation layer between host 105 and memory device 110. Additionally, the memory controller may include a memory interface for interfacing with the associated memory device. In some instances, the memory interface may be an Open NAND Flash Interface (ONFI). Although memory controller 115 is described herein as part of the memory device 110 package, other configurations may be employed, such as memory controller 115 as a component of host 105 (e.g., as a discrete package on a single-chip system of host 105 separate from memory service 110) or even implemented via the central processing unit (CPU) of host 105.

[0028] Memory manager 125 may include, in particular, multiple components or integrated circuits and / or instructions for execution associated with various memory management functions. In some embodiments, the functionality of memory manager 125 is implemented by a controller (or processor) that executes firmware instructions, which in some instances are stored within memory controller 115. In other instances, memory manager 125 may be implemented at least partially by one or more processors within memory controller 115, which may execute instructions stored in memory array 120. Similarly, management tables 130 (e.g., mapping tables or logical block-to-physical address (L2P) tables) may be stored on memory controller 115 or in memory array 120. In such instances, instructions and / or management tables 130 may be stored in certain blocks of NAND die stack 120 and loaded into the working memory of memory controller 115 during operation.

[0029] For the purposes of this description, the instance memory operation and management functions will be described in the context of NAND memory. Those skilled in the art will recognize that other forms of non-volatile memory may have similar memory operation or management functions. Such NAND management functions include wear leveling, discarded item collection, recycling, error detection or correction, block deactivation, or one or more other memory management functions. Memory manager 125 may parse or format host commands (e.g., commands received from a host) into device commands (e.g., commands associated with the operation of memory array 120) or generate device commands for array controller 135 or one or more other components of memory device 110 (e.g., for performing various memory management functions). Such internally generated operations (e.g., discarded item collection, wear leveling, etc.) may result in the execution of operations that can provide opportunities for the power management operations described herein in the same manner as externally guided memory operations.

[0030] The memory manager 125 may include a set of management tables 130 configured to maintain various information associated with one or more components of the memory device 110, such as various information associated with the memory array or one or more memory cells coupled to the memory controller 115. For example, management table 130 may contain information about block age, block erase count, error history, or one or more error counts (e.g., write operation error count, read bit error count, read operation error count, erase error count, etc.) of one or more blocks of the memory cells coupled to the memory controller 115. In some instances, a bit error may be termed an uncorrectable bit error if the number of detected errors in one or more of the error counts exceeds a threshold. Management table 130 may, in particular, maintain counts of correctable or uncorrectable bit errors. In instances, management table 130 may contain a translation table or a logic-to-physical (L2P) table, or a portion thereof.

[0031] The array controller 135 may further include, in particular, circuitry or components configured to control memory operations associated with writing data to, reading data from, or erasing data from the memory cells of the memory device 110 coupled to the memory controller 115. Memory operations may be based on host commands, for example, received from the host 105 or generated internally by the memory manager 125 (e.g., associated with wear leveling, error detection, or correction).

[0032] The array controller 135 may further include an error correction code (ECC) component 140, which may in particular include an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells coupled to the memory device 110 of the memory controller 115. The memory controller 115 may be configured to proactively detect and recover from various errors associated with data operation or storage, such as bit errors, operational errors, etc., based on ECC data maintained by the array controller 135. This enables the memory controller 115 to maintain the integrity of data transferred between the host 105 and the memory device 110, or to maintain the integrity of stored data. This integrity maintenance may include removing (e.g., retiring) failed memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.

[0033] Memory array 120 may contain several memory cells arranged, for example, as devices, planes, sub-blocks, blocks, or pages. As an example, a 48GB TLC NAND memory device may contain 18,592 data bytes (B) per page (16,384 + 2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device. As another example, a 32GB MLC memory device (storing two data bits per cell (i.e., 4 programmable states)) may contain 18,592 data bytes (B) per page (16,384 + 2208 bytes), 1024 pages per block, 548 blocks per plane, and 4 planes per device, but with half the write time and twice the program / erase (P / E) cycles of a corresponding TLC memory device. Other examples may contain other numbers or arrangements. In some examples, the memory device or a portion thereof may selectively operate in SLC mode or a desired MLC mode (e.g., TLC, QLC, etc.).

[0034] During operation, data is typically written to or read from NAND memory device 110 in pages and erased in blocks. However, one or more memory operations (e.g., read, write, erase, etc.) may be performed on larger or smaller groups of memory cells as desired. The data transfer size of NAND memory device 110 is typically referred to as a page, while the data transfer size of the host is typically referred to as a sector.

[0035] In some instances, the memory array may include several NAND dies, and one or more functions of the memory controller 115 for a particular NAND die may be implemented on a die-on-die controller on said particular die. Other organization and description of control functionality may also be utilized, such as controllers for each die, plane, superblock, block, page, and the like.

[0036] Although a data page may contain several bytes of user data (e.g., a data payload comprising several data sectors) and its corresponding metadata, the page size typically refers only to the number of bytes used to store the user data. For example, a data page with a 4KB page size may contain 4KB of user data (e.g., eight sectors of 512B sector size) and several bytes of metadata corresponding to the user data (e.g., 32B, 54B, 224B, etc.), such as integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data.

[0037] Different types of memory cells or memory arrays 120 can provide different page sizes or require different amounts of metadata associated with them. For example, different memory device types may have different bit error rates, which can result in different amounts of metadata required to ensure the integrity of data pages (e.g., a memory device with a higher bit error rate requires more error correction code data bytes than a memory device with a lower bit error rate). As an example, an MLC NAND flash device may have a higher bit error rate than its corresponding SLC NAND flash device. Therefore, an MLC device requires more metadata bytes for error data than its corresponding SLC device. In some instances, the memory array may contain a complete mapping table or L2P table 161.

[0038] Figure 2 This diagram broadly illustrates the mapping table data or L2P table data that can be located during operation of memory device 110 (e.g., a UFS device). In some instances, the complete mapping table 161 may be stored in the memory array of memory device 110, and portions of mapping table 161 may be retrieved as needed by memory controller 115. Mapping table 161 may be divided into multiple L2P regions 260n. Within each L2P region 260n, there are multiple consecutive LBAs (e.g., 256 LBAs, 512 LBAs, 1024 LBAs, 2048 LBAs, etc.) of physical addresses (PAs). L2P regions can serve as the basic unit for loading and updating from / to flash memory.

[0039] For a read command, memory controller 115 can perform LBA translation to find one or more physical addresses (Pa) of one or more LBAs associated with the read command. If the required mapped data is in the L2P cache of management table 130 within memory controller 115, then memory controller 115 can quickly obtain the physical address. However, due to the limited size of the L2P cache, the L2P cache hit rate may be low, which means that a large number of read command executions are used to load the appropriate L2P area 260n from flash memory 120. The overhead of L2P mapping load from flash memory 120 to the L2P cache is a factor that may inhibit the read performance of memory device 110.

[0040] As discussed above, an L2P area can be the basic unit transferred from the flash array to the L2P cache. When there is no suitable L2P area in the L2P cache available to translate the LBA of a received read command (e.g., an L2P cache miss), the memory controller of a conventional memory device transfers an L2P area from the flash to the L2P cache.

[0041] While not limited to this, the L2P area size can be 2KB or 4KB. For sequential reads, once an L2P area is loaded from flash into the L2P cache, it can serve 2MB or 4MB of host reads. Therefore, the memory controller typically loads one L2P area from flash after each 2MB or 4MB host read. The overhead of loading an L2P area includes the read time for loading the L2P area from flash and the latency associated with the memory controller overhead for scheduling the L2P load task. Therefore, the read throughput of a conventional flash memory device may not reach its potential maximum throughput speed due to the overhead of loading mapped data.

[0042] Figure 3A This section outlines three main latency issues associated with read commands in a conventional flash device discussed above. These latency issues may include the latency associated with reading the requested data 370 (e.g., 2 to 4 MB of user data), the memory controller overhead 371 for scheduling and executing the transfer of the L2P area from the flash array to the L2P cache, and the latency associated with the actual transfer 372 of the L2P area from the flash array to the L2P cache.

[0043] Figure 3B This section broadly describes the instance read sequence, including L2P area preloading. To reduce the overhead of L2P area loading, in some instances, the memory controller may preload multiple L2P areas for sequential reads. In some instances, when the memory controller detects a sequential read mode, it may load multiple L2P areas (e.g., eight L2P areas) instead of just one. For example, if eight 4KB L2P areas are loaded into the L2P cache, these areas can provide a mapping of up to 32MB of user data.

[0044] Refer again Figure 3A For a typical device reading 32MB of data, the memory controller schedules the L2P area load task 8 times. However, as... Figure 3B As shown, the memory device for reading 32MB of user data according to the present invention can schedule L2P area loading tasks once and can load multiple L2P areas from the flash array into the L2P cache to support many LBA translations associated with sequential reads. Therefore, memory controller overhead can be reduced.

[0045] In addition, the conventional device costs 8xtR (t R = Flash read time) to load 8 L2P areas. However, instance devices using L2P area preloading can send 8 flash read commands to the flash in batches. These commands can be distributed across all flash dies. Since flash commands on different dies can be executed in parallel, in the best case, it only takes one flash read time (t) to load 8 L2P areas. R Read all 8 L2P areas. In the worst case, all 8 flash read commands target the same die, which will then take 8 seconds. R To load 8 L2P areas. In summary, the total time for loading 8 L2P areas in batches will be less than the time for loading 8 L2P areas one by one.

[0046] Table 1 illustrates the performance improvements of the example memory devices operating with and without pre-loaded multiple L2P areas for both single-level cell (SLC) and three-level cell (TLC) memory.

[0047] capacity Flash type Standard processing capacity (MB / s) Processing capacity w / preload (MB / s) improve 256GB SLC 1845 2020 9.5％ 256GB TLC 1730 1950 12.7％

[0048] Table 1

[0049] In some instances, multiple L2P regions of the L2P cache are loaded only when a sequential read mode is detected. When no sequential read mode is detected, the memory controller loads a single L2P region on an L2P cache miss event. In some instances, preloading more L2P regions for sequential reads can improve sequential read performance by approximately 10%.

[0050] Figure 4 This section describes an example method 400 for operating a flash memory device. At 401, the memory controller or host interface of the flash memory device receives a memory access command from a host. At 403, it can be determined whether a first LBA received with the memory access command is indexed in an L2P area within the L2P cache, resulting in an "L2P cache hit". At 405, if the first LBA is not indexed in the LBA-to-Physical Address (L2P) table portion of the L2P cache, then multiple L2P areas of the complete L2P table can be loaded from the flash memory into the L2P cache. At 407, the physical address of the flash memory can be determined based on the first LBA and the L2P areas among the multiple L2P areas in the L2P cache. At 409, the memory access command can be executed using the physical address. In some instances, multiple L2P areas are loaded into the L2P cache only in response to determining that the memory access command is a sequential read command. If it is determined that the memory access command is not a sequential read command and the memory controller encounters an L2P cache miss, then a single L2P area corresponding to the LBA received along with the memory access command will be loaded from flash memory into the L2P cache.

[0051] If multiple L2P regions are loaded from the flash array into the L2P cache in response to determining that a memory access command is a sequential read command, the memory controller can achieve higher data read throughput because subsequent read commands associated with sequential reads will not encounter L2P cache misses.

[0052] Figure 5 This section generally illustrates a flowchart of an example method 505 according to the present invention, which loads multiple L2P areas into the L2P cache after an L2P cache miss. In some instances, and as described above regarding... Figure 4 The method describes loading multiple L2P regions only after an L2P cache miss and after determining that the memory access command is a sequential read command (a sequential read command within multiple L2P regions). Method 505 may be initiated at 511 in response to an L2P cache miss. At 511, the command may be evaluated to determine whether the memory access command is a read command. If the command is not a read command, then the method may continue to 513 and a single L2P region may be loaded into the L2P cache. If it is determined that the current command is a read command, then historical command information may be evaluated. In some instances, if the immediately preceding command is not a read command, then the current command is not considered a sequential read command. In some instances, a minimum number of immediately preceding commands (e.g., the most recent 4 commands) need to be read commands before the current command is considered a potential sequential read command. At 515, optionally, if the minimum number of immediately preceding commands are not read commands, then the method continues to 513 and a single L2P region is loaded into the L2P cache. In 517, the data block size, the number of LBAs read by the current read command, or the length of read data read by the current read command can be optionally evaluated based on the minimum size. If the data block size of the current read command is not equal to or greater than the minimum size (e.g., the maximum block size or page size), then the method can continue to 513 and load a single L2P area into the L2P cache.

[0053] In 519, the starting LBA of the current read command can be evaluated with respect to the parameters immediately following the previous read command. For example, if the LBA of the previous command plus the data block size of the previous read command equals the LBA of the current read command, then the current read command can be determined to be a sequential read command. In some instances, the sum of the LBA of the previous command and the data size of the previous command can point to an LBA adjacent to the LBA of the current command to satisfy the determination that the current read command is a sequential read command. If the evaluation of the current command, the LBA of the previous command, and the data block parameters does not align with support for sequential reads, then the method can continue to 513 and a single L2P area is loaded into the L2P cache.

[0054] In step 521, after evaluating whether the current command is a sequential read command through one or more of steps 511, 515, 517, or 519, multiple LBAs can be loaded into the L2P cache to support the current read command and any subsequent read commands. In step 523, the parameters of the current command can be saved to provide historical command information.

[0055] Figure 6 A block diagram illustrating an instance machine 600 on which any or more of the techniques (e.g., methodologies) discussed herein can be implemented. For example, any of the memory systems (main memory 604, static memory 606, and mass storage device 621) within machine 600 can implement the techniques discussed herein. Figures 1 to 4 The improved memory access command execution is discussed. In alternative embodiments, machine 600 may operate as a standalone device or be connected (e.g., networked) to other machines. In a networked deployment, machine 600 may act as a server machine or a client machine, or both, in a server-client network environment. In an example, machine 600 may act as a peer-to-peer (P2P) (or other distributed) network environment. Machine 600 may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network device, IoT device, automotive system, or any machine capable of (sequentially or otherwise) executing instructions specifying actions to be taken by the machine. Furthermore, while only a single machine is described, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methodologies discussed herein (e.g., cloud computing, Software as a Service (SaaS), other computer cluster configurations).

[0056] As described herein, an instance may comprise or be operable by logic, components, devices, packages, or mechanisms. A circuit system is a collection (e.g., a group of circuits) of circuits implemented in a tangible entity containing hardware (e.g., simple circuits, gates, logic, etc.). The membership of a circuit system can vary flexibly over time and with the variability of the underlying hardware. A circuit system contains members that can perform specific tasks individually or in combination during operation. In an instance, the hardware of a circuit system may be designed invariantly to perform specific operations (e.g., hardwired). In an instance, the hardware of a circuit system may contain variablely connected physical components (e.g., execution units, transistors, simple circuits, etc.) containing computer-readable media that have been physically modified (e.g., magnetic, electrical, movable placement of massless particles, etc.) to encode instructions for specific operations. When connecting physical components, the underlying electrical properties of the hardware configuration (e.g.,) change from an insulator to a conductor, or vice versa. Instructions enable participating hardware (e.g., execution units or load mechanisms) to generate portions of the circuit system members in the hardware via variable connections to perform specific tasks during operation. Therefore, when the device is operating, it can be communicatively coupled to other components of the circuit system via computer-readable media. In an example, any of the physical components can be used in more than one member of more than one circuit system. For instance, under operation, an execution unit can be used at one point in a first circuit of a first circuit system and reused at a different time by a second circuit in the first circuit system or a third circuit in the second circuit system.

[0057] Machine (e.g., computer system) 600 (e.g., host device 105, memory device 110, etc.) may include a hardware processor 602 (e.g., a central processing unit (CPU), graphics processing unit (GPU), hardware processor core, or any combination thereof, such as memory controller 115, etc.), main memory 604, and static memory 606, some or all of which may communicate with each other via interconnect (e.g., bus) 608. Machine 600 may further include a display unit 610, an alphanumeric input device 612 (e.g., keyboard), and a user interface (UI) navigation device 614 (e.g., mouse). In an example, the display unit 610, input device 612, and UI navigation device 614 may be a touch screen display. Machine 600 may additionally include a storage device (e.g., drive unit) 621, a signal generating device 618 (e.g., speaker), a network interface device 620, and one or more sensors 616, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. Machine 600 may include output controller 628, for example, for communicating or controlling one or more peripheral devices (e.g., printer, card reader, etc.) via serial (e.g., Universal Serial Bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connections).

[0058] Storage device 621 may include machine-readable medium 622 thereon storing one or more sets of data structures or instructions 624 (e.g., software) embodying or utilized by any or more of the techniques or functions described herein. Instructions 624 may also reside wholly or at least partially within main memory 604, static memory 606, or hardware processor 602 during execution by machine 600. In an example, one or any combination of hardware processor 602, main memory 604, static memory 606, or storage device 621 may constitute machine-readable medium 622.

[0059] Although machine-readable media 622 is described as a single medium, the term "machine-readable media" may include a single medium or multiple media (e.g., a centralized or distributed database or associated cache and server) configured to store one or more instructions 624.

[0060] The term "machine-readable medium" may include any medium capable of storing, encoding, or transmitting instructions executable by machine 600 and causing machine 600 to perform any or more of the technologies disclosed herein, or any medium capable of storing, encoding, or transmitting data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory and optical and magnetic media. In examples, aggregated machine-readable media includes machine-readable media having a plurality of particles with invariant (e.g., rest) mass. Therefore, aggregated machine-readable media is not a transient propagation signal. Specific examples of aggregated machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0061] Instructions 624 (e.g., software, programs, operating systems (OS), etc.) or other data are stored on storage device 621 and are accessible by memory 604 for use by processor 602. Memory 604 (e.g., DRAM) is typically fast but volatile, and is therefore a different type of storage than storage device 621 (e.g., SSD), which is suitable for long-term storage (including under "power-off" conditions). Instructions 624 or data used by the user or machine 600 are typically loaded into memory 604 for use by processor 602. When memory 604 is full, virtual space from storage device 621 can be allocated to supplement memory 604; however, because storage device 621 is typically slower than memory 604 and write speeds are typically at least twice as slow as read speeds, using virtual memory can significantly degrade the user experience (compared to memory 604, such as DRAM) due to storage device latency. Furthermore, using storage device 621 for virtual memory significantly reduces the usable lifespan of storage device 621.

[0062] Compared to virtual memory, virtual memory compression (e.g.) The kernel feature “ZRAM” uses a portion of memory as a compressed block storage device to avoid paging to storage device 621. Paging occurs within the compressed block until the data needs to be written to storage device 621. Virtual memory compression increases the available size of memory 604 while reducing wear and tear on storage device 621.

[0063] Storage devices optimized for mobile electronic devices or mobile storage devices typically include MMC solid-state storage devices (such as microSD cards). TM (e.g., cards, etc.) MMC devices contain several parallel interfaces (e.g., 8-bit parallel interfaces) with the host device and are typically components that can be removed and detached from the host device. In contrast, eMMC... TM The device, attached to the circuit board and considered a component of the host device, has comparable performance to that based on Serial ATA. TM The read speeds of SSD devices (Serial ATA (Advanced Technology) accessories or SATA) are still limited. However, the increasing demands for mobile device performance, such as fully realizing virtual or augmented reality devices and utilizing improved network speeds, have led to a shift in storage devices from parallel communication interfaces to serial communication interfaces. Universal Flash Storage (UFS) devices (including the controller and firmware) use a Low Voltage Differential Signaling (LVDS) serial interface with dedicated read / write paths to communicate with the host device, further enhancing read / write speeds.

[0064] Instruction 624 can further transmit or receive via a communication network 626 using a transmission medium through a network interface device 620 that utilizes any of several transmission protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Example communication networks may include Local Area Networks (LANs), Wide Area Networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), Simple Old-Style Telephone (POTS) networks, and wireless data networks (e.g., the IEEE 802.11 series of standards). ), IEEE 802.16 series standards (referred to as (e.g., IEEE 802.15.4 series standards, peer-to-peer (P2P) networks, etc.). In an example, network interface device 620 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connection to communication network 626. In an example, network interface device 620 may include multiple antennas for wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmission medium" should be considered as any intangible medium capable of storing, encoding, or transmitting instructions executed by machine 600, and includes digital or analog communication signals or other intangible media that facilitate such software communication.

[0065] Additional examples:

[0066] In Example 1, a method may include: receiving a memory access command from a host; determining whether an L2P area containing a first LBA received with the memory access command is in a mapped cache; in response to determining that the L2P area containing the LBA of the memory access command is not in the mapped cache, loading a plurality of L2P areas of an LBA-to-Physical Address (L2P) table from flash memory into the mapped cache; determining the physical address of the flash memory based on the first LBA in the mapped cache and the first L2P area among the plurality of L2P areas; and executing the memory access command.

[0067] In Example 2, the method according to Example 1 optionally includes: receiving a second memory access command; and determining that the second L2P area of ​​the mapped cache contains a second LBA received together with the second memory access command.

[0068] In Example 3, the method according to any one or more of Examples 1 to 2 optionally includes, after receiving the second memory access command, executing the second memory access command without first transferring a portion of the L2P table from the flash memory to the mapped cache.

[0069] In Example 4, receiving the memory access command according to any one or more of Examples 1 to 3 optionally includes determining that the memory access command is a sequential read command.

[0070] In Example 5, determining that the memory access command is a sequential read command according to any or more of Examples 1 to 4 optionally includes determining that the memory access command is a read command.

[0071] In Example 6, determining that the memory access command is a sequential read command according to any or more of Examples 1 to 5 optionally includes determining that a plurality of immediately preceding memory access commands are dedicated read commands.

[0072] In Example 7, determining that the memory access command is a sequential read command according to any one or more of Examples 1 to 6 optionally includes determining that the memory access command is a read command having a data block size equal to the maximum data block size.

[0073] In Example 8, determining that the memory access command is a sequential read command according to any or more of Examples 1 to 7 optionally includes determining that the sum of the starting LBA from the immediately preceding read command and the data block size of the immediately preceding read command points to the starting LBA of the memory access command.

[0074] In Example 9, the L2P area of ​​the L2P table described in any one or more of Examples 1 to 8 is optionally configured to map more than 1,000 LBAs to the corresponding physical addresses of the flash memory.

[0075] In Example 10, loading multiple L2P areas according to any one or more of Examples 1 to 9 optionally includes loading at least three L2P areas of the L2P table from the flash memory into the memory cache.

[0076] In Example 11, a memory device may include a memory array (e.g., a flash memory array) and a memory controller. The memory controller may be configured to receive commands from a host device. The memory controller may include a processing circuitry system comprising one or more processors and may be configured to perform operations including: receiving a memory access command from a host; determining whether an L2P region containing a first LBA received with the memory access command is in a mapped cache; in response to determining that the L2P region containing the LBA of the memory access command is not in the mapped cache, loading a plurality of L2P regions of an LBA-to-Physical Address (L2P) table from flash memory into the mapped cache; determining the physical address of the flash memory based on the first LBA in the mapped cache and the first L2P region among the plurality of L2P regions; and executing the memory access command.

[0077] In Example 12, the operation of the memory device according to any one or more of Examples 1 to 11 optionally includes: receiving a second memory access command; and determining that the second L2P area of ​​the mapped cache contains a second LBA received together with the second memory access command.

[0078] In Example 13, the operation of the memory device according to any one or more of Examples 1 to 12 optionally includes, after receiving the second memory access command, executing the second memory access command without first transferring a portion of the L2P table from the flash memory to the mapped cache.

[0079] In Example 14, the operation of the memory device according to any one or more of Examples 1 to 13 optionally includes determining that the memory access command is a sequential read command.

[0080] In Example 15, determining that the memory access command is a sequential read command according to any or more of Examples 1 to 14 optionally includes determining that the memory access command is a read command.

[0081] In Example 16, determining that the memory access command is a sequential read command according to any or more of Examples 1 to 15 optionally includes determining that a plurality of immediately preceding memory access commands are dedicated read commands.

[0082] In Example 17, determining that the memory access command is a sequential read command according to any or more of Examples 1 to 16 optionally includes determining that the memory access command is a read command having a data block size equal to the maximum data block size.

[0083] In Example 18, determining that the memory access command is a sequential read command according to any or more of Examples 1 to 17 optionally includes determining that the sum of the starting LBA from the immediately preceding read command and the data block size of the immediately preceding read command points to the starting LBA of the memory access command.

[0084] In Example 19, the L2P area of ​​the L2P table described according to any one or more of Examples 1 to 18 optionally includes corresponding physical addresses configured to map more than 1000 LBAs to the flash memory.

[0085] In Example 20, the operation of loading multiple L2P areas according to any one or more of Examples 1 to 19 optionally includes loading at least three L2P areas of the L2P table from the flash memory into the memory cache.

[0086] Example 21 is at least one machine-readable medium containing instructions that, when executed by a processing circuit system, cause the processing circuit system to perform any of the operations described in Examples 1 to 20.

[0087] Example 22 is a device that includes components for implementing any of Examples 1 to 20.

[0088] Example 23 is a system used according to any of Examples 1 through 20.

[0089] Example 24 is a method for implementing any of Examples 1 through 20.

[0090] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The drawings illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as “examples.” Such examples may include elements other than those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. Furthermore, the inventors also contemplate examples (or examples) of any combination or arrangement of those elements shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0091] In this invention, the term "a," commonly found in patent files, is used to include one or more, independent of any other examples or usages of "at least one" or "one or more." In this invention, the term "or" is used to refer to a non-exclusive "or," such that "A or B" can include "A but not B," "B but not A," and "A and B," unless otherwise indicated. In the appended claims, the terms "comprising" and "in which" are used as common English equivalents of the corresponding terms "including" and "wherein." Furthermore, in the appended claims, the terms "comprising" and "including" are open-ended, meaning that a system, apparatus, article, or process comprising elements other than those listed after this term in a claim is still considered to fall within the scope of the claim. Additionally, in the appended claims, the terms "first," "second," and "third," etc., are used merely as designations and are not intended to impose numerical requirements on their objects.

[0092] In various instances, the components, controllers, processors, units, engines, or tables described herein may include, in particular, physical circuitry systems or firmware stored on a physical device. As used herein, “processor” means any type of computing circuitry, such as (but not limited to) a microprocessor, microcontroller, graphics processor, digital signal processor (DSP), or any other type of processor or processing circuitry (including processors or groups of multi-core devices).

[0093] As used in this invention, the term "horizontal" is defined as a plane parallel to the conventional plane or surface of the substrate (e.g., a plane under the wafer or die), regardless of the actual orientation of the substrate at any point in time. The term "vertical" refers to a direction perpendicular to the horizontal as defined above. Prepositions (e.g., "on," "above," and "below") are defined relative to a conventional plane or surface as being on top of or on an exposed surface of the substrate, regardless of the orientation of the substrate; while "on" is intended to indicate direct contact of one structure with respect to another structure located "on" it (unless explicitly indicated otherwise); the terms "above" and "below" are intended to identify the relative placement of structures (or layers, features, etc.), which explicitly include (but are not limited to) direct contact between the identified structures, unless explicitly identified as such. Similarly, the terms "above" and "below" are not limited to horizontal orientation, because if at some point the structure is the outermost part of the construction in question, then it may be "above" a reference structure, even if this structure extends vertically relative to the reference structure rather than in a horizontal orientation.

[0094] The terms “wafer” and “substrate” are generally used herein to refer to any structure on which an integrated circuit is formed, and also to such structures during the various stages of integrated circuit manufacturing. Therefore, the following detailed description should not be considered as intended to be limiting, and the scope of the various embodiments is defined only by the full scope of the appended claims and their equivalents.

[0095] The present disclosure and the various embodiments described herein include a memory that utilizes memory cells (e.g., NAND memory cell strings) with a vertical structure. As used herein, directional adjectives will be considered relative to the surface of the substrate on which the memory cells are formed (i.e., a vertical structure will be considered as extending away from the substrate surface, the bottom end of the vertical structure will be considered as the end closest to the substrate surface and the top end of the vertical structure will be considered as the end furthest from the substrate surface).

[0096] As used herein, directional adjectives (e.g., horizontal, vertical, normal, parallel, perpendicular, etc.) may refer to relative orientation and are not intended to require strict adherence to specific geometric properties, unless otherwise stated. For example, as used herein, an upright structure does not need to be strictly perpendicular to the surface of the substrate, but may be substantially perpendicular to the surface of the substrate and may form an acute angle with the surface of the substrate (e.g., between 60 and 120 degrees, etc.).

[0097] In some embodiments described herein, different doping configurations may be applied to the source-side selected gate (SGS), control gate (CG), and drain-side selected gate (SGD), each of which in this example may be formed of or at least contain polysilicon, resulting in these layers (e.g., polysilicon, etc.) having different etch rates when exposed to an etch solution. For example, during the formation of a monolithic pillar in a 3D semiconductor device, SGS and CG may form recesses, while SGD may retain less or no recess. Therefore, these doping configurations can be selectively etched into dissimilar layers (e.g., SGS, CG, and SGD) in the 3D semiconductor device using an etch solution (e.g., tetramethylammonium hydroxide (TMCH)).

[0098] As used herein, operating a memory cell includes reading from a memory cell, writing to a memory cell, or erasing a memory cell. An operation that brings a memory cell to a desired state is referred to herein as “programming” and may include both writing to a memory cell and erasing from a memory cell (e.g., a memory cell may be programmed to an erased state).

[0099] According to one or more embodiments of this disclosure, a memory controller (e.g., processor, controller, firmware, etc.) located inside or outside the memory device can determine (e.g., select, set, adjust, calculate, change, clear, communicate, adapt, derive, define, utilize, modify, apply, etc.) a certain number of wear cycles or wear states (e.g., record wear cycles, count the operation of the memory device (when it occurs), end its operation when the memory device is started, evaluate the memory device characteristics corresponding to the wear states, etc.).

[0100] According to one or more embodiments of this disclosure, a memory access device may be configured to provide wear cycle information to the memory device for each memory operation. The memory device control circuitry (e.g., control logic) may be programmed to compensate for changes in memory device performance corresponding to the wear cycle information. The memory device may receive the wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.

[0101] It should be understood that when an element is referred to as "on another element," "connected to another element," or "coupled to another element," it may be directly on, directly connected to, or directly coupled to the other element, or there may be an intermediary element present. In contrast, when an element is referred to as "directly on another element," "directly connected to another element," or "directly coupled to another element," there is no intermediary element or layer. If two elements are shown in the diagram as being connected by a line, then the two elements may be coupled or directly coupled, unless otherwise indicated.

[0102] The methods described herein can be implemented, at least in part, by a machine or computer. Some examples may include computer-readable or machine-readable media encoded with instructions operable to configure electronic devices to perform the methods described in the examples above. Implementations of such methods may include code, such as microcode, assembly language code, high-level language code, or the like. This code may contain computer-readable instructions for performing various methods. The code may form part of a computer program product. Furthermore, the code may be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, for example, during execution or at other times. Examples of such tangible computer-readable media may include (but are not limited to) hard disks, removable disks, removable optical disks (e.g., optical discs and digital video disks), magnetic tapes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), solid-state drives (SSDs), universal flash storage (UFS) devices, embedded MMC (eMMC) devices, and the like.

[0103] The foregoing description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used by those skilled in the art after reviewing the foregoing description. It should be understood at the time of filing that it is not intended to interpret or limit the scope or meaning of the claims. Moreover, in the detailed description, various features may be grouped together to simplify this disclosure. This should not be interpreted as an intention that unclaimed features are essential to any claim. Rather, the invention may have not all features of a particular disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim is itself an individual embodiment, and such embodiments are contemplated to be combined or arranged in various ways. The scope of the invention should be determined with reference to the appended claims together with the full scope of the equivalents granted by these claims.

Claims

1. A method executed by a memory device, the method comprising: Receive a first memory access command from the host, the first memory access command being used to access the memory array of the memory device; It is determined that the first memory access command is a continuous read command; Determine whether the L2P area of ​​the LBA-to-physical address L2P cache contains the first LBA received along with the first memory access command. In response to determining that the first LBA of the first memory access command is not in the L2P cache and that the first memory access command is a sequential read command, a single load is performed to transfer multiple L2P areas of the L2P table from the memory array to the L2P cache. The first physical address of the memory array is determined based on the first LBA in the L2P cache and at least the first L2P region among the plurality of L2P regions. and The first memory access command is executed based on the first physical address.

2. The method according to claim 1, comprising: Receive second memory access commands; and It is determined that the L2P cache contains a second LBA received along with the second memory access command.

3. The method of claim 2, wherein after receiving the second memory access command, the second memory access command is executed without first transferring other areas of the L2P table from the memory array to the L2P cache.

4. The method of claim 1, wherein determining that the first memory access command is a sequential read command further comprises determining that a plurality of immediately preceding memory access commands are dedicated read commands.

5. The method of claim 1, wherein determining that the first memory access command is a sequential read command further comprises determining that the first memory access command is a read command having a data block size equal to the maximum data block size.

6. The method of claim 1, wherein determining that the first memory access command is a sequential read command further comprises determining that the sum of the starting LBA of the immediately preceding read command and the data block size of the immediately preceding read command extends to the starting LBA of the first memory access command.

7. The method of claim 1, wherein the memory device is a flash memory device and the memory array is a flash memory array, and wherein the L2P area of ​​the L2P table is configured to map more than 1000 LBAs to corresponding physical addresses of the flash memory array.

8. The method of claim 1, wherein loading the plurality of L2P areas comprises loading at least three L2P areas of the L2P table from the memory into the memory L2P cache.

9. The method of claim 1, wherein determining that the first memory access command is a sequential read command comprises: Determine whether the LBA of the immediately preceding read command plus the data block size of the immediately preceding read command is equal to the LBA of the first memory access command.

10. A memory device comprising: Memory array; and A memory controller configured to receive commands from a host device, the memory controller comprising a processing circuitry including one or more processors and configured to perform operations including: Receives a first memory access command from the host, the first memory access command being used to access the memory array of the memory device; It is determined that the first memory access command is a continuous read command; Determine whether the L2P area of ​​the LBA-to-physical address L2P cache contains the first LBA received along with the first memory access command. In response to determining that the L2P cache does not contain the first LBA of the first memory access command and that the first memory access command is a sequential read command, a single load is performed to transfer multiple L2P areas of the L2P table from the memory array to the L2P cache. The first physical address of the memory array is determined based on the first LBA in the L2P cache and the first L2P area in the plurality of L2P areas. and The first memory access command is executed at least in part based on the first physical address.

11. The memory device of claim 10, wherein the operation comprises: Receive second memory access commands; and It is determined that the second L2P area of ​​the L2P cache contains the second LBA received along with the second memory access command.

12. The memory device of claim 11, wherein the operation includes executing the second memory access command after receiving the second memory access command without first transferring other portions of the L2P table from the memory array to the L2P cache.

13. The memory device of claim 10, wherein determining that the first memory access command is a sequential read command includes determining that a plurality of immediately preceding memory access commands are dedicated read commands.

14. The memory device of claim 10, wherein determining that the first memory access command is a sequential read command includes determining that the first memory access command is a read command having a read data length equal to the maximum read data length.

15. The memory device of claim 10, wherein determining that the first memory access command is a sequential read command includes determining that the sum of the starting LBA from the immediately preceding read command and the length of the read data from the immediately preceding read command extends to the starting LBA of the first memory access command.

16. The memory device of claim 10, wherein the memory device is a flash memory device and the memory array is a flash memory array, and wherein the L2P area of ​​the L2P table is configured to map more than 1000 LBAs to corresponding physical addresses of the flash memory array.

17. The memory device of claim 10, wherein the operation of loading a plurality of L2P areas comprises loading at least three L2P areas of the L2P table from the memory array into the L2P cache.

18. The memory device of claim 10, wherein determining that the first memory access command is a sequential read command comprises: Determine whether the LBA of the immediately preceding read command plus the data block size of the immediately preceding read command is equal to the LBA of the first memory access command.

19. The memory device of claim 10, wherein determining that the first memory access command is a sequential read command comprises: The next memory access command that determines the selected number is a read command.

20. The memory device of claim 10, wherein executing the first memory access command based on the first physical address comprises: Multiple read commands are sent in batches to the memory array.

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