Power management based on detected voltage parameter levels in a memory subsystem

Abstract

A set of memory management operations is performed on a plurality of memory dies of a memory sub-system. Voltage parameter levels corresponding to the set of memory management operations are determined. Information representing voltage parameter levels and corresponding portions of the set of memory management operations is determined based on the set of voltage parameter levels. A request is received from a host system to perform a target portion of a memory management operation. First information corresponding to the target portion of the memory management operation is identified. A power management action is performed based on the first voltage parameter level.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to power management based on detected voltage parameter levels in memory subsystems. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Attached Figure Description

[0003] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0005] Figure 2 This is a flowchart of an example method for performing power management actions taking into account the voltage parameter levels of the memory die, according to some embodiments.

[0006] Figure 3 This describes an example system according to some embodiments, which includes a power management component configured to manage the power level of a memory die.

[0007] Figure 4 This describes an example power management component, according to some embodiments, configured to perform power management actions corresponding to a portion of an operation sequence based on voltage parameter levels.

[0008] Figure 5 This is a block diagram of an example computer system in which embodiments of this disclosure may operate. Detailed Implementation

[0009] This disclosure relates to power management based on detected voltage parameter levels in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a combination of both. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Typically, a host system may use a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0010] The memory subsystem can perform multiple parallel operations (e.g., random read, sequential read, random write, sequential write, etc.) involving multiple memory devices with multiple memory dies. To perform memory management operations (e.g., read operations, programming operations, erase operations, etc.), the memory subsystem can perform a corresponding set of sub-operations. For example, a read operation can be performed by measuring the threshold voltage of a memory cell and comparing it with a read voltage level to determine the stored data value. The parallel execution of multiple memory management operations involving multiple memory devices results in higher current consumption and higher peak power demands, negatively impacting the stability and reliability of data storage and data transmission. Furthermore, in real-world operating environments, many applications or host systems experience significant voltage parameter changes (e.g., voltage drop, voltage sag, etc.) due to the large peak current draw when multiple memory dies operate simultaneously.

[0011] To address the peak power issue arising from overlapping operations, conventional memory devices employ a peak power budget to set or limit the levels at which multiple multi-die memory devices can operate during concurrent operations. However, this approach leads to the establishment of a predefined peak power performance level, determined based on worst-case assumptions or simulations during the characterization phase, which reduces the overall system efficiency. Therefore, the controller in a conventional system is constrained by this predefined peak performance level and forced to limit the number of memory dies that can be active at a given time to perform parallel programming, erasing, and reading operations. Furthermore, predefined peak power levels and corresponding limits on the number of active memory dies are established for the memory subsystem in a manner independent of the actual host system and corresponding power delivery network design. However, the same peak current or power level can cause different host systems and power delivery network designs with different operating parameters (e.g., impedance, frequency domain, etc.) to produce different voltage parameters during operations (e.g., read, program, erase, etc.). Therefore, given the different host system requirements, conventional power management systems cannot be configured to account for these power consumption differences.

[0012] This disclosure addresses the above and other deficiencies through a memory subsystem that can distribute training command sequences to multiple memory dies within the memory subsystem. During this training phase, each memory die performs multiple memory management operations (e.g., read operations, programming operations, erase operations, power test operations) and determines voltage parameters (e.g., voltage drop, etc.) for corresponding portions of the memory management operations. For example, the set of memory management operations may include one or more of the following: read operations (e.g., a set of instructions that executes a set of sub-operations to perform a read operation), programming operations (e.g., a set of instructions that executes a set of sub-operations to perform a programming operation), erase operations (e.g., a set of instructions that executes a set of sub-operations to perform an erase operation), peak power simulation operations (e.g., a set of instructions that generates one or more peak power or peak current draw events), etc.

[0013] During the training phase, each target memory die performs a set of memory management operations to induce one or more peak current draw events (e.g., one or more instances of a memory die drawing a current level exceeding a peak current level threshold). Each of the peak current draw events is combined to determine a voltage parameter level (e.g., voltage drop value, voltage decrease value, etc.). Each voltage parameter level (e.g., voltage drop value) is associated with a corresponding portion of the set of memory management operations. The voltage parameter levels and information identifying the corresponding portion of the memory management operation that induces the voltage parameter level can be encoded (e.g., as tokens) and stored. In an embodiment, a set of tokens is generated and stored for each of the multiple memory dies, where each token represents the voltage parameter level associated with the peak current draw event and information identifying the corresponding portion (e.g., a memory management operation portion) of a command sequence that induces the voltage parameter level. The controller of the memory subsystem may continue to sequentially issue training command sequences to each memory die until all memory dies of the memory subsystem have completed the training phase.

[0014] During the training phase, the system can classify portions of a memory management operation (e.g., one or more sub-operations of a memory management operation) based on a risk level (e.g., high risk or low risk) that varies with the associated voltage parameter level. For example, power management component 113 can classify a portion of a memory management operation having a voltage parameter level exceeding a voltage parameter level threshold as high risk.

[0015] Following the training phase, the system manages the power level consumption of the memory dies during the execution of memory management operations initiated by the host system. To address the power issues caused by overlapping memory management operations performed by multiple memory dies in parallel, the system can read the tokens generated during the training phase and perform one or more power management actions (e.g., pausing the execution of memory management operations, delaying the execution of memory management operations, switching the memory dies to a low-power mode, etc.).

[0016] Advantageously, the system according to embodiments of this disclosure can determine voltage parameter levels during the training phase and, in conjunction with the execution of memory management operations initiated by the host system, use voltage parameter level information associated with peak current draw events to perform power management actions to manage the power consumed by the memory die. Furthermore, the in-system training phase can be performed for various host system designs and various power delivery networks. Therefore, the system according to embodiments of this disclosure performs power management actions taking into account the design and requirements of real or practical host systems. Given applicable power constraints, this increases throughput and optimizes the execution of operations.

[0017] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0018] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0019] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., a computer contained in a vehicle, industrial equipment or networked commercially available device), or such computing device that includes memory and processing means (e.g., a processor).

[0020] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, and magnetic connections.

[0021] Host system 120 may include a processor chipset and software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110 to, for example, write data to memory subsystem 110 and read data from memory subsystem 110.

[0022] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access memory components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0023] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0024] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and in-place write memory, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0025] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0026] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND flash memory (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0027] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include digital circuitry with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0028] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0029] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but instead may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0030] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to implement the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0031] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0032] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0033] The memory subsystem 110 includes a power management component 113 to manage a training phase during which a sequence of training commands is issued to multiple memory dies of the memory subsystem. In one embodiment, the training command sequence may be initiated or issued by a memory subsystem controller 115. In another embodiment, the power management component 113 monitors the execution of a set of memory management operations associated with the training command sequence on the target memory die. Each memory management operation may include a set of sub-operations or functions related to the execution of one or more tasks or operations (e.g., read operations, programming operations, erase operations, power test simulation operations, etc.). In yet another embodiment, the power management component 113 sends the training command sequence to each memory die until all memory dies have executed the set of memory management operations.

[0034] In an embodiment, power management component 113 determines voltage parameter levels (also referred to as "memory management operation portions") resulting from the execution of each portion of a memory management operation. In an embodiment, the voltage parameter level may be a voltage drop level (e.g., an output voltage loss experienced due to driving a load). A memory management operation portion may include one or more sub-operations (e.g., bit line precharge sub-operation, word line ramp sub-operation, etc.) performed in conjunction with the execution of a memory management operation (e.g., a read operation). In an embodiment, the detected voltage parameter level corresponding to each memory management operation portion is encoded to generate encoded information. The encoded information is stored in a log of memory subsystem 110 (e.g., an encoded information log stored in volatile memory (e.g., a RAM or SRAM storage location of controller 115) or non-volatile memory (e.g., a latch storage area of ​​memory device 130).

[0035] In an embodiment, power management component 113 identifies, encodes, and stores encoded information corresponding to peak current draw events (e.g., voltage parameter levels and information identifying an associated portion of a memory management operation) (e.g., an example where a memory die draws or consumes a current level exceeding a peak current draw level threshold). For each memory die, performing a set of memory management operations generates one or more peak current draw events. Power management component 113 identifies and encodes information identifying a portion of the memory management operation and the voltage parameter levels corresponding to the peak current draw events.

[0036] During the training phase, each memory die performs multiple memory management operations and determines the voltage parameters (e.g., voltage drop) corresponding to the respective memory management operation portion. The memory subsystem controller may continue to issue training command sequences sequentially to each memory die until all memory dies in the memory subsystem have completed the training phase.

[0037] Following the training phase, power management component 113 manages the power level consumption of multiple memory dies during the execution of memory management operations requested by host system 120. In response to a request to perform a portion of a memory management operation on a specific memory die, power management component 113 reads encoded information corresponding to the requested memory management operation portion and determines the associated voltage parameter level. Using the identified voltage parameter level, power management component 113 can perform power management actions relative to the requested memory management operation portion. Instance power management actions may include pausing or delaying the execution of the requested memory management operation portion, executing the requested memory management operation portion, switching the memory die to a low-power mode, etc.

[0038] In an embodiment, power management component 113 may determine the aggregate or total voltage parameter level in the current memory subsystem and determine whether the voltage parameter level associated with the requested memory management operation will cause the total voltage parameter level to exceed the total voltage parameter level threshold.

[0039] Figure 2 A flowchart of an example method 200 for identifying and establishing a desired peak power mode configuration for one or more memory dies to be simultaneously activated for performing one or more operations requested by a host system. Method 200 may be performed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 200 is performed by… Figure 1 The power management component 113 performs this. Additionally... Figure 3 The example memory subsystem controller 115 includes a power management component 113 configured to perform the operations of method 200. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0040] like Figure 2 As shown, at operation 210, the processing logic performs a set of memory management operations on multiple memory dies of the memory subsystem. In an embodiment, the set of memory management operations may include a set of instructions for performing the operations, such as read operations, programming operations, erase operations, power simulation operations, etc. In an embodiment, each corresponding memory die (e.g., Figure 3 The memory dies 1 to N in the memory dies perform a set of memory management operations, which causes power to be consumed (e.g., current to be drawn) from the power supply 350 of the respective memory dies to perform a corresponding part (e.g., one or more sub-operations) of each memory management operation.

[0041] In one embodiment, the processing logic executes commands for a set of memory management operations to be performed by a set of memory dies of the memory subsystem. In another embodiment, commands are initiated and executed during a training phase, during which each memory die of the memory device performs a set of memory management operations.

[0042] In one embodiment, the power management component 113 of the memory subsystem controller 115 may initiate a sequence of commands to enable execution on multiple memory dies (e.g., memory dies 1 through memory dies N). In another embodiment, the power management component 113 may issue each training command sequence to each of the memory dies (memory dies 1 through N) until all memory dies have performed a set of memory management operations. In yet another embodiment, the power management component 113 may issue a single training command sequence, which is sent to each of the memory dies for parallel execution of a set of memory management operations.

[0043] At operation 220, the processing logic determines a set of voltage parameter levels corresponding to the execution of a set of memory management operations. In an embodiment, the voltage parameter levels are detected in response to the execution of a corresponding portion of a set of memory management operations by each memory die in a set of memory dies. In an embodiment, the voltage parameter levels may be the voltage drop level of the memory die resulting from the execution of a portion of the memory management operation.

[0044] In an embodiment, such as Figure 3 As shown, a memory die may include one or more voltage detector components or circuits (e.g., voltage detectors 1 to X of memory die 1), each having a corresponding threshold voltage. Voltage detector detection can determine the voltage parameter level associated with the execution of each memory management operation section. In an embodiment, process logic determines the voltage parameter level corresponding to each peak current draw event associated with the memory die (e.g., an example where the execution of the memory management operation section produces a current draw level on the memory die that exceeds the peak current draw threshold level).

[0045] At operation 230, the processing logic determines the voltage parameter levels representing a set of memory management operations and the corresponding information based on a set of voltage parameter levels. In an embodiment, as... Figure 3As shown, an encoder (e.g., encoder 1 of memory die 1) generates encoded information representing the voltage parameter level associated with the execution of a corresponding memory management operation section. In an embodiment, the encoder generates a token containing encoded or token information and stores the encoded information in an encoded information log (e.g., encoded information log 1 storing encoded information associated with memory die 1, encoded information log N storing encoded information associated with memory die N). For example, a first token value 101 may be generated that encodes a first voltage parameter level associated with the execution of a word line ramp operation (e.g., a first memory management operation section), and a second token value 111 may be generated that encodes a second voltage parameter level associated with the execution of a bit line precharge operation (e.g., a second memory management operation section), etc. In an embodiment, the encoder generates encoded information containing the voltage parameter level corresponding to the corresponding memory management operation section. In an embodiment, the encoded information includes the voltage parameter level and the associated memory management operation section corresponding to the identified peak current draw event. In an embodiment, the encoded information log 1 may be the storage location of the memory die (e.g., the latch storage area of ​​the memory die) or the volatile memory of the memory subsystem controller 115 (e.g., RAM or SRAM memory).

[0046] In an embodiment, after the training phase is completed (e.g., a sequence of commands is executed by each memory die of the memory subsystem), the encoded information of each memory die is stored by and accessible by a power management component (e.g., power management component 1 to power management component N). In an embodiment, the power management component is part of power management component 113 and is configured to access an encoded information log to read the stored encoded information (e.g., stored tokens).

[0047] At operation 240, the processing logic receives from the host system a request to execute a target portion of a set of memory management operations. In an embodiment, the target portion refers to one or more sub-operations in a memory management operation that cause or generate one or more peak currents. The processing logic identifies the target portion (e.g., a high-risk portion) of the memory management operation associated with one or more peak current events for further processing, as described below.

[0048] In one embodiment, after the training phase is complete, the power management component 113 manages the peak power level of the memory subsystem during system execution of an operation request from the host system 120. In another embodiment, the host system 120 requests the execution of a memory management operation (e.g., a programming memory management operation), and the power management component 113 identifies the target portion of the memory management operation to be performed by a memory die from a set of memory dies.

[0049] At operation 250, the processing logic identifier corresponds to the first information of the target portion of the memory management operation. In an embodiment, the first information is stored encoded information representing the voltage parameter level resulting from the execution of the target portion of the memory management operation detected during the training phase. In an embodiment, power management component 113 executes a peak power management procedure to establish an optimized level of memory dies, which can be activated in parallel based on applicable peak power limits (also referred to as peak power budgets) and voltage parameter level thresholds (e.g., limitations of the memory subsystem or maximum permissible voltage parameter levels).

[0050] At operation 260, the processing logic performs a power management action based on the first voltage parameter level of the first information. In an embodiment, the power management action may include pausing or delaying the execution of the target portion of the memory management operation, enabling the memory die to execute the target portion of the memory management operation, and switching the memory die to a different power mode.

[0051] In an embodiment, the power management component 113 can place the memory die in one of a plurality of different power modes. For example, the memory die can be placed in a low-power mode by setting one or more parameters of the memory die to a first set of values ​​such that the resulting peak power level is lower than a threshold peak power level. The memory die can be placed in a medium-power mode by setting one or more parameters of the memory die to a second set of values ​​such that the resulting peak power level is equal to a threshold peak power level. The memory die can be placed in a high-power mode by setting one or more parameters of the memory die to a third set of values ​​such that the resulting peak power level is higher than a threshold peak power level.

[0052] In an embodiment, the power management component 113 can classify memory management operation portions based on a risk level (e.g., high risk or low risk) that varies with associated voltage parameter levels. For example, the power management component 113 can classify memory management operation portions having voltage parameter levels exceeding a voltage parameter level threshold as high risk. In an embodiment, considering that the associated first voltage parameter level exceeds the voltage parameter level threshold, the power management component 113 can identify a requested target portion of the memory management operation representing a high-risk portion. In an embodiment, a high-risk memory management operation portion is identified by determining that the voltage parameter level associated with the execution of the memory management operation portion exceeds the voltage parameter level threshold. In an embodiment, the power management component 113 can identify the voltage parameter level of the memory subsystem (e.g., the total voltage parameter level of the currently active memory die operating in a specific time frame) and determine whether the execution of the target portion of the memory management operation (as requested by the host system 120) will cause the updated total voltage parameter level (including the first voltage parameter level) to exceed the total voltage parameter level threshold. For example, power management component 113 may determine that a target portion of the memory die performing memory management operations at the current time will generate a total voltage parameter level exceeding a total voltage parameter level threshold. In response, power management component 113 may take appropriate power management actions to prevent the situation (e.g., the total voltage parameter level exceeding the voltage parameter level threshold), such as delaying the target portion of the memory die performing memory management operations or switching the memory die to a low-power mode.

[0053] In one embodiment, the power management component 113 may identify coded information associated with one or more memory management operations corresponding to a peak current draw event. In this embodiment, this coded information may be identified or encoded as a “high-risk” or flagged portion associated with a corresponding power management action (e.g., delaying or pausing execution or switching to a low-power mode).

[0054] like Figure 3 As shown, the encoding information (e.g., encoding information 1, encoding information N) can be shared by the power management module of the power management component 113 to identify the power management action in conjunction with the execution of the requested memory management operation section. Figure 4The description describes a power management component 113 that includes power management modules (e.g., power management modules 1, 2...N) that synchronize or share encoded information (e.g., encoded information 1, encoded information 2... encoded information N) determined during the training phase. In application (e.g., when a host system sends a memory management operation request to be executed by one or more memory dies), the power management component 113 can access the encoded information (e.g., a token set) to enable it to identify high-risk memory management operation portions (e.g., portions of memory management operations determined during the training phase to have voltage parameter levels exceeding a voltage parameter level threshold). For these high-risk memory management operation portions (e.g., those with the largest relative voltage drop), the power management component 113 can perform power management actions, such as delaying the execution of the high-risk memory management operation portion or switching the memory die to a low-power mode for executing the high-risk memory management operation portion.

[0055] Figure 5 This describes an example machine of computer system 500, within which an instruction set can be executed to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of the power management component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0056] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch or bridge, or non-digital circuit system, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying an action to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be considered to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0057] The example computer system 500 includes a processing device 502 that communicates with each other via a bus 530, a main memory 504 (e.g., read-only memory (ROM), flash memory, such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), dynamic random access memory (DRAM), static memory 506 (e.g., flash memory, static random access memory (SRAM)), and a data storage system 518.

[0058] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may also include a network interface device 508 for communication via network 520.

[0059] Data storage system 518 may include machine-readable storage medium 524 (also referred to as computer-readable medium) on which one or more instruction sets 526 or software embodying any one or more of the methods or functions described herein are stored. Instructions 526 may also reside wholly or at least partially within main memory 504 and / or processing device 502 during execution by computer system 500, which also constitute machine-readable storage medium. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0060] In one embodiment, instruction 526 includes implementing a data protection component (e.g., Figure 1 The power management component 113) contains functional instructions. Although machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" may include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0061] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0062] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0063] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0064] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0065] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0066] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments of the invention as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A method comprising: The processing unit performs a set of memory management operations on multiple memory dies of the memory subsystem; Determine a set of voltage parameter levels corresponding to the execution of the set of memory management operations; Based on the set of voltage parameter levels, determine the voltage parameter levels representing the set of memory management operations and the corresponding information; Receive a request from the host system for executing the target portion of the memory management operation in the set of memory management operations; The information identifies a first information corresponding to the target portion of the memory management operation, wherein the first information indicates a first voltage parameter level associated with the target portion of the memory management operation; The comparison between the first voltage parameter level and the voltage parameter level threshold of the first information is determined to meet the condition. as well as In response to the condition being met, a power management action is performed.

2. The method according to claim 1, further comprising: The voltage parameter level and the information identifying the corresponding part of the set of memory management operations are encoded to generate a token; as well as The token is stored in the log.

3. The method according to claim 1, further comprising: The target portion of the memory management operation is classified as a high-risk memory management operation portion.

4. The method of claim 3, wherein the power management action includes one of the following: delaying the execution of the high-risk memory management operation portion or switching the memory die to a low-power mode for executing the high-risk memory management operation portion.

5. The method of claim 1, wherein the set of memory management operations includes one or more of the following: read memory management operation, program memory management operation, erase memory management operation, or power analog memory management operation.

6. The method of claim 1, further comprising: Determine the total voltage parameter level associated with the plurality of memory dies; It is determined that the sum of the first voltage parameter level and the total voltage parameter level exceeds the total voltage parameter level threshold. as well as Performing the power management action includes one of the following: delaying the execution of the target portion of the memory management operation, or switching the memory die to a low-power mode for performing the target portion of the memory management operation.

7. The method of claim 1, wherein the voltage parameter level includes a voltage drop level.

8. A non-transitory computer-readable medium comprising instructions that, when executed by a processing means, cause the processing means to perform operations including: During the training phase, a set of memory management operations are performed on memory dies across multiple memory dies in the memory subsystem. Identify peak current draw events generated by executing the memory management operation portion of the set of memory management operations; Detect the voltage drop level corresponding to the peak current draw event; The storage includes a token representing the voltage drop level and information identifying the memory management operation section; The token is identified in response to a request from the host system for performing the memory management operation. as well as Power management actions are performed based on the voltage drop level.

9. The non-transitory computer-readable medium of claim 8, wherein the operation further comprises: The voltage drop level is compared with a threshold level to determine whether a condition is met, wherein the power management action is performed in response to the condition being met.

10. The non-transitory computer-readable medium of claim 8, wherein the power management action includes one of the following: delaying the execution of the memory management operation portion or switching the memory die to a low-power mode.

11. The non-transitory computer-readable medium of claim 8, wherein the voltage drop level is detected using one or more voltage detectors.

12. The non-transitory computer-readable medium of claim 8, wherein the token is stored in a storage location of the controller of the memory subsystem.

13. The non-transitory computer-readable medium of claim 8, wherein the set of memory management operations are performed on the plurality of memory dies of the memory subsystem during the training phase.

14. A system comprising: Memory devices; as well as A processing device operatively coupled to the memory device to perform operations including: Initiating commands used to perform a set of memory management operations by multiple memory dies of the memory subsystem; Perform the set of memory management operations on each of the plurality of memory dies; Determine a set of voltage parameter levels corresponding to the execution of the set of memory management operations; Based on the set of voltage parameter levels, determine the voltage parameter levels representing the set of memory management operations and the corresponding information; Receive a request from the host system for the target portion to perform memory management operations; The information identifies a first information corresponding to the target portion of the memory management operation, wherein the first information indicates a first voltage parameter level associated with the target portion of the memory management operation; The comparison between the first voltage parameter level and the voltage parameter level threshold of the first information is determined to meet the condition. as well as In response to the condition being met, a power management action is performed.

15. The system of claim 14, wherein the operation further comprises: The voltage parameter level and the information identifying the corresponding part of the set of memory management operations are encoded to generate a token; as well as The token is stored in the log.

16. The system of claim 14, wherein the operation further comprises: The target portion of the memory management operation is classified as a high-risk memory management operation portion.

17. The system of claim 16, wherein the power management action includes one of the following: delaying the execution of the high-risk memory management operation portion or switching the memory die to a low-power mode for executing the high-risk memory management operation portion.

18. The system of claim 14, wherein the set of memory management operations includes one or more of the following: a read memory management operation, a program memory management operation, an erase memory management operation, or a power analog memory management operation.

19. The system of claim 14, wherein the voltage parameter level includes a voltage drop level.

20. The system of claim 14, wherein the operation further comprises: Determine the total voltage parameter level associated with the plurality of memory dies; It is determined that the sum of the first voltage parameter level and the total voltage parameter level exceeds the total voltage parameter level threshold. as well as Performing the power management action includes one of the following: delaying the execution of the target portion of the memory management operation, or switching the memory die to a low-power mode for performing the target portion of the memory management operation.

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