Method for forming a conductive tube between adjacent features and integrated assembly having a conductive tube between adjacent features

Abstract

Some embodiments include an integrated assembly having a pair of substantially parallel features separated from each other by an intervening space. A conductive tube is between the features and substantially parallel to the features. The conductive tube may be formed within a conduit. The conduit may be created by depositing an insulating material between the features in such a manner that a top region of the insulating material is pinched off so that the conduit is a void region below the pinched-off top region.

Description

Technical Field

[0001] Integrated assembly and method of forming the integrated assembly. Method of forming a conductive tube between adjacent features. Integrated assembly with a conductive tube between adjacent features. Background Art

[0002] Patterned features are often used in integrated assemblies. In some example applications, patterned features may be conductive features used as interconnects and / or to introduce suitable voltages (e.g., VDD, VSS, etc.) to an integrated circuit. Fabricating patterned features becomes increasingly difficult with increasing levels of integration due to the tight pitch available for patterned features. It will be necessary to develop new methods for forming patterned features and to develop new architectures that utilize patterned features. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figures 1 to 1B A view of the zone that integrates the assembly for the instance. Figure 1 For along Figure 1A and 1B Schematic top view of cross section 1-1. Figure 1A and 1B Along the Figure 1 Diagrammatic cross-sectional side view of lines AA and BB.

[0004] Figures 2 to 5 A view of a region of an instance integration assembly at a sequential processing stage of an instance method. Figures 2 to 5 It is a top view for illustration. Figures 2A to 5A Along the Figures 2 to 5 Diagrammatic cross-sectional side view of line AA.

[0005] Figure 6 is a diagrammatic cross-sectional side view of a region of an example integrated assembly.

[0006] Figures 7 to 9 is a diagrammatic cross-sectional side view of a region of an example integrated assembly at sequential processing stages of an example method.

[0007] Figures 10 to 13 A view of the sequential processing phases of the instance methods for the instance integration assembly. Figures 10 to 13 It is a top view for illustration. Figures 10A to 13A Along the Figures 10 to 13 Diagrammatic cross-sectional side view of line AA. Figures 10B to 12B Along the Figures 10 to 12 Diagrammatic cross-sectional side view of line BB.

[0008] Figures 14 to 16 A diagrammatic top view of regions of an example integrated assembly at sequential processing stages of an example method.

[0009] Figures 17 to 20 A diagrammatic top view of regions of an example integrated assembly at sequential processing stages of an example method.

[0010] Figures 21 to 21B A view of the zone that integrates the assembly for the instance. Fig.21 For along Fig.21A and 21B Diagrammatic cross-sectional top view of line CC. Fig.21A and 21B Along the Fig.21 Diagrammatic cross-sectional side view of lines AA and BB.

[0011] 22A is a diagrammatic top view of a region of an example prior art integrated circuit.

[0012] 22B is a schematic diagram of the example prior art integrated circuit of FIG. 22A .

[0013] Fig.23A is a diagrammatic top view of a region of an example embodiment integrated circuit that may include the prior art arrangement of FIG. 22B .

[0014] FIG. 23B is a repetition of the schematic diagram of FIG. 22B .

[0015] Fig.24 A diagrammatic cross-sectional top view of an example integrated assembly.

[0016] Fig.25 A diagrammatic cross-sectional top view of an example integrated assembly. DETAILED DESCRIPTION

[0017] Some embodiments include methods of forming a conductive tube (linear structure) between features of an integrated assembly. Some embodiments include an integrated assembly including a conductive tube. Some embodiments include logic circuits (e.g., 2NFET, 2PFET circuits; where NFET refers to a field effect transistor with n-type source / drain regions, and PFET refers to a field effect transistor with p-type source / drain regions). Reference Figures 1 to 25 Example embodiments are described.

[0018] refer to Figures 1 to 1B , the integrated assembly 10 includes a pair of features 12 and 14. The features are shown as linear structures, wherein such linear structures extend along a first direction corresponding to the x-axis direction shown. The linear features may be straight (as shown), wavy, curved, etc., and are substantially parallel to each other. The term "substantially parallel" means parallel within reasonable manufacturing and measurement tolerances.

[0019] Features 12 and 14 may be supported by an underlying semiconductor substrate (not shown). The substrate may include a semiconductor material; and may, for example, include, consist essentially of, or consist of single crystal silicon. The substrate may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any structure including semiconductor material, including but not limited to bulk semiconductor material, such as a semiconductor wafer (alone or in an assembly including other materials) and a layer of semiconductor material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrate described above. In some applications, the substrate may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.

[0020] Features 12 and 14 are separated from each other by an intervening space 16. In the illustrated embodiment, space 16 has approximately the same width W along the illustrated y-axis as features 12 and 14. Thus, features 12 and 14 may be considered to be formed along (on) pitch P, with the width of space 16 being approximately ½P.

[0021] Features 12 and 14 include material 18. Material 18 may include any suitable composition. Although material 18 is shown as being homogeneous, in other embodiments, material 18 may be heterogeneous and may include two or more discrete compositions. Furthermore, although features 12 and 14 are shown as including the same material 18 as one another, in other embodiments, the features may include different compositions relative to one another.

[0022] Material 18 may be conductive, insulating, semiconductive, etc. If material 18 comprises two or more discrete compositions, such compositions may have different conductivities relative to each other. For example, in some embodiments, one of the compositions may be conductive while another is insulating, etc.

[0023] Conductive tube (structure, feature, line, etc.) 20 is in space 16. Conductive tube 20 is in Figure 1 It is shown with a dashed (phantom) line to indicate that it is underneath other material.

[0024] The conductive tube includes a conductive material 22. The conductive material 22 may include any suitable conductive composition, such as one or more of the following: various metals (e.g., titanium, tungsten, tantalum, cobalt, molybdenum, nickel, platinum, ruthenium, copper, aluminum, palladium, silver, gold, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, the conductive material 22 may include, consist essentially of, or consist of one or more of the following: metal nitrides, metal carbides, metal silicides, and metal borides. In some embodiments, the conductive material 22 may include a tungsten core laterally surrounded by a layer including titanium nitride.

[0025] Conductive tube 20 is substantially parallel to features 12 and 14 and in the embodiment shown is approximately halfway within intervening space 16 between features 12 and 14 .

[0026] A first conductive post (brick, structure, etc.) 24 is along one side of tube 20, and a second conductive post (brick, structure, etc.) 26 is along an opposing second side of tube 20. Posts 20 and 24 comprise the same composition 22 as tube 20.

[0027] First dielectric material 28 is within intervening space 16, beneath conductive tube 20, and along the sidewalls of features 12 and 14. First dielectric material 28 may comprise any suitable composition, and in some embodiments may comprise, consist essentially of, or consist of one or more of silicon nitride, silicon dioxide, aluminum oxide, hafnium oxide, tantalum oxide, etc.

[0028] The second dielectric material 30 is within the intervening space 16 and above the first dielectric material 28. The second dielectric material 30 is above and below the conductive tube 20, and in the embodiment shown, also along the sidewalls of the conductive tube 20. The second dielectric material 30 may be less dense than the first dielectric material 28. The second dielectric material 30 may include any suitable composition, and in some embodiments, may include, consist essentially of, or consist of one or more of silicon nitride, silicon dioxide, porous silicon dioxide, carbon-doped silicon oxide, boron-doped silicon dioxide, silicon oxynitride, and the like.

[0029] In some embodiments, both first dielectric material 28 and second dielectric material 30 may include silicon nitride, wherein the density of second dielectric material 30 is less than that of the first dielectric material. In some embodiments, both first dielectric material 28 and second dielectric material 30 may include silicon dioxide, wherein the density of the second dielectric material is less than that of the first dielectric material. In some embodiments, first dielectric material 28 may include silicon nitride, and second dielectric material 30 may include silicon dioxide. In some embodiments, first dielectric material 28 may include silicon nitride, and second dielectric material 30 may include silicon oxynitride.

[0030] A third dielectric material 32 is above the second dielectric material 30. The third dielectric material can be denser than the second dielectric material 30, and can include any of the compositions described above as suitable for the first dielectric material 28. The first dielectric material 28 and the third dielectric material 32 can include the same composition as one another, or can include different compositions relative to one another.

[0031] In the embodiment shown, planarized surface 33 extends across second dielectric material 30 and third dielectric material 32. Planarized surface 33 is separated from upper surfaces 17 of features 12 and 14 by at least second dielectric material 30, and in the embodiment shown by both second dielectric material 30 and first dielectric material 28.

[0032] Figures 1 to 1B An advantage of the configuration is that features 12 and 14 can be formed on a very tight pitch P (e.g., a pitch corresponding to the minimum pitch achievable by a manufacturing process), and tube 20 can be formed in the spaces between these features. Thus, conductive tube 20 can be packaged in tight spaces of an integrated assembly, and conductive interconnects can be provided in such tight spaces.

[0033] Figures 1 to 1B The assembly may be formed by any suitable process. Figures 2 to 5 Describes instance processing.

[0034] refer to Figure 2 and 2A , assembly 10 is shown including features 12 and 14 as fins extending upwardly from pillar 34 of material 18. In some embodiments, Figure 2 and 2AThe material 18 may be a semiconductor material. The semiconductor material may include any suitable composition; and in some embodiments may include, consist essentially of, or consist of one or more of the following: silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; wherein the term III / V semiconductor material refers to a semiconductor material including elements selected from Group III and Group V of the periodic table (wherein Group III and Group V are old nomenclature and are now referred to as Group 13 and Group 15). In some embodiments, Figure 2 and 2A The semiconductor material 18 may include, consist essentially of, or consist of silicon. The silicon may be in any suitable crystalline form (eg, single crystal, polycrystalline, amorphous, etc.).

[0035] Fin 12 and fin 14 may be referred to as a first fin and a second fin, respectively. In embodiments where material 18 is a semiconductor material, the fins may have regions of any suitable conductivity type. For example, in some embodiments, fin 12 and fin 14 may include regions that are p-type (e.g., may include regions having silicon conductively doped with boron), and / or may include regions that are n-type (e.g., may include regions having silicon conductively doped with one or both of phosphorus and arsenic). In some embodiments, fin 12 may include a first region having a first conductivity type, and fin 14 may include a second region having a second conductivity type, wherein the second conductivity type is different from the first conductivity type (e.g., one of the first conductivity type and the second conductivity type may be p-type and the other is n-type).

[0036] The fins 12 and 14 (ie, the first features 12 and the second features 14 ) are separated from each other by intervening spaces 16 and extend substantially parallel to each other along the illustrated x-axis direction.

[0037] refer to Figure 3 and 3A , dielectric material 28 is formed within intervening space 16. In the illustrated embodiment, dielectric material 28 conformally extends along the outer surfaces of features 12 and 14 and narrows intervening space 16. Dielectric material 28 may be referred to as a first dielectric material.

[0038] The second dielectric material 30 is formed over the first dielectric material 28 and within the space 16 narrowed by the first dielectric material. The second dielectric material 30 may have a lower density than the first dielectric material 28, and therefore, voids 36 may be created within the material 30 during deposition of the material 30. In particular, a top region 37 of the second material 30 may pinch off at the top of the intervening space 16 to prevent the material 30 from completely filling the space, and thereby creating voids 36.

[0039] In the embodiment shown, the gap 36 corresponds to the pipeline (as shown in FIG. Figure 3 ), wherein such conduits extend substantially parallel to the first feature 12 and the second feature 14. The conduits 36 and the features 12 and 14 are Figure 3 The figure is shown in dashed view to indicate that the pipes and features are beneath other material.

[0040] The conduit 36 ​​has a first end 39 and an opposite second end 41 .

[0041] The third dielectric material 32 is formed over the second dielectric material 30. The density of the third dielectric material 32 may be greater than that of the second dielectric material 30. In some embodiments, the third dielectric material 32 may be tailored to effectively seal voids within the second dielectric material 30. For example, the third dielectric material 32 may be provided to have high conformality such that it may effectively seal voids 32 in the second dielectric material 30 to the extent that additional sealing is needed or desired.

[0042] In some embodiments, dielectric materials 28, 30, and 32 may all include the same composition (e.g., silicon dioxide or silicon nitride), but deposition conditions may be varied so that intermediate dielectric material 30 has a lower density than upper dielectric material 28 and lower dielectric material 32. In some embodiments, intermediate dielectric material 30 may include a different composition than upper dielectric material 28 and lower dielectric material 32. For example, both upper dielectric material 28 and lower dielectric material 32 may include silicon nitride, while the intermediate dielectric material includes silicon dioxide. Alternatively, both upper dielectric material 28 and lower dielectric material 32 may include silicon dioxide, while the intermediate dielectric material includes silicon nitride. As another example, both upper dielectric material 28 and lower dielectric material 32 may include silicon nitride, while intermediate dielectric material 30 includes silicon oxynitride.

[0043] In some embodiments, the density of the intermediary dielectric material 30 can be affected by incorporating one or more dopants (and / or other additives) into the material. For example, the intermediary dielectric material 30 can include carbon-doped silicon dioxide, boron-doped silicon dioxide, etc.

[0044] Upper dielectric material 28 and lower dielectric material 32 may include the same composition as one another, or may include different compositions relative to one another.

[0045] Dielectric materials 28 , 30 , and 32 may be formed by any suitable process, including, for example, atomic layer deposition (ALD) and / or chemical vapor deposition (CVD), among others.

[0046] In some embodiments, one or both of dielectric material 28 and dielectric material 32 may be omitted.

[0047] Figure 3A The planarized surface 33 is shown extending across the third dielectric material 32. In other embodiments, the planarized surface 33 may be formed to extend across regions of both the third dielectric material 32 and the second dielectric material 30, such as Figure 1A as shown in .

[0048] refer to Figure 4 and 4A , openings 38 are formed along ends 39 and 41 of tubing 36. The openings may be used to allow access to ends 39 and 41 of tubing 36. Although the openings are shown as being formed along both opposing ends 39 and 41 of tubing 36, in other embodiments, the openings are formed along only one of the ends of the tubing.

[0049] refer to Figure 5 and 5A , the conductive material 22 is formed in the openings 38 and flows into the conduit 36 ​​through such openings. In the illustrated embodiment, the conductive material 22 fills the conduit 36 ​​to form the conductive material 22 described above. Figures 1 to 1B The conductive tube 20. The material 22 may include the above-mentioned Figures 1 to 1B Any of the compositions described. Material 22 may be formed by any suitable process, including, for example, one or more of ALD, CVD, and physical vapor deposition (PVD).

[0050] In some embodiments, material 22 may include one or more metals and / or metal-containing compositions. For example, in some embodiments, material 22 may include a liner of a metal nitride (e.g., titanium nitride, tungsten nitride, etc.) that lines conduit 36, and may include a metal core material within the lined conduit. The metal core material may, for example, include, consist essentially of, or consist of tungsten, titanium, etc.

[0051] In some embodiments, forming conductive material 22 within conduit 36 ​​may be considered a method for patterning conductive tube 20 within region 16 between features 12 and 14. Conductive tube 20 is shown to be substantially parallel to first feature 12 and second feature 14.

[0052] Although the dielectric materials 28, 30 and 32 are Figures 1 to 5 In the embodiments of , one or more of such other materials may comprise a laminate of two or more compositions. For example, Figure 6 In an example embodiment of a laminate in which dielectric material 28 and dielectric material 30 each include two or more compositions, in a similar Figure 5A1 and 14. The dielectric material 28 is a laminate of compositions 28a, 28b, and 28c, and the dielectric material 30 is a laminate of compositions 30a and 30b. The laminate may include abrupt boundaries between adjacent compositions and / or may include a gradient between adjacent compositions.

[0053] An advantage of utilizing a laminate configuration for one or more of the dielectric materials may be that this may enable the dielectric material to be customized for a particular application. For example, a laminate configuration of dielectric material 30 may enable the cross-sectional shape of voids 36 to be customized for a particular application.

[0054] Compositions 28a - c may include any of the substances described above as suitable for dielectric material 28 , and compositions 30a and 30b may include any of the substances described above as suitable for dielectric material 30 .

[0055] In some embodiments, one or more etchants may flow through opening 38 ( Figure 4 ) and enters the pipe 36 to form the conductive material 22 ( Figure 5 ) before widening the pipeline. For example, Figure 7 Shown in Figure 4 and 4A 1 and 12. An enlarged view of the space 16 between features 12 and 14 at a processing stage of FIG. Figure 8 Shown in Figure 7 and showing the pipe 36 passing through the opening 38 ( Figure 4 ) One or more etchants flowing into the pipeline widens. If the dielectric material 30 includes silicon dioxide, the etchant may include hydrochloric acid. If the dielectric material 30 includes silicon nitride, the etchant may include phosphoric acid.

[0056] The original position of the pipe 36 is Figure 8 The dashed line 43 is shown in the figure so that the reader can easily understand that the pipeline 36 is already Figure 8 The processing stage is relative to Figure 7 The processing stage is widened.

[0057] refer to Fig. 9 , the conductive material 22 is formed in the widened pipe 36 to form the above reference Figure 5 A conductive tube 20 of the type described.

[0058] Figures 2 to 5The embodiment of FIG. 1 shows dielectric materials 28, 30, and 32 formed along the entire length of the space 16 between features 12 and 14. In other embodiments, dielectric material may be formed only along sections of such a space so that the resulting conduit 36 ​​only extends along sections of the space, rather than the full length of the space. Figures 10 to 13 Examples of these other embodiments are described.

[0059] refer to Figures 10 to 10B , the assembly 10 is similar to Figure 3 and 3A 14, except that the space 16 between features 12 and 14 is subdivided among three sections 44, 46 and 48. Sections 44 and 48 include the above reference Figure 3 and 3A The dielectric materials 28, 30 and 32.

[0060] Section 46 includes dielectric materials 40 and 42. Dielectric materials 40 and 42 may include any suitable composition. In some embodiments, dielectric material 40 may be the same as dielectric material 28, and dielectric material 42 may be the same as dielectric material 32. In some embodiments, dielectric materials 40 and 42 may be replaced by a single dielectric material.

[0061] The less dense (soft) material 30 from the section 46 , and therefore, no voids 36 are formed along the section 46 . Fig.10 The configuration of can be viewed as having sections 44 and 48 corresponding to a first zone 50 of the intervening space 16, and having section 46 corresponding to a second zone 52 of the intervening space. The conduit 36 ​​extends across the first zone 50 of the intervening space 16, but does not extend across the second zone 52 of the intervening space. In some items, the conduit 36 ​​within section 44 of the intervening space 16 can be referred to as a first conduit 51, and the conduit within the third section 48 can be referred to as a second conduit 53.

[0062] refer to Figures 11 to 11B , by similar means to the above reference Figure 4 and 4A The process described forms the opening 38 .

[0063] refer to Figures 12 to 12B , by similar means to the above reference Figure 5 and 5A The process described forms conductive material 22 within openings 38 and conduits 51 and 53 .

[0064] The conductive material 22 in the tube 51 forms a first conductive tube 20 a , and the conductive material 22 in the tube 53 forms a second conductive tube 20 b .

[0065] The conductive material 22 in the opening 38 forms the Figure 1 Blocks (pillars) 24 and 26 of the type described.

[0066] In some embodiments, features 12 and 14 may be considered to extend a first distance D1 along the x-axis direction, and tubes 20a and 20b may each be considered to extend a second distance D2 along the x-axis direction; wherein the second distance is less than the first distance. In the embodiment shown, second distance D2 is less than half of first distance D1. In the embodiment shown, tubes 20a and 20b extend about the same distance as each other (i.e., are about the same length as each other). In other embodiments, tube 20a may be a different length than tube 20b.

[0067] In the illustrated embodiment, the first conductive tube 20a and the second conductive tube 20b are separated from each other by an intervening gap corresponding to the segment 46. The intervening gap 46 can be considered as an insulating region 46 between the first conductive tube 20a and the second conductive tube 20b. The tube 20a can be considered to have a first terminal end 55a on one side of the insulating region 46, and the tube 20b can be considered to have a second terminal end 55b on an opposite second side of the insulating region 46.

[0068] In some embodiments, the conductive interconnects may be formed to extend downward to one or both of the terminal ends 55a and 55b. Fig.13 and 13A An electrical interconnect 54 is shown extending downwardly through the insulating materials 28, 30 and 32 to electrically couple with the terminal ends 55a and 55b of the conductive tubes 20a and 20b.

[0069] Electrical interconnect 54 may include any suitable conductive composition, such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, electrical interconnect 54 may include conductive material 22 (i.e., the same conductive material as utilized in blocks 24 and 26 and as utilized in tubes 20a and 20b).

[0070] Electrical interconnect 54 may be coupled with other circuitry (not shown). Such other circuitry may be at any suitable height level, and in some embodiments may be at a height level higher than features 12 and 14.

[0071] In some embodiments, features 12 and 14 may include segments separated by intervening gaps, and it may be desirable to form conductive structures that are continuous across such intervening gaps. Figures 14 to 20 The method described in can be used to manufacture such conductive structures.

[0072] refer to Fig.14, construction 10 includes a configuration in which feature 12 includes a pair of segments 12a and 12b and in which feature 14 includes a pair of segments 14a and 14b. Segments 12a and 14a are separated from segments 12b and 14b by an intervening gap 56.

[0073] refer to Fig.15 , the conductive tubes 20a and 20b are similar to the above reference Figures 2 to 5 The process described is formed between features 12 and 14. Specifically, conductive tube 20a is formed between features 12a and 14a, and conductive tube 20b is formed between features 12b and 14b. Insulating material 32 is shown extending across features 12a, 12b, 14a, and 14b, and in a manner similar to Figure 5 and 5A The configuration of the configuration extends across the tubes 20a and 20b. The tubes 20a and 20b are separated from each other by an intervening gap 56.

[0074] 16, conductive material 58 is formed within intervening gap 56 and is patterned to conductively couple first conductive tube 20a to second conductive tube 20b. In some embodiments, conductive material 58 can be viewed as a feature (structure) 59 patterned to bridge across gap 56 to electrically couple first conductive tube 20a and second conductive tube 20b to each other.

[0075] Conductive material 58 may include any suitable conductive composition, such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, conductive material 58 may include the same composition as conductive material 22, and in other embodiments, conductive material 58 may include a different composition than conductive material 22.

[0076] refer to Fig.17 , in a similar Figure 2 Assembly 10 is shown at a processing stage of FIG. 1 , wherein features 12 and 14 extend along the x-axis direction.

[0077] refer to Fig.18 , by similar means to the above reference Figure 3 and 3A The above-mentioned treatment process forms a pipeline 36.

[0078] refer to Fig.19, the patterned cutting subdivides feature 12 into first structure 12a and second structure 12b, subdivides feature 14 into first structure 14a and second structure 14b, and subdivides conduit 36 ​​into first structure 36a and second structure 36b. Intervening gap 56 is thus formed to extend between the first structure (12a, 14a and 36a) and the second structure (12b, 14b and 36b).

[0079] refer to Fig. 20 , a bridge structure 59 is formed to extend across the intervening gap 56 and couple the first tube 36a with the second tube 36b. The bridge structure 59 includes a conductive material 58, and such conductive material can flow into the tubes 36a and 36b to form tubes 20a and 20b extending outward from the bridge structure 59. In some embodiments, the conductive material 58 includes both a metal nitride (e.g., titanium nitride, tungsten nitride, etc.) and a relatively pure metal (e.g., tungsten). The metal nitride can flow into the tubes 36a and 36b to line the tubes, and then the relatively pure metal can flow into the lined tubes to form a metal core surrounded by a metal nitride liner.

[0080] In some embodiments, the structures described above may be incorporated into Figures 21 to 21B The integrated circuit described.

[0081] Figures 21 to 21B The assembly 10 of FIG. 1 includes features 12 and 14 configured as fins of semiconductor material 18, wherein such fins extend upwardly from a column 34 of semiconductor material. Spots are provided within the semiconductor material 18 to assist the reader in identifying the semiconductor material.

[0082] Semiconductor material 18 may include any suitable composition; and in some embodiments may include, consist essentially of, or consist of one or more of silicon, germanium, a Group III / V semiconductor material (e.g., gallium phosphide), a semiconductor oxide, etc.; wherein the term Group III / V semiconductor material refers to a semiconductor material including elements selected from Group III and Group V of the periodic table (wherein Group III and Group V are old nomenclature and are now referred to as Groups 13 and 15). For example, in some embodiments, semiconductor material 18 may include, consist essentially of, or consist of silicon. The silicon may be in any suitable crystalline form, and in some embodiments may correspond to single crystal silicon.

[0083] The fin 12 is shown to include a p-type source / drain region S / D. The p-type region of the fin 12 may include a layer doped with boron to at least about 10 20 atoms / cm3 concentration of silicon.

[0084] The fin 14 is shown to include n-type source / drain regions S / D. The n-type region of the fin 14 may include a ferroelectric element doped with one or both of phosphorus and arsenic to at least about 10 20 atoms / cm3 of total concentration of silicon.

[0085] The source / drain region S / D along the first fin 12 may be referred to as a first source / drain region, and the source / drain region S / D along the second fin 14 may be referred to as a second source / drain region.

[0086] Gating structures 60a and 60b extend across fins 12 and 14, wherein the gating structures extend along the y-axis direction as shown. One of gating structures 60a and 60b may be referred to as a first gating structure, and the other may be referred to as a second gating structure.

[0087] The gate structure includes a conductive gate material 62a-c. The gate material 62a-c may include any suitable conductive composition; for example, one or more of the following: various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, two or more of the gate materials 62a-c may be compositionally identical to one another, and in other embodiments, two or more of the gate materials may be compositionally different from one another.

[0088] Insulating material (gate dielectric material) 62 is along the outer surfaces of fins 12 and 14. Insulating material 62 may include any suitable composition, and in some embodiments, may include one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, hafnium oxide, and the like.

[0089] Fin 12 includes channel regions 64a and 64b between the source / drain regions S / D shown along such fins, and fin 14 includes channel regions 66a and 66b between the source / drain regions S / D shown along such fins. Channel regions 64a and 66a are operatively close to gate structure 60a, and channel regions 64b and 66b are operatively close to gate structure 60b. The term "operatively close" means that the gate structure is appropriately close to the channel region so that an electric field can be selectively induced on the channel region by electrical activation / deactivation of the gate structure. Selective induction of an electric field on the channel region can be used to achieve controlled coupling / decoupling of the source / drain S / D on opposite sides of the channel region.

[0090] Channel regions 64 and 66 may be appropriately doped to achieve a desired threshold voltage.

[0091] Similar to Figures 21 to 21B The circuit of the circuit can be used in a logic device.

[0092] 22A and 22B illustrate an example prior art logic device that includes two NFET devices 68a and 68b (labeled transistors T1 and T2) and two PFET devices 70a and 70b (labeled transistors T3 and T4). The device shown also includes a capacitor 69.

[0093] FIG. 22B is a schematic illustration of a prior art device, and FIG. 22A is a diagrammatic illustration of a region of a semiconductor assembly 72 that includes the device.

[0094] The diagram of Figure 22A shows that the assembly can be considered to include six tracks (labeled Tracks 1 to 6). The tracks are on pitch P1, which can be the minimum lithographic pitch of the manufacturing process. The outer tracks (Track 1 and Track 6) include conductive structures (power lines, wires) 74 and 76 that provide VDD and VSS to the device (i.e., they are coupled to reference nodes at VDD and VSS).

[0095] In some embodiments, the Figures 1 to 21 22A and 22B to achieve a higher level of integration than the prior art device of FIG. 22A .

[0096] Fig.23A Assembly 10 is shown including an example logic cell 78 having two NFET transistors 68a and 68b and two PFET transistors 70a and 70b. Logic cell 78 may be referred to as a dual NFET dual PFET device.

[0097] Fig. 23B schematically illustrates a dual NFET dual PFET logic cell 78. The schematic illustration of Fig. 23B is the same as the schematic illustration of Fig. 22B.

[0098] The six tracks (tracks 1 to 6) described above with respect to FIG. 22A are shown along Fig.23A However, the logic unit mainly utilizes only four of these six tracks. Therefore, the four tracks 77 are along Fig.23A , wherein the four tracks are identified as a first track, a second track, a third track, and a fourth track. The four tracks 77 extend along a first direction corresponding to the x-axis direction shown. The four tracks 77 are separated from each other by intervening spaces 79. The tracks (77) and the spaces (79) alternate with each other along a second direction (the y-axis direction shown). The second direction (y-axis direction) is shown as being orthogonal to the first direction (x-axis direction). In some embodiments, the second direction may be substantially orthogonal to the first direction, wherein the term "substantially orthogonal" means orthogonal within reasonable manufacturing and measurement tolerances.

[0099] Tracks 77 and intervening spaces 79 are at a pitch P1, which may be the minimum photolithography pitch of the manufacturing process.

[0100] The first semiconductor-containing feature 80 is along the first track, and the second semiconductor-containing feature 82 is along the fourth track. The first semiconductor-containing feature 80 is paired with an adjacent semiconductor-containing feature 81, and the second semiconductor-containing feature 82 is paired with an adjacent semiconductor-containing feature 83. Features 80-83 may correspond to a structure similar to Fig.21 In the embodiment shown, fins 80 and 81 are paired with each other, and conductive tube 20a is formed between such fins. In addition, fins 82 and 83 are paired with each other, and conductive tube 20b is formed between such fins. Conductive tubes 20a and 20b can be formed by similar means to those described above with reference to Figures 2 to 5 The processing of the processing is formed.

[0101] The fins 80 and 81 can be considered to be separated from each other by the first gap 16a, and the fins 82 and 83 can be considered to be separated from each other by the second gap 16b. The conductive tubes 20a and 20b are respectively in the first gap and the second gap. The conductive tube 20a is substantially parallel to the fins 80 and 81, and the conductive tube 20b is substantially parallel to the fins 82 and 83.

[0102] In the illustrated embodiment, the fins 80 to 83 are all formed at the pitch P1, and the conductive tubes 20a and 20b are not at this pitch. Instead, the conductive tube 20a is spaced apart from the fin 80 by a first distance D1 that is less than or equal to about one-half of the pitch P1, and the conductive tube 20b is spaced apart from the fin 82 by a second distance D2 that is also less than or equal to about one-half of the pitch P1.

[0103] In some embodiments, distances D1 and D2 may be the same as each other, and in other embodiments, such distances may be different from each other. In some embodiments, first distance D1 and second distance D2 may be less than or equal to about one quarter of pitch P1.

[0104] In the illustrated embodiment, conductive tube 20a is on the side of first semiconductor-containing feature 80 opposite the second track, and conductive tube 20b is on the side of semiconductor-containing feature 82 opposite the third track. Thus, a pair of outer edges of logic cell 78 are bounded by conductive tubes 20a and 20b.

[0105] Conductive tube 20a is shown coupled to VDD (ie, coupled to a reference voltage node at VDD), and conductive tube 20b is shown coupled to VSS (ie, coupled to a reference voltage node at VSS). In other embodiments, the conductive tubes may be coupled to other suitable supply voltages.

[0106] Semiconductor-containing feature 80 is shown to include three p-type source / drain regions (S / D-1, S / D-2, and S / D-3), and semiconductor-containing feature 82 is shown to include three n-type source / drain regions (S / D-4, S / D-5, and S / D-6). Regions S / D-1, S / D-2, and S / D-3 may be referred to as first, second, and third source / drain regions, and regions S / D-4, S / D-5, and S / D-6 may be referred to as fourth, fifth, and sixth source / drain regions.

[0107] The first gating structure 60 a and the second gating structure 60 b extend along the second direction (y-axis direction) and cross the track 77 .

[0108] The first source / drain region S / D-1 and the second source / drain region S / D-2 are on opposite sides of the second gating structure 60b relative to each other, and the second source / drain region S / D-2 and the third source / drain region S / D-3 are on opposite sides of the first gating structure 60a relative to each other. The fourth source / drain region S / D-4 and the fifth source / drain region S / D-5 are on opposite sides of the second gating structure 60b relative to each other, and the fifth source / drain region S / D-5 and the sixth source / drain region S / D-6 are on opposite sides of the first gating structure 60a relative to each other.

[0109] A first electrical connection 84 extends from the first source / drain region S / D-1 to the first conductive tube 20a, and a second electrical connection 86 extends from the third source / drain region S / D-3 to the first conductive tube 20a. A third electrical connection 88 extends from the sixth source / drain region S / D-6 to the second conductive tube 20b. A fourth electrical connection 90 extends from the second source / drain region S / D-2 to the fourth source / drain region S / D-4.

[0110] Input / outputs (I / O) are provided with respect to logic unit 78. In the embodiment shown, a first input / output (I / O-1) has a region (interconnect) extending along the third track and electrically coupled with first gating structure 60a via interconnect 91a.

[0111] The second input / output (I / O-2) has a region (interconnect) extending along the second track and electrically coupled with the second gating structure 60b via the interconnect 91b.

[0112] The third input / output (I / O-3) has a region (interconnect) extending along the third track.A fifth electrical connection 92 extends from the fourth source / drain region (S / D-4) to the interconnect associated with I / O-3.

[0113] The terms "first", "second", and "third" input / output are arbitrary. For example, any of the input / outputs I / O-1 and I / O-2 may be referred to as the "first" and "second" input / outputs.

[0114] Electrical connections 84, 86, 88, 90, and 92 may include any suitable material and may be formed at any suitable elevation level. In some embodiments, gating structures 60a and 60b may be at a first elevation level, and connections 90 and 92 may be at a second level higher than the first level. Electrical connections 84, 86, and 88 may be at the same elevation level as gating structures 60a and 60b, or may be at a different elevation level relative to such gating structures. Electrical connections 84, 86, 88, 90, and 92 may include any suitable conductive material and may include any suitable structural configuration.

[0115] Capacitor 69 is shown electrically coupled along connection 92, and therefore electrically coupled to the fourth source / drain region (S / D-4). Capacitor 69 may be formed at any suitable location, and may or may not be formed at the location shown. One of the electrodes of capacitor 69 is shown coupled to a ground voltage (GND), or in other words, to an electrical node at a ground voltage. In other embodiments, the electrode may be coupled to any other suitable voltage.

[0116] The conductive tube 20 described herein may be disposed in any suitable location and may be used in any suitable application. Fig.24 An application is shown in which conductive features 12 are formed along a first pitch P1 and in which conductive tubes 20 are disposed between the features and used to reduce the pitch. Specifically, features 12 and tubes 20 may be conductive structures that alternate with each other and are formed together along a second pitch that is less than the first pitch P1. Conventional processes utilize a variety of techniques to reduce the pitch. Such techniques are generally referred to as pitch multiplication techniques, with an example pitch multiplication technique being a pitch doubling technique. The pitch doubling technique effectively reduces the pitch between features by approximately half (i.e., forming up to twice as many features within a defined area of ​​a semiconductor substrate). Reference Fig.24 The described method may be considered as an example of utilizing tube 20 in pitch multiplication technology. Fig.24 The structure of can be utilized at any suitable level within an integrated circuit. For example, the structure can be used in a memory array, an electrical bus, etc.

[0117] Fig.25Another application of the conductive tube 20 formed according to the embodiments described herein is shown. The illustrated embodiment has a conductive tube 20 formed between a pair of features 12 and 14. Regions 100a-c are below features 12 and 14 and below the conductive tube 20. Regions 100a-c may correspond to, for example, active regions that span a memory array (i.e., may include semiconductor material 102). The conductive tube 20 shown is coupled to outer regions 100a and 100c via conductive blocks 24 and 26, but extends across inner region 100b without coupling to this region. Specifically, the conductive tube 20 may be higher in height than region 100b. Therefore, the tube 20 may be used as an electrical interconnect extending from region 100a to region 100c and across region 100b without being electrically coupled to this region. In some embodiments, regions 100a and 100c may be referred to as first and second active regions, and region 100b may be referred to as a third active region.

[0118] The assemblies and structures discussed above may be used within integrated circuits (where the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multi-layer, multi-chip modules. The electronic system may be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, game consoles, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0119] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0120] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. The terms are considered synonymous in this disclosure. The use of the term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may provide language changes within the disclosure to simplify the premise basis within the appended claims, and is not intended to indicate any significant chemical or electrical differences.

[0121] Both the terms "electrically connected" and "electrically coupled" may be utilized in this disclosure. The terms are considered synonymous. Utilizing one term in some cases and the other term in other cases may provide language variation within this disclosure to simplify the premise basis within the appended claims.

[0122] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The description provided herein and the appended claims are directed to any structure having the described relationships between the various features, regardless of whether the structure is in a specific orientation in the drawings or rotated relative to such orientation.

[0123] Unless otherwise indicated, the cross-sectional views of the accompanying drawings show only features within the plane of the cross-section and not material behind the plane of the cross-section in order to simplify the drawings.

[0124] When a structure is referred to above as being "on," "adjacent to," or "against" another structure, it may be directly on the other structure or there may also be intervening structures. In contrast, when a structure is referred to as being "directly above," "directly adjacent to," or "directly against" another structure, there are no intervening structures. The terms "directly below," "directly above," and the like do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment.

[0125] Structures (eg, layers, materials, etc.) may be referred to as "vertically extending" to indicate that the structures extend generally upward from an underlying base (eg, substrate). Vertically extending structures may or may not extend generally orthogonally relative to an upper surface of the base.

[0126] Some embodiments include an integrated assembly having a pair of substantially parallel features separated from each other by an intervening space. A conductive tube is between the features and substantially parallel to the features. A first dielectric material is within the intervening space, below the conductive tube, and along the sidewalls of the features. A second dielectric material is within the intervening space and above the first dielectric material. The second dielectric material is above and below the conductive tube.

[0127] Some embodiments include an integrated circuit having a first track, a second track, a third track, and a fourth track extending along a first direction and separated from each other by intervening spaces. The tracks and the intervening spaces alternate with each other along a second direction substantially orthogonal to the first direction. The tracks and the intervening spaces are at a certain pitch. A first semiconductor-containing feature is along the first track. A second semiconductor-containing feature is along the fourth track. A first gating structure extends along the second direction and intersects the first track, the second track, the third track, and the fourth track. A second gating structure extends along the second direction and intersects the first track, the second track, the third track, and the fourth track. A first source / drain region, a second source / drain region, and a third source / drain region are within the first semiconductor-containing feature. The first source / drain region and the second source / drain region are on opposite sides of the second gating structure relative to each other, and the second source / drain region and the third source / drain region are on opposite sides of the first gating structure relative to each other. A fourth source / drain region, a fifth source / drain region, and a sixth source / drain region are within the second semiconductor-containing feature. The fourth source / drain region and the fifth source / drain region are on opposite sides of the second gate structure relative to each other, and the fifth source / drain region and the sixth source / drain region are on opposite sides of the first gate structure relative to each other. A first conductive tube is adjacent to the first semiconductor-containing feature and on a side of the first semiconductor-containing feature opposite to the second track. The first conductive tube is substantially parallel to the first semiconductor-containing feature and is spaced from the first semiconductor-containing feature by a first distance less than about one-half of the pitch. A second conductive tube is adjacent to the second semiconductor-containing feature and on a side of the second semiconductor-containing feature opposite to the third track. The second conductive tube is substantially parallel to the second semiconductor-containing feature and is spaced from the second semiconductor-containing feature by a second distance less than about one-half of the pitch. A first electrical connection extends from the first source / drain region to the first conductive tube. A second electrical connection extends from the third source / drain region to the first conductive tube. A third electrical connection extends from the sixth source / drain region to the second conductive tube.

[0128] Some embodiments include a method of forming an integrated assembly. A first feature and a second feature are formed to be separated from each other by an intervening space. The first feature and the second feature are substantially parallel to each other. A dielectric material is formed within the intervening space. The dielectric material is pinched off at a top of the intervening space to form a tube extending substantially parallel to the first feature and the second feature. A conductive material is formed within the tube to thereby pattern a conductive tube within the tube. The conductive tube is substantially parallel to the first feature and the second feature.

Claims

1. An integrated assembly comprising: a pair of generally parallel features separated from each other by an intervening space; a conductive tube between and substantially parallel to the features; a first dielectric material within the intervening space, beneath the conductive tube and along the sidewalls of the feature; A second dielectric material within the intervening space and above the first dielectric material; the second dielectric material is above and below the conductive tube; and In vertical cross-section, the intervening space includes a horizontal width dimension that is approximately the same as a horizontal width dimension of at least one of the pair of substantially parallel features.

2. The integrated assembly of claim 1, wherein the second dielectric material is along a sidewall of the conductive tube.

3. The integrated assembly of claim 1, comprising a third dielectric material over the second dielectric material.

4. An integrated assembly according to claim 3, wherein the second dielectric material is above the feature; and the integrated assembly includes a planarized surface extending across the second dielectric material and the third dielectric material, wherein the planarized surface is separated from the upper surface of the feature by at least the second dielectric material.

5. The integrated assembly of claim 1, wherein the features comprise fins of semiconductor material, the fins being a first fin and a second fin; one of the pair of substantially parallel features corresponds to the first fin, and the other of the pair of substantially parallel features corresponds to the second fin.

6. The integrated assembly of claim 5, wherein the first fin and the second fin extend upwardly from the column of semiconductor material.

7. The integrated assembly of claim 5, wherein the first fin and the second fin include a first source / drain region and a second source / drain region, respectively; and wherein the conductivity type of the first source / drain region and the second source / drain region are the same as each other.

8. The integrated assembly of claim 7, wherein the first source / drain region and the second source / drain region are p-type.

9. The integrated assembly of claim 7, wherein the first source / drain region and the second source / drain region are n-type.

10. The integrated assembly of claim 7, wherein the first source / drain region is of a different conductivity type relative to the second source / drain region.

11. The integrated assembly of claim 5, wherein the semiconductor material comprises silicon.

12. The integrated assembly of claim 5, wherein the semiconductor material comprises single crystal silicon.

13. The integrated assembly of claim 1, wherein the feature extends a first distance, and wherein the conductive tube extends a second distance less than the first distance.

14. An integrated assembly according to claim 1, wherein the feature extends a first distance, wherein the conductive tube is one of two conductive tubes between the features and each extending a second distance less than the first distance; the two conductive tubes are a first conductive tube and a second conductive tube; the first conductive tube and the second conductive tube are separated by an intervening gap.

15. The integrated assembly of claim 14, comprising a conductive material within the intervening gap and conductively coupling the first conductive tube to the second conductive tube.

16. An integrated assembly according to claim 14, comprising an insulating region within the intervening gap; the first conductive tube has a first terminal end on one side of the insulating region, and the second conductive tube has a second terminal end on an opposite second side of the insulating region.

17. The integrated assembly of claim 16, comprising at least one electrical interconnect extending downwardly to couple with at least one of the first terminal end and the second terminal end.

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