Control circuit with overcurrent prediction to drive capacitive loads

Abstract

A device (700) includes: an input (724) configured to receive an input voltage (714); a prediction circuit (706) coupled to the input (724) and configured to provide an overcurrent prediction (718) based on an analysis of the input voltage (714); a delay circuit (704) coupled to the input (724); a gain control circuit (708) coupled to the output of the delay circuit (704) and configured to selectively adjust a gain applied to at least one frequency range of the input voltage (714) based on the overcurrent prediction (718); a driver (710) coupled to the output of the gain control circuit (708); and a capacitive load (712) coupled to the output of the driver (710).

Description

Background Technology

[0001] The proliferation of electronic devices and integrated circuit (IC) technology has led to the commercialization of IC products. As new electronic devices are developed and IC technology advances, new IC products are commercialized. One example of an IC product required in electronic devices is a current limiter for capacitive loads. A piezoelectric loudspeaker is an example of a capacitive load.

[0002] Piezoelectric loudspeakers, with their advantages of being lighter and thinner, are beginning to be used in devices such as televisions and computers. The capacitive loading characteristics of piezoelectric loudspeakers (impedance varies with frequency) cause the impedance to drop rapidly at high frequencies (>10kHz). Considering the resonant effect of the output LC filter of a Class D amplifier, the combination of a piezoelectric loudspeaker and a Class D amplifier may trigger overcurrent conditions at higher frequencies. Furthermore, the capacitive load introduces poles, which can lead to instability in the Class D amplifier. To address these overcurrent and stability issues, some piezoelectric loudspeaker applications (e.g., televisions) add a series power resistor (~2 to 10 ohms). This series power resistor has several disadvantages, including power loss (low efficiency), heat dissipation (potentially affecting the display or other electronic devices), cost, and size. Summary of the Invention

[0003] According to an example embodiment of this disclosure, a device includes an input configured to receive an input voltage. The device further includes prediction circuitry coupled to the input and configured to provide overcurrent prediction based on analysis of the input voltage. The device also includes a delay circuitry coupled to the input. The device further includes a gain control circuitry coupled to the output of the delay circuitry, wherein the gain control circuitry is configured to selectively adjust a gain applied to at least one frequency range of the input voltage based on the overcurrent prediction. The device further includes a driver coupled to the output of the gain control circuitry. The device also includes a capacitive load coupled to the output of the driver.

[0004] According to an example embodiment of this disclosure, an integrated circuit includes an input configured to receive an input voltage. The integrated circuit also includes control circuitry coupled to the input and configured to: delay the input voltage; provide overcurrent prediction while the input voltage is delayed, wherein the overcurrent prediction is based on analysis of the input voltage and impedance network distribution; select a gain for at least one frequency range of the input voltage based on the overcurrent prediction; and output a drive voltage to a capacitive load based on the selected gain.

[0005] According to an example embodiment of this disclosure, a method includes delaying an input voltage. The method further includes providing an overcurrent prediction while the input voltage is delayed, wherein the overcurrent prediction is based on analysis of the input voltage and capacitive load distribution. The method also includes selecting a gain for at least one frequency range of the input voltage based on the overcurrent prediction, and outputting a drive voltage to the capacitive load based on the selected gain. Attached Figure Description

[0006] Detailed descriptions of various examples will now be provided with reference to the accompanying drawings, in which:

[0007] Figure 1 It is a diagram showing the range of electromagnetic loudspeakers and piezoelectric loudspeakers;

[0008] Figure 2A It is a graph showing the impedance of an electromagnetic loudspeaker as a function of frequency;

[0009] Figure 2B It is a graph showing the impedance of a piezoelectric loudspeaker as a function of frequency;

[0010] Figure 3A is a diagram showing an audio system with a piezoelectric speaker according to a first conventional circuit;

[0011] Figure 3B is a diagram showing another audio system with a piezoelectric speaker according to the second conventional circuit;

[0012] Figure 4A This is a schematic diagram illustrating an impedance network model based on an example embodiment;

[0013] Figure 4B It is a display Figure 4A A graph showing the impedance of the impedance network model as a function of frequency.

[0014] Figure 4C It is a graph showing how the output voltage of a Class D driver circuit changes with the frequency of a piezoelectric loudspeaker;

[0015] Figure 5A This is a diagram illustrating an audio system with an impedance network according to an example embodiment;

[0016] Figure 5B This is a diagram illustrating the distribution of piezoelectric loudspeakers according to an example embodiment;

[0017] Figure 6A This demonstrates an example embodiment. Figure 4A Impedance network model and digital signal processor (DSP) signal diagram;

[0018] Figure 6B It is a display relative to Figure 6A The diagram shows the differential equivalent circuit of the impedance network model.

[0019] Figure 6C It is a display relative to Figure 6A The diagram shows the common equivalent circuit of the impedance network model.

[0020] Figure 7 This is a block diagram illustrating a system according to an example embodiment;

[0021] Figure 8 This is a block diagram illustrating the audio signal and the control circuit of the piezoelectric speaker according to an example embodiment;

[0022] Figure 9 This is a screenshot of a graphical user interface (GUI) for adjusting impedance network distribution according to an example embodiment;

[0023] Figure 10 This is a block diagram illustrating a system according to an example embodiment; and

[0024] Figure 11 This is a flowchart illustrating a method according to an example embodiment. Detailed Implementation

[0025] This document discloses a control circuit for a capacitive load (i.e., the impedance of the load decreases as the frequency of the input signal or voltage to the load increases). In some exemplary embodiments, the capacitive load is a piezoelectric loudspeaker, and the control circuit is part of an integrated circuit (IC), multi-die module (MDM), multi-chip module, or other circuit product for driving the piezoelectric loudspeaker. In one exemplary embodiment, the control circuit delays the input audio signal (voltage) to the piezoelectric loudspeaker. During the delay, the control circuit analyzes the frequency content of the input audio signal (voltage) to determine an overcurrent prediction. Based on the overcurrent prediction, the control circuit selects a gain applied to different frequency ranges of the input audio signal (voltage). More specifically, the gain applied to different frequency ranges of the input audio signal (voltage) is selected to avoid an overcurrent condition. In one example, a gain applied to higher frequency content of the input audio signal (voltage) may be selected to avoid an overcurrent condition. Simultaneously, the control circuit operates to avoid interference at frequencies below a threshold frequency and / or operates to maximize the input audio signal (voltage) to the piezoelectric loudspeaker (e.g., according to predetermined sound quality specifications) without triggering an overcurrent condition.

[0026] In some example embodiments, the overcurrent prediction operation of the control circuit involves a digital signal processor (DSP) configured to provide an impedance network distribution. In one example, the impedance network distribution is based on a model including an inductor-capacitor (LC) circuit and a piezoelectric speaker modeled as a capacitor. Using the impedance network distribution, the DSP can predict the current consumption of the piezoelectric speaker based on the frequency content of the input audio signal (voltage) and the output voltage (Vout) to the piezoelectric speaker. As needed, the control circuit can adjust the gain applied to different frequencies of the input audio signal (voltage) and / or adjust Vout to avoid overcurrent conditions. In some example embodiments, one or more parameters of the impedance network distribution applied by the DSP can be adjusted using a graphical user interface (GUI). In this way, the proposed control circuit can be used to adapt to different piezoelectric speaker scenarios (e.g., televisions / monitors with different sound performance). To provide a better understanding, various control circuit options and associated capacitive load systems or scenarios are described using the following figures. Furthermore, conventional electromagnetic speaker and piezoelectric speaker scenarios are described for contextual reference.

[0027] Figure 1 Figure 100 shows the range 104 of the electromagnetic loudspeaker and the range 108 of the piezoelectric loudspeaker. As shown in Figure 100, the electromagnetic loudspeaker 102 is larger, and its corresponding range 104 is smaller than the range 108 of the piezoelectric loudspeaker 106. Due to the reduced size and improved range of the piezoelectric loudspeaker 106 compared to the electromagnetic loudspeaker 102, it is increasingly used in applications such as television sets or computer monitors. However, some issues remain, such as relative cost and current consumption management.

[0028] Figure 2A Figure 200 shows the impedance of an electromagnetic loudspeaker as a function of frequency. As shown in Figure 200, the impedance has a minimum value set by the DC resistance (Re) of the electromagnetic loudspeaker. The impedance peaks at the resonant frequency (e.g., 20 to 80 Hz) and also increases at higher frequencies due to the voice coil inductance.

[0029] Figure 2B Figure 210 illustrates the impedance of a piezoelectric loudspeaker as a function of frequency. As shown in Figure 210, the impedance curve of the piezoelectric loudspeaker decreases with increasing frequency, as indicated by the solid line, which results in higher current consumption. Furthermore, the phase curve of the piezoelectric loudspeaker increases above 100 kHz, as indicated by the dashed line. In some exemplary embodiments, since the frequency range of the audio application is 20 Hz to 22 kHz, higher frequency values ​​(e.g., above 100 kHz) can be ignored because these values ​​will not be used for audio processing.

[0030] Figure 3A is a diagram illustrating an audio system 300 with a piezoelectric speaker 304 according to a first conventional circuit. As shown, the audio system 300 includes a Class D driver circuit 302 having a positive power supply node (labeled "+") and a negative power supply node (labeled "-"). In the example of Figure 3A, a first inductor-capacitor (LC) circuit with L (e.g., 10uH) and C0 (e.g., 0.68uF) is coupled between the positive power supply node and the ground node. Furthermore, a second LC circuit with L and C0 is coupled between the negative power supply node and the ground node. As shown, a resistor (R1) is used in the audio system 300, where a first end of R1 (e.g., 4.7 ohms) is coupled between L and C0 of the first LC circuit. The second end of R1 is coupled to the piezoelectric speaker 304, such that R1 is in series with the piezoelectric speaker 304. With R1, the impedance distribution of the piezoelectric speaker 304 does not cause an overcurrent condition because R1 increases impedance at all frequencies. However, the use of R1 is undesirable because it increases heat dissipation (heating other nearby electronic devices), consumes power, negatively impacts sound quality, and is a large component that increases the difficulty of housing R1 and other electronic devices within the casing of the final product (e.g., a television or computer monitor).

[0031] Figure 3B is a diagram illustrating another audio system 310 with a piezoelectric speaker according to a second conventional circuit. As shown, audio system 310 includes the first and second LC circuits described in Figure 3A and a piezoelectric speaker 304. The audio system 310 of Figure 3B uses features of a Class D driver circuit 312 to limit the current to the piezoelectric speaker 304, instead of using R1 to limit the current to the piezoelectric speaker 304 as in the audio system 300 of Figure 3A. As shown, the Class D driver circuit 312 includes a first equalizer block 314, a volume block 316, and a digital signal processor (DSP) 318 with dynamic range compression (DRC) and a second equalizer block 320. In the example of Figure 3B, adjusting the equalizer parameters to limit the frequency band of the audio signal (voltage) limits the current to the piezoelectric speaker 304.

[0032] Using the frequency band limiting of the audio system 310 in Figure 3B, the omission of R1 may improve efficiency. However, instability is also possible. Furthermore, the frequency band limiting of the audio system 310 affects all audio levels, which degrades sound quality. Additionally, when the audio signal (voltage) contains several frequency harmonics (multiple tones), the frequency band limiting of the audio system 310 is difficult to adjust and cannot eliminate the risk of overcurrent.

[0033] Figure 4AThis is a schematic diagram illustrating an impedance network model 400 according to an example embodiment. As shown, model 400 includes the first and second LC circuits described in Figures 3A and 3B. Model 400 also includes a piezoelectric loudspeaker represented as a capacitive load (Cp / 2). Model 400 also includes a resistive load (2*Rp) connected in parallel with the piezoelectric loudspeaker. In some example embodiments, the impedance of model 400 is used as an impedance network distribution for the proposed control circuitry to predict overcurrent conditions and adjust as needed. Using impedance network model 400, the current through the inductor and Vout to the piezoelectric loudspeaker 304 can be estimated and used to predict overcurrent conditions. Example adjustments to avoid overcurrent conditions include frequency-dependent gain adjustment and Vout adjustment.

[0034] Figure 4B It is a display Figure 4A Figure 410 shows the impedance of model 400 as a function of frequency. As shown, the impedance of model 400 decreases with increasing frequency. In some exemplary embodiments, an impedance curve is fitted to the impedance of model 400 to limit the current to the piezoelectric loudspeaker. In some exemplary embodiments, the impedance curve (e.g., one shown in Figure 410) is fitted by the proposed control circuitry. The impedance curve can be used to estimate the current consumption of the piezoelectric loudspeaker and to identify risky overcurrent regions that vary with voltage and frequency.

[0035] For example, Figure 4C Figure 420 illustrates the output voltage of a Class D driver circuit varying with the frequency of a piezoelectric speaker. In Figure 420, the impedance curve of model 400 is used to define the overcurrent risk region as a function of output voltage and frequency. The overcurrent risk region can be avoided by monitoring the frequency content of the input audio signal (voltage) and adjusting the output voltage as needed. In some exemplary embodiments, the proposed control circuitry uses a sampling delay buffer (e.g., a 128-sample or 2.67ms delay buffer) to monitor the high-frequency content of the input audio signal (voltage). If an overcurrent or overvoltage condition is estimated to be triggered, the proposed control circuitry reduces the gain applied to the high-frequency content and / or reduces the Vout of the piezoelectric speaker to avoid the overcurrent risk.

[0036] Figure 5AThis is a diagram illustrating an audio system 500 with an impedance network 512 according to an example embodiment. In the audio system 500, the impedance network 512 includes the first and second LC circuits described in Figures 3A and 3B, and a piezoelectric speaker 304. As shown, the audio system 500 of Figure 5 includes a driver circuit 502 configured to provide an output voltage (Vout) to the impedance network 512 based on a control circuit 504 having an overvoltage setting / overcurrent prediction algorithm 506. Using the control circuit 504, Vout is adjusted to take into account the frequency content of the input audio signal (voltage), so that overvoltage and overcurrent events are avoided.

[0037] In some implementations, the operation of control circuit 504 is based on current modeling and estimation across the entire audio frequency band. The overvoltage setting / overcurrent prediction algorithm 506 employed by control circuit 504 can be described as an adaptive look-ahead current limiting algorithm to prevent overvoltage and overcurrent conditions in piezoelectric speaker applications. More specifically, in some implementations, the operation of control circuit 504 is based on current estimation modeling, accurate peak current detection, piezoelectric impedance curve fitting, look-ahead delay buffering, current and voltage gain control, and gain smoothing and attenuation control. In some implementations, control circuit 504 uses LC filters and piezoelectric speaker modeling (e.g., impedance network model 400 for accurate peak current detection and impedance curve fitting). Furthermore, control circuit 504 considers sound quality targets using adaptive gain control, which primarily affects high-frequency content. Independent adjustments are possible for mid- and low-frequency content to minimize the impact of current limiting operation on piezoelectric speaker sound quality. Using audio system 500 avoids series resistors (see, for example, R1 in Figure 3A), which reduces cost and circuit footprint. Furthermore, the driver circuit 502 with control circuit 504 provides a solution that avoids overvoltage and overcurrent conditions of the piezoelectric speaker 304 without affecting the stability of all audio levels. In addition, the driver circuit 502 with control circuit 504 can be adjusted for different impedance networks and is effective for input audio signals (voltages) with several frequency harmonics (multiple tones).

[0038] Figure 5BFigure 510 illustrates the piezoelectric speaker distribution (impedance varying with frequency) according to an example embodiment. In Figure 510, the piezoelectric speaker distribution corresponds to a calculated impedance varying with frequency, which is represented together with a measured impedance varying with frequency. As shown, the calculated impedance and the measured impedance are very well matched, indicating that a curve fitting algorithm (e.g., a DSP implementation using the proposed control circuitry) can provide a piezoelectric speaker distribution that effectively predicts overcurrent conditions from the frequency content of the input audio signal (voltage) and the Vout of the piezoelectric speaker. Based on the predicted overcurrent conditions, the piezoelectric speaker driver can adjust the frequency-dependent gain and / or Vout to avoid overcurrent conditions.

[0039] Figure 6A This demonstrates an example embodiment. Figure 4A The impedance network model 400 and the DSP signal are shown in Figure 600. In Figure 600, the DSP output is a pulse width modulation (PWM) waveform 602 modulated from the audio signal (voltage) 604. Figure 6A In this example, the PWM waveform 602 can be analyzed in two ways. The first method involves filtering out the audio signal (voltage) 604 (after LC filtering) to obtain... Figure 6B The differential equivalent circuit is used to obtain I_diff. The second method involves directly applying the PWM waveform 602 to the LC filter to obtain... Figure 6C The common equivalent circuit is obtained, thus yielding I_com.

[0040] As previously discussed, the impedance network model 400 includes inductors and capacitors, a capacitor (Cpideo) representing a piezoelectric loudspeaker, and an arrangement of parallel resistors. Figure 6B Figure 610 shows the differential equivalent circuit relative to impedance network model 400. Figure 6B In this context, Z_diff corresponds to the impedance of the impedance network as seen from the inductor, V_piezo is the voltage supplied to Cpiezo, and z1 is the impedance of Cpize. Figure 6C Figure 620 shows the common equivalent circuit relative to impedance network model 400. Figure 6C In this context, I_com is the common current in the impedance network, and Vcom is the common voltage supplied to Cpideo.

[0041] In at least some of the example embodiments, the proposed control circuit performs current modeling based on the following:

[0042] Z_diff=i*w*L+Rp. / (1+i*w*Rp*(C0+Cpiezo));

[0043] I_diff = Vin / Z_diff;

[0044] I_com = 1 / L * duty * sin(phasei) * Tpwm * (PVDD - Vcom); and

[0045] I_total = I_diff + I_com

[0046] Where i is the imaginary unit, w is 2*pi* frequency, Vin is the output of the Class D amplifier and the input to the impedance network model 400, phasei is the phase of the current and voltage, Tpwm is the period of the PWM waveform 602, PVDD is the supply voltage of the Class D amplifier, and I_total is the total current through the inductor. Furthermore, in at least some example embodiments, the proposed control circuit performs voltage modeling based on the following:

[0047] z1=Rp / (1+i*w*Rp*(C0+Cpiezo));

[0048] G0 = z1 / z_diff

[0049] Vpiezo = Vin * G1,

[0050] Where z1 is the total impedance of Rp and Cpiezo, C0 is the capacitor of the LC filter, G0 is the gain of the LC filter, Vpiezo is the voltage supplied to the piezoelectric speaker, and G1 is the gain of Vpiezo / Vin. This type of current and voltage modeling operation enables the proposed control circuit to predict the overcurrent condition of the piezoelectric speaker and adjust it as described herein.

[0051] Figure 7 This is a block diagram illustrating a system 700 according to an example embodiment. As shown, system 700 includes control circuitry 702 (e.g., an example of control circuitry 504 in FIG. 5) having an input node 724 configured to receive an input signal (voltage) 714 (e.g., an input audio signal or voltage). Figure 7 In one example, control circuitry 702 includes delay circuitry 704 coupled to input node 724 and configured to output filtered content 716 of input signal (voltage) 714. In this example embodiment, filtered content 716 includes high-frequency content (at or above a threshold frequency) of input signal (voltage) 714 and low-frequency content (below a threshold frequency) of input signal (voltage) 714. Filtered content 716 is provided to gain control circuitry 708 of control circuitry 702.

[0052] As shown, control circuitry 702 also includes overvoltage setting / overcurrent prediction circuitry 706 coupled to input node 724 (e.g., for providing overvoltage setting / overcurrent prediction algorithm 506 in FIG. 5), wherein overvoltage setting / overcurrent prediction circuitry 706 is configured to predict overcurrent conditions of capacitive load 712 based on an adjustable overvoltage setting and analysis of input signal (voltage) 714 and impedance network distribution (e.g., impedance network model 400). In an example embodiment, overvoltage setting / overcurrent prediction circuitry 706 analyzes filtered content of input signal (voltage) 714, such as high-frequency content (at or above a threshold frequency determined by the capacitive load distribution) and low-frequency content (below a threshold frequency determined by the capacitive load distribution). If the amount of high-frequency content is greater than a predetermined amount, then overvoltage setting / overcurrent prediction circuitry 706 predicts that an overcurrent condition will occur and indicates this positive prediction using prediction signal 118. Otherwise, overvoltage setting / overcurrent prediction circuitry 706 predicts that no overcurrent condition will occur and indicates this negative prediction using prediction signal 718. In different embodiments, the prediction signal 718 indicates overcurrent prediction, the predicted amount of overcurrent, the predicted amount of current (whether or not overcurrent is predicted), the amount of current attributable to each of the multiple frequency ranges of the input signal (voltage) 714, and / or other factors.

[0053] Gain control circuit 708 uses prediction signal 718 to adjust the gain of the filtered content 716 applied to input signal (voltage) 714. As needed, the gain applied to the high-frequency content of input signal (voltage) 714 is reduced to avoid overcurrent conditions. Furthermore, the gain applied by gain control circuit 708 can be adjusted to achieve a target sound quality for one or more frequency ranges of input signal (voltage) 714. In some embodiments, driver / other option circuit 710 uses control signal 720 output from gain control circuit 708 to generate drive signal (voltage) 722, which is provided to output node 726 coupled to capacitive load 712 (e.g., piezoelectric speaker). In some embodiments, driver / other option circuit 710 includes driver components and equalizer and / or automatic gain equalizer (AGL) components. Using overcurrent prediction operation of control circuit 702, the amount of current supplied to capacitive load 712 using drive signal (voltage) 722 is limited as needed to avoid overcurrent conditions. Meanwhile, the frequency content of the drive signal (voltage) 722 is intended to match the frequency content of the input signal (voltage) 714 (some equalization options may be selected by the user) and / or the amount of current provided to the capacitive load 712 by the drive signal (voltage) 722 is intended to meet predetermined sound quality specifications.

[0054] Figure 8This demonstrates an audio signal (voltage) and a control circuit 800 for a piezoelectric loudspeaker according to an example embodiment (control circuit 504 in Figure 5 or...). Figure 7 A block diagram of an example of control circuit 702. As shown, control circuit 800 includes delay circuit 704A ( Figure 7 Example of delay circuit 704), overvoltage setting / overcurrent prediction circuit 706A ( Figure 7 Examples of overvoltage setting or overcurrent prediction circuit 706 and gain control circuit 708A (in the context of overvoltage setting or overcurrent prediction circuit 706) Figure 7 (Example of gain control circuit 708). In different example embodiments, hardware, software, or a combination of hardware and software are used to perform the operation of control circuit 800. In one example embodiment, a DSP and related instructions are used to perform at least some of the operations of control circuit 800.

[0055] exist Figure 8 In one example, the delay circuit 702A includes a delay buffer 802 (e.g., a 128-sample delay buffer), a low-pass filter 804 (e.g., a 4th-order Butterworth low-pass filter), and a high-pass filter 806 (e.g., a 4th-order Butterworth high-pass filter). The output of the delay circuit 702A includes a voltage 714A based on the input signal (voltage) provided to the delay circuit 702A. Figure 7 The delayed low-frequency content 860 and delayed high-frequency content 862 of the input signal or voltage 714 (example).

[0056] Input signal (voltage) 714A is also provided to overvoltage setting / overcurrent prediction circuit 706A, which includes a low-pass filter 812 (e.g., a 4th-order Butterworth low-pass filter) and a high-pass filter 842 (e.g., a 4th-order Butterworth high-pass filter). The output of low-pass filter 812 is input to a feedback loop, which includes a multiplier block 814, a boost / attenuation block 816, a smoothing block 818, and a minimum block 820. As shown, a first output signal 864 from overvoltage setting / overcurrent prediction circuit 706A is provided from minimum block 820 to gain control circuit 708A. The first output signal 864 is also fed back to multiplier block 814. Similarly, the output of high-pass filter 842 is input to a feedback loop, which includes multiplier block 844, boost / attenuation block 846, smoothing block 848, and minimum block 850. As shown, a second output signal 866 from the overvoltage setting / overcurrent prediction circuit 706A is provided from the minimum block 850 to the gain control circuit 708A. The second output signal 866 is also fed back to the multiplication block 844. The outputs of multiplication blocks 814 and 844 are also provided to the weight selection controller 822, which includes a summing block 824, a voltage-to-current conversion function block 826, a tone / attenuation block 828, a smoothing block 830, a low-frequency weighting block 832, and a high-frequency weighting block 834. As needed, the output of the low-frequency weighting block 832 is used to adjust at least one parameter of the minimum block 820, and the output of the high-frequency weighting block 834 is used to adjust at least one parameter of the minimum block 850.

[0057] As shown, the gain control circuit 708A includes a first multiplier block 852 to control the gain applied to the delayed low-frequency content 860 based on a first output signal 864 from the overvoltage setting / overcurrent prediction circuit 706A. The gain control circuit 706A also includes a second multiplier block 854 to control the gain applied to the delayed high-frequency content 862 based on a second output signal 866 from the overvoltage setting / overcurrent prediction circuit 706A. The outputs of multiplier blocks 852 and 854 are provided to a summing block 856. The output of the summing block 856 is the output signal 868 from the gain control circuit 708A. Figure 8 In the example, the output signal is 868 ( Figure 7 An instance of control signal 720 in the middle is provided to block 870. Figure 7 An example of the driver / other option circuit 710), which performs subsequent operations such as post-equalization or AGL operation. The drive signal (voltage) 872 output from block 870 ( Figure 7 An example of the drive signal 722 is provided to a capacitive load (e.g., a piezoelectric loudspeaker), as described herein.

[0058] exist Figure 8In the example, the blocks of the delay circuit 704A, the overvoltage setting / overcurrent prediction circuit 706A, and the gain control circuit 708A are indicated by bold numbers 1 to 12 to illustrate the sequence of steps of the example algorithm employed by the control circuit 800. Steps 1 to 12 are intended to aid understanding. Figure 8 This is an example algorithm and is not intended to limit the implementation of the control circuitry to a particular set of components or operations / sequence. In step 1, delay buffer 802 buffers the input audio data before outputting it to the piezoelectric speaker. During the buffering time, the algorithm executes steps 2 through 9. In step 2, low-pass filter 812 and high-pass filter 842 filter the input audio signal (voltage) 714A into low-frequency and high-frequency content. In step 3, the full-band audio signal (voltage) is recovered by summing block 824 by adding the low-frequency audio content to the high-frequency content. Step 3 is executed in part because current control works faster than voltage control. At step 4, voltage-to-current conversion function block 826 (e.g., corresponding to five dual quaternions or "BQ" of an infinite impulse response (IIR) filter) is used to perform a fitting operation and predict the current in the piezoelectric speaker based on the impedance network distribution. At step 5, gain control is performed using attack / attenuation blocks 816, 828, and 846. When I = V / R, the maximum output current is estimated and compared with a predetermined maximum allowable current value. If the estimated maximum output current exceeds the predetermined maximum allowable current value, the gain is reduced. Otherwise, the gain remains unchanged. In some example embodiments, step 5 involves comparing the output voltage with a predetermined maximum allowable output voltage. If the output voltage exceeds the maximum value, the gain is reduced. Otherwise, the gain remains unchanged.

[0059] At step 6, smoothing blocks 818, 830, and 848 operate to smooth voltage and current gains to avoid sound defects. At step 7, weighting blocks 832 and 834 are used to adjust the gain weights of low-frequency and high-frequency content. When an overcurrent is predicted, at least one of the gain adjustments is reduced. In one example embodiment, the gains of both low-frequency and high-frequency content decrease in response to an overcurrent prediction (e.g., the reduction in high-frequency content gain is greater than the reduction in low-frequency content gain to achieve the desired sound quality). At step 8, minimum operations are performed by minimum blocks 820 and 850 to ensure that the algorithm satisfies independent voltage and current control. At step 9, multiplication blocks 814 and 844 implement a feedback mechanism to ensure a stable and appropriate gain after repeated operations of the voltage and current gain control algorithm. At step 10, the delay time expires, and multiplication blocks 852 and 854 receive the delayed and filtered input signal (voltage) content. Multiplication blocks 852 and 854 multiply the high-frequency and low-frequency content by the gain obtained from steps 2 through 9 to avoid overcurrent and overvoltage conditions. At step 11, summing block 856 combines the adjusted high-frequency and low-frequency content to form the full-band audio content for output from gain control circuit 708A. At step 12, block 870 performs post-equalization and AGL operations to further limit the voltage applied to the power loudspeaker (if necessary).

[0060] Figure 9 This is a screenshot 900 of a GUI for adjusting the impedance network distribution according to an example embodiment. As shown in screenshot 900, the values ​​of Cpiezo, Rp, L, and C (C0 in the impedance network model 400 and related equations) are adjustable, which allows for changes to the fit of the impedance network distribution used by the control circuitry described herein. In some example embodiments of the GUI, the value of Cpiezo is determined by user selection. Once Cpiezo is selected, values ​​for L, C, and Rp are recommended based on stability considerations and the current limiting algorithm. After the GUI accepts all values, the values ​​are sent to the control circuitry (e.g., DSP) of the Class D amplifier for use in the current limiting algorithm.

[0061] Figure 10This is a block diagram illustrating a system 1000 according to an example embodiment. System 1000 represents an end product (e.g., a television or computer monitor) having a piezoelectric speaker 1008 capable of dynamically avoiding overvoltage and overcurrent conditions of the piezoelectric speaker as described herein, and one or more integrated circuits (ICs) 1001. As shown, IC 1001 includes control circuitry 1002 (e.g., an example of control circuitry 504 in FIG. 5, such as a DSP and / or other components), which has delay circuitry 704, overvoltage setting / overcurrent prediction circuitry 706, gain control circuitry 708, and associated signals (e.g., 714, 716, 718, 720). Control signal 720 output from control circuitry 1002 is provided to driver / other option circuitry 710 included in IC 1001. Figure 10 In one example, the control circuit 1002 also includes GUI instructions 1004 to support adjustments to the impedance network distribution, as described herein (see example...). Figure 9 (Screenshot 900). IC 1001 also includes a video processing block 1006, which is configured to process the input video signal 1010. Figure 10 In this example, the input nodes of IC 1001 include an audio input node 1014 and a video input node 1016. Furthermore, the output nodes of IC 1001 include an audio output node 1018 (e.g., for outputting a drive signal (voltage) 722 to a piezoelectric speaker 1008) and a video output node 1020 for outputting a video signal 1012 to a display 1010. In different example embodiments, IC 1001 corresponds to a single integrated circuit, multiple integrated circuits, and / or a combination of integrated circuit components and discrete components.

[0062] Figure 11 This is a flowchart illustrating method 1100 according to an example embodiment. As shown, method 1100 includes delaying an input signal (voltage) at block 1102. At block 1104, an overcurrent prediction signal is provided while the input signal (voltage) is delayed, wherein the overcurrent prediction signal is based on analysis of the input signal (voltage) and impedance network distribution (e.g., Figure 4A (Impedance network model 400 in the diagram). At block 1106, based on the overcurrent prediction signal, a gain for at least one frequency range of the input signal (voltage) is selected. At block 1108, the drive signal (voltage) is output to the capacitive load based on the selected gain.

[0063] In some example embodiments, method 1100 includes filtering the input signal (voltage) to obtain a first input signal (voltage) content associated with a first frequency range (e.g., from...). Figure 8The first frequency range is higher than the second frequency range, and the overcurrent prediction signal is based on the analysis of the first input signal (voltage) content.

[0064] In some example embodiments, method 1100 includes storing the input signal or voltage (e.g., using...). Figure 8 The delay buffer 802 in the middle); filters the input signal to obtain a first input signal (voltage) content associated with a first frequency range (e.g., from the delay buffer 802 in the middle); Figure 8 The high-frequency content of the high-pass filter 806 in the middle) and the content of the second input signal (voltage) associated with the second frequency range (e.g., from the high-pass filter 806 in the middle) and the second input signal (voltage) content associated with the second frequency range (e.g., from the high-frequency content of ... Figure 8 The low-frequency content of the low-pass filter 804 in the middle, wherein the first frequency range is higher than the second frequency range; multiply the first input signal (voltage) content by a first gain (e.g., by multiplication block 854) to obtain an adjusted first input signal content, wherein the first gain is based on an overcurrent prediction signal; multiply the second input signal (voltage) content by a second gain (e.g., by multiplication block 852) to obtain an adjusted second input signal (voltage) content; and combine the adjusted first input signal (voltage) content with the adjusted second input signal (voltage) content (e.g., by summing block 856).

[0065] In some example embodiments, method 1100 includes: filtering the input signal (voltage) to obtain a first input signal (voltage) content associated with a first frequency range (e.g., from...). Figure 8 The high-frequency content of the high-pass filter 842 in the middle) and the content of the second input signal (voltage) associated with the second frequency range (e.g., from the high-pass filter 842 in the middle) and the second input signal (voltage) content associated with the second frequency range (e.g., from the high-frequency content of ... Figure 8 The low-frequency content of the low-pass filter 812 in the middle), wherein the first frequency range is higher than the second frequency range; the first feedback loop (e.g., Figure 8 Blocks 814, 816, 818, and 820 in the code are applied to the content of the first input signal (voltage) to generate a first gain; and the second feedback loop (e.g., Figure 8 Blocks 844, 846, 848, and 850 in the method are applied to the content of the second input signal (voltage) to generate a second gain. In some example embodiments, method 1100 includes applying weights to the first gain and the second gain based on a weight selection operation that takes into account the content of the first input signal (voltage) and the content of the second input signal (voltage).

[0066] In some example embodiments, a device (e.g., a television set or computer monitor) includes components configured to receive input signals or voltages (e.g., Figure 10The input node of the input audio signal 714 in the middle (e.g., Figure 10 The device also includes prediction circuitry (e.g., overvoltage setting / overcurrent prediction circuitry 506 in Figure 5). (Input audio node 1014 in the figure). Figure 7 and 10 The overvoltage setting / overcurrent prediction circuit 706 in the middle, or Figure 8 The overvoltage setting / overcurrent prediction circuit 706A in the circuit is coupled to the input node and configured to provide an overcurrent prediction signal based on the analysis of the input signal (voltage). Figure 7 and 10 Predicted signal 718 Figure 8 The first output signal 864 or Figure 8 The second output signal is 866. The device also includes delay circuitry coupled to the input node (e.g., Figure 7 and 10 The delay circuit 704 in the middle, or Figure 8 The device also includes a delay line 704A (in the example). The device also includes gain control circuitry (e.g., ...). Figure 7 and 10 The gain control circuit 708 in the middle, or Figure 8 The device includes a gain control circuit 708A coupled to the output of a delay circuit and configured to selectively adjust the gain applied to at least one frequency range of an input signal (voltage) based on an overcurrent prediction signal. The device also includes a driver (e.g., ...) coupled to the output of the gain control circuit. Figure 7 and 10 The driver / other option circuit 710 in the middle, or Figure 8 Block 870 in the middle), where the driver is based on the output of the gain control circuit (e.g., Figure 7 and 10 Control signal 720 in, or Figure 8 The output signal 868 in the middle provides a drive signal or voltage (e.g., Figure 7 and 10 The drive signal 722 in the middle, or Figure 8 The drive signal 872 in the device also includes a capacitive load (e.g., drive signal 872 in the device). Figure 5A The piezoelectric loudspeaker 304 in Figure 7 The capacitive load 712 in the middle Figure 10 The piezoelectric loudspeaker 1008 is coupled to the output of the driver and configured to receive a drive signal (voltage).

[0067] In some example embodiments, the prediction circuit is configured to filter the input signal (voltage) to obtain a first input signal (voltage) content associated with a first frequency range (e.g., high-frequency content from high-pass filter 842) and a second input signal (voltage) content associated with a second frequency range (e.g., low-frequency content from low-pass filter 812), wherein the first frequency range is higher than the second frequency range, and wherein the overcurrent prediction signal is based on the analysis of the first input signal (voltage) content.

[0068] In some example embodiments, the delay circuit includes: a delay buffer (e.g., Figure 8 Delay buffer 802 in the middle); low-pass filter (e.g., Figure 8 The low-pass filter 804 in the buffer is coupled to the output of the delay buffer; and the high-pass filter (e.g., Figure 8 The high-pass filter 806 in the circuit is coupled to the output of the delay buffer. In some example embodiments, the gain control circuit includes a first multiplier (e.g., Figure 8 The multiplier block 852 in the middle is coupled to the output of the low-pass filter; the second multiplier (e.g., Figure 8 The multiplication block 854 in the middle is coupled to the output of the high-pass filter; and the summing circuit (e.g., Figure 8 The summation block 856 in the middle is coupled to the outputs of the first and second multipliers.

[0069] In some example embodiments, the prediction circuit includes: a low-pass filter (e.g., Figure 8 The low-pass filter 812 in the middle is coupled to the input node; the first feedback loop (e.g., Figure 8 Blocks 814, 816, 818, and 820 in the diagram), which are coupled to the output of a low-pass filter; a high-pass filter (e.g., Figure 8 The high-pass filter 842 in the middle is coupled to the input node; the second feedback loop (e.g., Figure 8 Blocks 844, 846, 848, and 850 in the diagram), which are coupled to the output of the high-pass filter; and a weight selection controller (e.g., Figure 8 The weight selection controller 822 in the middle is coupled to the first and second feedback loops.

[0070] In some example embodiments, the first feedback loop includes a third multiplier block (e.g., Figure 8 Multiplication block 814); First attack / attenuation block (e.g., Figure 8 The attack / attenuation block 816 in the middle, which is coupled to the third multiplier block; the first smoothing block (e.g., Figure 8 The smooth block 818 in the middle, which is coupled to the first tone / attenuation block; and the first minimum block (e.g., Figure 8The smallest block 820 in the first smoothing block is coupled to the first smoothing block, wherein the output of the first smallest block is provided to the third multiplier block (e.g., multiplier block 814) and the first multiplier block of the gain control circuit (e.g., ...). Figure 8 (Multiplication block 852 in the example). In some example embodiments, the second feedback loop includes: a fourth multiplier block (e.g., Figure 8 The multiplication block 844); the second tone / attenuation block (e.g., Figure 8 The attack / attenuation block 846 in the middle, which is coupled to the fourth multiplier block; the second smoothing block (e.g., Figure 8 The smooth block 848 in the middle, which is coupled to the second attack / attenuation block; and the second minimum block (e.g., Figure 8 The smallest block (850) is coupled to the second smoothing block, wherein the output of the second smallest block is provided to the fourth multiplier block (e.g.: Figure 8 The multiplier block 844 in the multiplier circuit and the second multiplier block of the gain control circuit (e.g., Figure 8 Multiplication block 854 in the middle.

[0071] In some example implementations, the weight selection controller includes: a summation block (e.g., Figure 8 Summation block 824); Voltage to current conversion function block (e.g., Figure 8 The voltage-to-current conversion function block 826 in the middle), which is coupled to the summation block; the third tone / attenuation block (e.g., Figure 8 The attenuation / fade-off block 828 in the middle, which is coupled to the voltage-to-current conversion function block; the third smoothing block (e.g., Figure 8 The smoothing block 830 in the middle), which is coupled to the third tone / attenuation block; the first weight block (e.g., Figure 8 The low-frequency weight block 832 in the first weight block is coupled to the third smoothing block, wherein the output of the first weight block is provided to the first minimum block; and the second weight block (e.g., Figure 8 The high-frequency weight block 834 is coupled to the third smoothing block, wherein the output of the second weight block is provided to the second minimum block.

[0072] In some example embodiments, the device further includes: a display (e.g., Figure 10 The display (1010) and housing (e.g., a television or computer monitor housing) are included, wherein the capacitive load is a piezoelectric speaker mechanically coupled to the display to transmit audio signals (voltage). In some exemplary embodiments, the input node, prediction circuitry, delay circuitry, and gain control circuitry are components of an integrated circuit. In some exemplary embodiments, the operation of the prediction circuitry, delay circuitry, and gain control circuitry is performed by a DSP.

[0073] In some example embodiments, an integrated circuit includes: an input node (e.g., input audio node 1014) configured to receive an input signal or voltage (e.g., input audio signal 714); and control circuitry (e.g., Figure 5A The control circuit 504 in Figure 7 and 10 The control circuit 702, or Figure 10 The control circuit 1002 is configured to: delay the input signal (voltage); and provide an overcurrent prediction signal (e.g., while the input signal (voltage) is delayed. Figure 7 and 10 The predicted signal 718 in the figure, wherein the overcurrent prediction signal is based on the analysis of the input signal (voltage) and the impedance network distribution (e.g., in the figure). Figure 4A Impedance network model 400); based on the overcurrent prediction signal, select the gain applied to at least one frequency range of the input signal (voltage) (e.g., using...). Figure 8 The first and second output signals 864 and 866 in the middle); and the driving signal or voltage (e.g., based on the selected gain) will be driven. Figure 7 and 10 The drive signal 722) is output to the capacitive load.

[0074] In some example embodiments, the control circuitry is configured to filter the input signal (voltage) to obtain high-frequency content (e.g., from...). Figure 8 The high-frequency content of the high-pass filter 842 in the middle) and the low-frequency content (e.g., from ... Figure 8 The low-frequency content of the low-pass filter 812 in the circuit is used, where the overcurrent prediction signal is based on the analysis of the high-frequency content. The control circuit is further configured to: store the input signal or voltage (e.g., using...). Figure 8 The delay buffer 802 in the middle); filters the input signal (voltage) to obtain high-frequency content (e.g., from the delay buffer 802 in the middle); Figure 8 The high-frequency content of the high-pass filter 806 in the middle) and the low-frequency content (e.g., from ... Figure 8 The low-frequency content of the low-pass filter 804 in the middle); multiply the high-frequency content by the first gain (e.g., Figure 8 The second output signal 866 or a related value is used to obtain the adjusted high-frequency content, wherein the first gain is based on the overcurrent prediction signal; the low-frequency content is multiplied by the second gain (e.g., Figure 8 The first output signal 864 or related value in the process is used to obtain adjusted low-frequency content; and the combination (e.g., using...) Figure 8 The summation block 856 in the middle is the adjusted high-frequency content and the adjusted low-frequency content.

[0075] In some exemplary embodiments, the control circuitry is further configured to: filter the input signal (voltage) to obtain high-frequency content (e.g., using... Figure 8 The high-pass filter 842 in the middle) and low-frequency content (e.g., using Figure 8 The control circuitry includes a low-pass filter 812; a first feedback loop (e.g., blocks 814, 816, 818, and 820) is applied to high-frequency content to generate a first gain; and a second feedback loop (e.g., blocks 844, 846, 848, and 850) is applied to low-frequency content to generate a second gain. In some example embodiments, the control circuitry is further configured to select operations based on weights that take into account both low-frequency and high-frequency content (e.g., ...). Figure 8 The operation of the weight selection controller 822 in the middle applies weights to the first gain and the second gain.

[0076] Throughout this description and claims, certain terms are used to refer to specific system components. As those skilled in the art will appreciate, different parties may use different names to refer to components. This document is not intended to distinguish components that differ only in name but are identical in their respective functions or structures. In this disclosure and claims, the terms "comprising" and "including" are used in an open-ended manner and should therefore be interpreted as "including (but not limited to)...".

[0077] The term "coupled" is used throughout this specification. The term may encompass a connection, communication, or signaling path that enables a functional relationship consistent with the description of this disclosure. For example, if device A generates a signal to control device B to perform an action, then in a first instance, device A is coupled to device B via a direct connection; or in a second instance, if intermediate component C does not substantially alter the functional relationship between device A and device B, then device A is coupled to device B via intermediate component C, such that device B is controlled by device A via a control signal generated by device A.

[0078] The foregoing discussion is intended to illustrate the principles of the invention and various embodiments. Once fully understanding the above disclosure, many variations and modifications will be apparent to those skilled in the art.

Claims

1. An electronic device comprising: Input, which is configured to receive input voltage; A prediction circuit coupled to the input and configured to provide an overcurrent prediction voltage based on the input voltage; Delay circuit, which is coupled to the input; A gain control circuit coupled to the output of the delay circuit and configured to selectively adjust the gain applied to at least one frequency range of the input voltage based on the overcurrent prediction voltage, wherein the overcurrent prediction voltage is based on an impedance network distribution. A driver, which is coupled to the output of the gain control circuit; as well as A capacitive load that is coupled to the output of the driver.

2. The electronic device of claim 1, wherein the prediction circuit is configured to filter the input voltage to obtain a first input voltage content associated with a first frequency range and a second input voltage content associated with a second frequency range, wherein the first frequency range is higher than the second frequency range, and wherein the overcurrent prediction voltage is based on an analysis of the first input voltage content.

3. The electronic device of claim 1, wherein the delay circuit comprises: Delay buffer; A first low-pass filter, coupled to the output of the delay buffer; and A first high-pass filter is coupled to the output of the delay buffer.

4. The electronic device of claim 3, wherein the gain control circuit comprises: The first multiplier is coupled to the output of the first low-pass filter; A second multiplier, coupled to the output of the first high-pass filter; and A summing circuit coupled to the outputs of the first multiplier and the second multiplier.

5. The electronic device of claim 4, wherein the prediction circuit comprises: A second low-pass filter is coupled to the input; The first feedback loop is coupled to the output of the second low-pass filter; A second high-pass filter is coupled to the input; The second feedback loop is coupled to the output of the second high-pass filter; and A weighted selection controller, which is coupled to the first feedback loop and the second feedback loop.

6. The electronic device of claim 5, wherein the first feedback loop comprises: Third multiplier block; The first tone / attenuation block is coupled to the third multiplier block; A first smoothing block, coupled to the first attack / attenuation block; and A first minimum block, coupled to the first smoothing block, wherein the output of the first minimum block is provided to the third multiplier block and the first multiplier block of the gain control circuit, and The second feedback loop includes: Fourth multiplier block; The second tone / attenuation block is coupled to the fourth multiplier block; A second smoothing block, coupled to the second attack / attenuation block; and The second minimum block is coupled to the second smoothing block, wherein the output of the second minimum block is provided to the fourth multiplier block and the second multiplier block of the gain control circuit.

7. The electronic device of claim 6, wherein the weight selection controller comprises: Summation block; A voltage-to-current conversion function block, which is coupled to the summing block; The third tone / attenuation block is coupled to the voltage-to-current conversion function block; The third smoothing block is coupled to the third tone / attenuation block; A first weighted block, which is coupled to the third smoothing block, wherein the output of the first weighted block is provided to the first minimum block; and A second weighted block is coupled to the third smoothing block, wherein the output of the second weighted block is provided to the second minimum block.

8. The electronic device of claim 1, comprising a display, wherein the capacitive load is a piezoelectric speaker mechanically coupled to the display.

9. The electronic device of claim 1, wherein the input, the prediction circuit, the delay circuit, and the gain control circuit are components of an integrated circuit.

10. The electronic device of claim 1, wherein the operation of the prediction circuit, the delay circuit, and the gain control circuit is performed by a digital signal processor (DSP).

11. An integrated circuit, comprising: Input, which is configured to receive input voltage; as well as Control circuitry, coupled to the input and configured to: Delay the input voltage; An overcurrent prediction voltage is provided when the input voltage is delayed, wherein the overcurrent prediction voltage is based on the input voltage and the impedance network distribution; Based on the overcurrent predicted voltage, a gain is selected for at least one frequency range of the input voltage; and The drive voltage is output to the capacitive load based on the selected gain.

12. The integrated circuit of claim 11, wherein the control circuit is configured to filter the input voltage to obtain low-frequency content and high-frequency content, and wherein the overcurrent prediction voltage is based on the analysis of the high-frequency content.

13. The integrated circuit of claim 11, wherein the control circuit is further configured to: Store the input voltage; The input voltage is filtered to obtain low-frequency and high-frequency content; The high-frequency content is multiplied by a first gain to obtain adjusted high-frequency content, wherein the first gain is based on the overcurrent prediction voltage; Multiply the low-frequency content by the second gain to obtain the adjusted low-frequency content; and Combine the adjusted low-frequency content with the adjusted high-frequency content.

14. The integrated circuit of claim 13, wherein the control circuit is further configured to: The input voltage is filtered to obtain low-frequency and high-frequency content; The first feedback loop is applied to the high-frequency content to generate the first gain; and The second feedback loop is applied to the low-frequency content to generate the second gain.

15. The integrated circuit of claim 14, wherein the control circuit is further configured to apply weights to the first gain and the second gain based on a weight selection operation that takes into account the high-frequency content and the low-frequency content.

16. A method for using an integrated circuit, comprising: Delay the input voltage; An overcurrent prediction voltage is provided when the input voltage is delayed, wherein the overcurrent prediction voltage is based on the analysis of the input voltage and the impedance network distribution; Based on the overcurrent predicted voltage, a gain is selected for at least one frequency range of the input voltage; as well as The drive voltage is output to the capacitive load based on the selected gain.

17. The method of claim 16, further comprising filtering the input voltage to obtain a first input voltage content associated with a first frequency range and a second input voltage content associated with a second frequency range, wherein the first frequency range is higher than the second frequency range, and wherein the overcurrent prediction voltage is based on the first input voltage content.

18. The method of claim 16, further comprising: Store the input voltage; The input voltage is filtered to obtain a first input voltage content associated with a first frequency range and a second input voltage content associated with a second frequency range, wherein the first frequency range is higher than the second frequency range; The first input voltage content is multiplied by a first gain to obtain an adjusted first input voltage content, wherein the first gain is based on the overcurrent predicted voltage; Multiply the second input voltage content by the second gain to obtain the adjusted second input voltage content; and Combine the adjusted first input voltage content with the adjusted second input voltage content.

19. The method of claim 18, further comprising: The input voltage is filtered to obtain a first input voltage content associated with a first frequency range and a second input voltage content associated with a second frequency range, wherein the first frequency range is higher than the second frequency range; The first feedback loop is applied to the first input voltage content to generate the first gain; and The second feedback loop is applied to the second input voltage content to generate the second gain.

20. The method of claim 19, further comprising applying weights to the first gain and the second gain based on a weight selection operation considering the first input voltage content and the second input voltage content.

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