A fft hardware accelerator and data processing method

Abstract

This application provides an FFT hardware accelerator and data processing method, relating to the field of digital signal processing. The FFT hardware accelerator includes an FFT processing module comprising multiple butterfly operation units, divided into even-level and odd-level butterfly operation units. Each odd-level butterfly operation unit is connected to a transformation unit, which swaps the real and imaginary parts of the complex number obtained from the previous-level butterfly operation unit connected to the transformation unit, inverts the swapped imaginary part, and then passes it to the next-level butterfly operation unit connected to the transformation unit; or, it passes the result of the previous-level butterfly operation unit connected to the transformation unit to the next-level butterfly operation unit connected to the transformation unit. Compared with related technologies, this significantly reduces the number of multiplication operations, lowers the data processing volume, and simplifies the hardware structure and simplifies control of the FFT hardware accelerator.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of digital signal processing, and in particular to an FFT hardware accelerator and a data processing method. BACKGROUND

[0002] The main core idea of the Fast Fourier Transform (FFT) algorithm is to gradually decompose an N-point sequence into (N-1) / 2, and then into two-point Discrete Fourier Transform (DFT). The current FFT algorithm can be divided into two categories: one is to decompose the sequence x(n) in the time domain, which is called time decimation method; the other is to decompose the sequence x(k) in the frequency domain, which is called frequency decimation method.

[0003] The commonly used FFT algorithm is base-2 FFT algorithm, and the base-2 FFT algorithm is a process of decomposing N-point DFT operation into log2N 2-point DFT operations. When the base-2 FFT algorithm is used to implement the FFT hardware accelerator, a complex multiplier needs to be connected after each butterfly operation unit in the FFT hardware accelerator, which makes the hardware structure of the FFT hardware accelerator simple, but requires a large amount of multiplication operation on data, and the operation amount is large. SUMMARY

[0004] To solve the existing technical problems, embodiments of the present application provide an FFT hardware accelerator and a data processing method, which can reduce the operation amount of the FFT hardware accelerator for processing data.

[0005] To achieve the above purpose, the technical scheme of the embodiments of the present application is as follows:

[0006] In a first aspect, the embodiments of the present application provide an FFT hardware accelerator, comprising an FFT processing module, the FFT processing module comprising a plurality of butterfly operation units; the plurality of butterfly operation units comprising even-stage butterfly operation units and odd-stage butterfly operation units; wherein one conversion unit is connected after each odd-stage butterfly operation unit; the conversion unit is used to exchange the real part and the imaginary part of the operation result of the upper-stage butterfly operation unit connected with the conversion unit, and after taking the negative of the exchanged imaginary part, the result is transmitted to the lower-stage butterfly operation unit connected with the conversion unit; or the conversion unit is used to transmit the operation result of the upper-stage butterfly operation unit connected with the conversion unit to the lower-stage butterfly operation unit connected with the conversion unit.

[0007] The FFT hardware accelerator provided by the embodiment of the present application comprises an FFT processing module, the FFT processing module comprises a plurality of butterfly operation units, and the plurality of butterfly operation units comprise even-level butterfly operation units and odd-level butterfly operation units. Each odd-level butterfly operation unit is connected with a conversion unit, the conversion unit is configured to exchange the real part and the imaginary part of the operation result of the butterfly operation unit connected with the conversion unit, and after negating the imaginary part after the exchange, the result is transmitted to the butterfly operation unit connected with the conversion unit; or the conversion unit is configured to transmit the operation result of the butterfly operation unit connected with the conversion unit to the butterfly operation unit connected with the conversion unit. Compared with the FFT hardware accelerator using the radix-2 FFT algorithm in the related art, since a complex multiplier is not connected after each butterfly operation unit, but a conversion unit is connected after each odd-level butterfly operation unit, the number of multiplication operations can be greatly reduced by using the conversion unit, thereby reducing the data operation amount, saving the hardware multiplier resources of the FFT hardware accelerator, and simplifying the hardware structure of the FFT hardware accelerator.

[0008] In an optional embodiment, the FFT processing module further comprises at least one complex multiplier.

[0009] Each complex multiplier is configured to generate a complex rotation factor, and after multiplying the operation result of the butterfly operation unit connected with the complex multiplier by the complex rotation factor, the result is transmitted to the butterfly operation unit connected with the complex multiplier.

[0010] The FFT processing module in the FFT hardware accelerator further comprises at least one complex multiplier, each complex multiplier is configured to generate a complex rotation factor, and after multiplying the operation result of the butterfly operation unit connected with the complex multiplier by the complex rotation factor, the result is transmitted to the butterfly operation unit connected with the complex multiplier. Thus, the FFT hardware accelerator can implement the corresponding FFT algorithm, and the control of the FFT hardware accelerator is convenient.

[0011] In an optional embodiment, each butterfly operation unit is configured to, when serially inputting target data with a length of N, store the first N / 2 data of the target data by using a random access memory (RAM) with a storage data amount of N / 2, and for each first data in the last N / 2 data of the target data, perform addition and subtraction operations on the first data and second data respectively; the second data is data in the first N / 2 data, and the second data is N / 2 data away from the first data; and N is the butterfly operation point number corresponding to the butterfly operation unit.

[0012] Each butterfly operation unit is also configured to directly output the plurality of data sum values obtained by performing the addition operation, store the plurality of data difference values obtained by performing the subtraction operation in the RAM, and overwrite the first N / 2 data stored in the RAM.

[0013] Each butterfly operation unit is also configured to read the plurality of data difference values stored in the RAM after the target data is inputted and the plurality of data sum values are all outputted.

[0014] Each butterfly operation unit in the FFT hardware accelerator can realize serial output of the butterfly operation, so that the serial output result can enter the next connected complex multiplier to perform complex multiplication with a complex rotation factor, enter the next connected butterfly operation unit, or enter the next connected butterfly operation unit after the complex real part and the complex imaginary part are exchanged and the complex imaginary part after the exchange is negated. Thus, the FFT hardware accelerator realizes pipeline operation, can process the input data in real time, and output the processed data in real time, improving the real-time performance of the FFT hardware accelerator.

[0015] In an optional embodiment, the FFT hardware accelerator further comprises a system controller; the system controller is configured to configure the FFT point number and the FFT frequency of the FFT processing module for data processing.

[0016] The FFT hardware accelerator can conveniently and flexibly configure the FFT point number and the FFT frequency of the FFT processing module through the system controller, thereby improving the configuration flexibility of the FFT hardware accelerator.

[0017] In an optional embodiment, the FFT hardware accelerator further comprises an address generation module.

[0018] The address generation module is configured to perform address reverse order on the operation result obtained by the FFT processing module, obtain a target operation result, and store the target operation result in an internal storage module.

[0019] In an optional embodiment, the FFT hardware accelerator further comprises a direct memory access (DMA) reading module.

[0020] The DMA reading module is configured to obtain to-be-processed data from an external input buffer when a value of an input write pointer is greater than a value of an input read pointer, and transmit the to-be-processed data to the FFT processing module; the input write pointer is configured to indicate a quantity of currently stored data in the external input buffer; and the input read pointer is configured to indicate a quantity of data that has been processed by the FFT processing module.

[0021] The FFT hardware accelerator further comprises a direct memory access (DMA) read module configured to obtain the to-be-processed data from the external input buffer when the value of the input write pointer is greater than the value of the input read pointer, and transmit the to-be-processed data to the FFT processing module. Since the DMA read module is used to move data in the FFT hardware accelerator, efficient processing of data can be achieved. In addition, since the input write pointer and the input read pointer are used to manage the data input process in the FFT processing module, the FFT operation in the FFT processing module can be started without waiting for the previous FFT operation to end, thereby improving the real-time performance of the FFT hardware accelerator.

[0022] In an optional embodiment, after the to-be-processed data is placed in the external input buffer, the value of the input write pointer is configured. When the DMA read module detects that the value of the input write pointer is greater than the value of the input read pointer, the DMA read module is started and is responsible for loading the to-be-processed data from the external input buffer and transmitting the to-be-processed data to the FFT processing module.

[0023] In an optional embodiment, the FFT hardware accelerator further comprises a direct memory access (DMA) write module and an internal storage module.

[0024] The DMA write module is configured to write the data stored in the internal storage module into an external output buffer when the value of an output read pointer is greater than the value of an output write pointer. The output read pointer is used to indicate the number of data taken out from the internal storage module, and the output write pointer is used to indicate the number of data written into the external output buffer.

[0025] The FFT hardware accelerator further comprises a direct memory access (DMA) write module and an internal storage module. The DMA write module is configured to write the data stored in the internal storage module into an external output buffer when the value of an output read pointer is greater than the value of an output write pointer. Thus, the control of the output data of the FFT hardware accelerator and the real-time output of data can be achieved.

[0026] In a second aspect, an embodiment of the present application provides a data processing method applied to a fast Fourier transform (FFT) hardware accelerator. The method comprises the following steps.

[0027] acquire the to-be-processed data, and determine a target butterfly operation unit from a plurality of butterfly operation units included in the FFT hardware accelerator according to a configured number of FFT points; the plurality of butterfly operation units include even-level butterfly operation units and odd-level butterfly operation units; wherein each odd-level butterfly operation unit is connected with a conversion unit; the conversion unit is configured to exchange a real part and an imaginary part of an operation result of a previous-level butterfly operation unit connected with the conversion unit, and after negating the imaginary part after the exchange, pass the imaginary part to a next-level butterfly operation unit connected with the conversion unit; or the conversion unit is configured to pass an operation result of a previous-level butterfly operation unit connected with the conversion unit to a next-level butterfly operation unit connected with the conversion unit;

[0028] for each level of butterfly operation unit in the target butterfly operation unit, perform first processing on the to-be-processed data based on the butterfly operation unit to obtain a first operation result, and perform second processing on the first operation result based on a complex multiplier or a conversion unit connected with the first-level butterfly operation unit to obtain a second operation result; wherein the complex multiplier is configured to generate a complex rotation factor, and after multiplying an operation result of a previous-level butterfly operation unit connected with the complex multiplier with the complex rotation factor, pass the result to a next-level butterfly operation unit connected with the complex multiplier.

[0029] In an optional embodiment, the first processing on the to-be-processed data based on the butterfly operation unit to obtain a first operation result includes:

[0030] divide the to-be-processed data into at least one target data according to a number of butterfly operation points corresponding to the butterfly operation unit; a length of each target data is N; the N is the number of butterfly operation points corresponding to the butterfly operation unit;

[0031] for each target data, the following operations are performed respectively: when a target data with a length of N is input in series, store a first N / 2 data of the target data in a random access memory (RAM) with a storage capacity of N / 2; for each first data in a second N / 2 data of the target data, perform addition and subtraction operations on the first data and a second data respectively; the second data is a data in the first N / 2 data, and the second data is N / 2 data away from the first data; directly output a plurality of sum values obtained by the addition operation, and store a plurality of difference values obtained by the subtraction operation in the RAM to overwrite the first N / 2 data stored in the RAM; after the target data is completely input and the plurality of sum values are completely output, read the plurality of difference values stored in the RAM;

[0032] The obtained at least one target data respectively corresponds to a plurality of data and values and a plurality of data difference values as a first operation result.

[0033] In an optional embodiment, the method further comprises:

[0034] When the value of the input write pointer is greater than the value of the input read pointer, the data to be processed is obtained from the external input buffer; the input write pointer is used to indicate the amount of data currently stored in the external input buffer; the input read pointer is used to indicate the amount of data that has been processed and completed;

[0035] When the value of the output read pointer is greater than the value of the output write pointer, the data stored in the FFT hardware accelerator is written into the external output buffer; the output read pointer is used to indicate the amount of data taken out from the FFT hardware accelerator, and the output write pointer is used to indicate the amount of data written into the external output buffer.

[0036] In a third aspect, the embodiments of the present application further provide a computer readable storage medium, and the computer readable storage medium stores a computer program. When the computer program is executed by a processor, the data processing method of the second aspect is implemented.

[0037] The technical effects brought by any one of the implementation manners of the second aspect or the third aspect can refer to the technical effects brought by the implementation manners of the first aspect, which will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0039] Figure 1 A relationship diagram of an FFT hardware accelerator and a system provided by the embodiments of the present application;

[0040] Figure 2 A structural diagram of an FFT hardware accelerator provided by the embodiments of the present application;

[0041] Figure 3 A structural diagram of an FFT processing module provided by the embodiments of the present application;

[0042] Figure 4 A flowchart of a data processing method provided by the embodiments of the present application;

[0043] Figure 5A flow chart of processing data by a butterfly operation unit provided for an embodiment of the present application;

[0044] Figure 6 A flow chart of another data processing method provided for an embodiment of the present application. DETAILED DESCRIPTION

[0045] For the purpose of making the purpose, technical scheme and advantages of the present application more clear, the present application will be described in further detail below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative work fall within the scope of protection of the present application.

[0046] It should be noted that the terms "first", "second" and the like in the present application are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0047] The design idea of the embodiments of the present application will be briefly introduced as follows:

[0048] The main core idea of the FFT algorithm is to gradually decompose the N-point sequence into N / 2, and then into two-point DFT. The current FFT algorithm can be divided into two categories: time decimation method and frequency decimation method. The time decimation method directly decomposes the sequence x(n) into odd and even sub-sequences, and realizes the DFT of the entire sequence by calculating the DFT of the sub-sequences; the frequency decimation method decomposes X(k) into even and odd sub-sequences in the frequency domain, and then performs DFT operation on the sub-sequences which are getting shorter and shorter, so as to obtain the FFT flow chart of the entire sequence in the frequency domain. In addition, the frequency decimation method can start operation after storing N / 2 points of data, while the time decimation method can start operation after storing N points of data.

[0049] The commonly used FFT algorithms include base-2 FFT algorithm and base-4 FFT algorithm. Among them, the base-2 FFT algorithm has simple hardware structure and convenient control, but has large amount of calculation, and the base-4 FFT algorithm has small amount of calculation, but can only realize 4-point, 16-point, 64-point and other 4M-point FFT.

[0050] In order to reduce the number of multiplication and addition in operation and to make the hardware structure simple and control convenient, the base-2 frequency decimation method is adopted in the application 2 The FFT hardware accelerator is implemented by using the FFT algorithm, and the FFT hardware accelerator comprises a fast Fourier transform (FFT) processing module, and the FFT processing module comprises a plurality of butterfly operation units, and the plurality of butterfly operation units comprise even-level butterfly operation units and odd-level butterfly operation units. Each odd-level butterfly operation unit is connected with a conversion unit, which is used for exchanging the real part and the imaginary part of the operation result of the upper-level butterfly operation unit connected with the conversion unit, and transmitting the exchanged imaginary part to the lower-level butterfly operation unit connected with the conversion unit after negating the exchanged imaginary part, or transmitting the operation result of the upper-level butterfly operation unit connected with the conversion unit to the lower-level butterfly operation unit connected with the conversion unit. Therefore, the FFT hardware accelerator not only has the characteristics of simple hardware structure and convenient control of the FFT hardware accelerator implemented by using the base-2 FFT algorithm, but also has the advantage of small operation amount of the base-4 FFT algorithm.

[0051] The application will be described in further detail below with reference to the drawings and specific embodiments.

[0052] The term "exemplary" is used herein in the sense of being an example, illustration, or illustration. Any embodiment described as "exemplary" is not necessarily to be construed as being superior to or better than other embodiments. In the description of the embodiments of the application, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0053] Referring to Figure 1 A relationship diagram of an FFT hardware accelerator and a system provided by the embodiments of the application is shown in the following figure. The FFT hardware accelerator exists in the system as a sub-module of the CP subsystem, and is called by the 5th generation reduced instruction set (RISC-V) / digital signal processor (DSP) in the CP subsystem to provide hardware acceleration services for related signal algorithms (such as synchronization capture). As shown in the figure, Figure 1 As shown in the figure, the RISC-V / DSP and the FFT hardware accelerator can interact through the system bus AHB_Bus interface, the RAM and the FFT hardware accelerator can interact through the bus protocol AXI_Bus interface, and the memory built-in self-test (RAMBIST) and the scan can directly interact with the FFT hardware accelerator.

[0054] Since the operation processes of the fast Fourier transform (FFT) algorithm and the inverse fast Fourier transform (IFFT) algorithm are basically the same, the FFT hardware accelerator implementing the FFT algorithm can also implement the IFFT algorithm.

[0055] Referring to Figure 2A hardware structure diagram of an FFT hardware accelerator provided for an embodiment of the present application is shown in FIG. 1. As shown in FIG. 1, the FFT hardware accelerator can include a system controller, a direct memory access (DMA) read module, a fast Fourier transform (FFT) processing module, an address generation module, an internal storage module, and a DMA write module. Figure 2

[0056] The system controller is configured to control the state of the FFT operation on the data in the entire FFT hardware accelerator. The system controller can be configured to configure the number of FFT points and the number of FFTs of the data processed by the FFT processing module, i.e., the system controller can configure the number of FFT points and the number of FFTs calculated by the FFT processing module each time through a register interface.

[0057] The DMA read module is configured to obtain the data to be processed from the external input buffer when the value of the input write pointer is greater than the value of the input read pointer, and transmit the data to be processed to the FFT processing module. The input write pointer is configured to indicate the number of data currently stored in the external input buffer, and the input read pointer is configured to indicate the number of data currently processed by the FFT processing module.

[0058] Specifically, after the data to be processed is placed in the external input buffer, the value of the input write pointer is configured. When the DMA read module detects that the value of the input write pointer is greater than the value of the input read pointer, the DMA read module is started and is responsible for loading the data to be processed from the external input buffer and transmitting the data to the FFT processing module.

[0059] Since the data to be processed is placed in the external input buffer, when the DMA read module detects that the value of the input write pointer is greater than the value of the input read pointer, the DMA read module can be started to load the data to be processed from the external input buffer and provide the data to the FFT processing module. When the FFT processing module receives the data to be processed from the DMA read module, the FFT processing module can perform a base-2 2 The FFT algorithm is configured to perform continuous and pipelined FFT hardware acceleration on the data to be processed, and configure different butterfly operation units to perform different butterfly operations according to the number of FFT points, so as to obtain a cascaded pipelined FFT hardware acceleration architecture design effect, thereby realizing pipelined processing of the data to be processed, improving the real-time performance of the FFT hardware accelerator, and improving the processing efficiency of the FFT hardware accelerator.

[0060] ​The FFT processing module can include a plurality of butterfly operation units, the plurality of butterfly operation units including even-stage butterfly operation units and odd-stage butterfly operation units. Each odd-stage butterfly operation unit is connected with a conversion unit, and the conversion unit is configured to exchange the real part and the imaginary part of the operation result of the upper-stage butterfly operation unit connected with the conversion unit, and after negating the exchanged imaginary part, the negated imaginary part is transmitted to the lower-stage butterfly operation unit connected with the conversion unit, or the operation result of the upper-stage butterfly operation unit connected with the conversion unit is transmitted to the lower-stage butterfly operation unit connected with the conversion unit.

[0061] In addition, the FFT processing module can further include at least one complex multiplier, and each complex multiplier is configured to generate a complex rotation factor, and after multiplying the operation result of the upper-stage butterfly operation unit connected with the complex multiplier by the complex rotation factor, the multiplied result is transmitted to the lower-stage butterfly operation unit connected with the complex multiplier.

[0062] Specifically, Figure 3 The hardware structure diagram of the FFT processing module is shown in FIG. 1. Figure 3 As shown in FIG. 1, the FFT processing module includes 11 butterfly operation units, i.e., bfly0, bfly1, bfly2, bfly3, bfly4, bfly5, bfly6, bfly7, bfly8, bfly9 and bfly10. The bfly0, bfly2, bfly4, bfly6 and bfly8 are respectively connected with a complex multiplier Cordic, and the bfly1, bfly3, bfly5, bfly7 and bfly9 are respectively connected with a conversion unit Shift.

[0063] The Cordic connected with the bfly0 is configured to generate a complex rotation factor, and after multiplying the operation result of the bfly0 by the complex rotation factor, the multiplied result is transmitted to the bfly1; the Cordic connected with the bfly2 is configured to generate a complex rotation factor, and after multiplying the operation result of the bfly2 by the complex rotation factor, the multiplied result is transmitted to the bfly3; the Cordic connected with the bfly4 is configured to generate a complex rotation factor, and after multiplying the operation result of the bfly4 by the complex rotation factor, the multiplied result is transmitted to the bfly5; the Cordic connected with the bfly6 is configured to generate a complex rotation factor, and after multiplying the operation result of the bfly6 by the complex rotation factor, the multiplied result is transmitted to the bfly7; the Cordic connected with the bfly8 is configured to generate a complex rotation factor, and after multiplying the operation result of the bfly8 by the complex rotation factor, the multiplied result is transmitted to the bfly9.

[0064] The Shift connected after bfly1 is used to multiply the operation result of bfly1 by -j and then pass to bfly2 or directly pass the operation result of bfly1 to bfly2; the Shift connected after bfly3 is used to multiply the operation result of bfly3 by -j and then pass to bfly4 or directly pass the operation result of bfly3 to bfly4; the Shift connected after bfly5 is used to multiply the operation result of bfly5 by -j and then pass to bfly6 or directly pass the operation result of bfly5 to bfly6; the Shift connected after bfly7 is used to multiply the operation result of bfly7 by -j and then pass to bfly8 or directly pass the operation result of bfly7 to bfly8; the Shift connected after bfly9 is used to multiply the operation result of bfly9 by -j and then pass to bfly10 or directly pass the operation result of bfly9 to bfly10.

[0065] The shift unit Shift can multiply the operation result of the butterfly operation unit by -j, and multiplying a complex number by -j can be realized by exchanging the real part and the imaginary part of the complex number and then taking the opposite of the sign of the imaginary part.

[0066] Furthermore, each butterfly operation unit is configured to, when serially inputting target data with a length of N, store the first N / 2 data of the target data in a random access memory (RAM) with a storage capacity of N / 2, and, for each first data of the last N / 2 data of the target data, perform addition and subtraction operations on the first data and a second data. The second data is a data in the first N / 2 data and is N / 2 data away from the first data. N is the butterfly operation point number corresponding to the butterfly operation unit.

[0067] Each butterfly operation unit is further configured to directly output the sum of the data obtained by the addition operation, store the difference of the data obtained by the subtraction operation in the RAM, and overwrite the first N / 2 data stored in the RAM. When the input of the target data is completed and the sum of the data is completely output, the difference of the data stored in the RAM is read.

[0068] That is, for each butterfly operation unit, data with a length of N (butterfly operation point number) can be serially input, the first N / 2 complex numbers can be stored in a RAM with a depth of N / 2, and, when the last N / 2 complex numbers are input, addition and subtraction operations are performed on the input data and a data in the first N / 2 data that is N / 2 data away from the input data, the sum of the data is directly output, and the difference of the data is written in the RAM (starting from address 0) to overwrite the previously stored data. When the input of the N data is completed and the output of the N / 2 sum of the data is completed, the N / 2 difference of the data stored in the RAM can be read, thereby realizing the serial output of the butterfly operation.

[0069] Specifically, such as Figure 3 As shown, the FFT processing module includes 11 butterfly operation units. bfly0 corresponds to 2048 butterfly operation points, bfly1 corresponds to 1024 butterfly operation points, bfly2 corresponds to 512 butterfly operation points, bfly3 corresponds to 256 butterfly operation points, bfly4 corresponds to 128 butterfly operation points, bfly5 corresponds to 64 butterfly operation points, bfly6 corresponds to 32 butterfly operation points, bfly7 corresponds to 16 butterfly operation points, bfly8 corresponds to 8 butterfly operation points, bfly9 corresponds to 4 butterfly operation points, and bfly10 corresponds to 2 butterfly operation points.

[0070] Taking bfly0 as an example, let's explain in detail the data processing process of the butterfly arithmetic unit mentioned above:

[0071] After inputting target data of length 2048, bfly0 can use RAM with a storage capacity of 1024 bytes to store the first 1024 bytes of the target data. For each of the last 1024 bytes of the target data, it performs addition and subtraction operations on the data and the data within 1024 bytes of the previous 1024 bytes respectively. The sum of the multiple data obtained from the addition operation is directly output, and the difference of the multiple data obtained from the subtraction operation is stored in RAM, overwriting the original first 1024 data in RAM. When all 2048 data are input, the addition and subtraction operations end, and the 1024 sums of the addition operation are also output. At this point, the 1024 differences stored in RAM are read, thus realizing the serial output of bfly0.

[0072] The address generation module WAddr Gen is used to reverse the address of the operation results obtained by the FFT processing module to obtain the target operation result, and then store the target operation result in the internal storage module Buffer RAM.

[0073] Specifically, the FFT processing module executes a frequency-decimation FFT algorithm, and the resulting operation is output in reverse order. The address generation module WAddr Gen can reverse the address of the operation result to generate the storage address of the operation result in the internal storage module Buffer RAM.

[0074] The internal storage module Buffer RAM is an internal storage space, including four RAMs, used to store the FFT data after calculation. Each RAM can store a maximum of 2048-point FFT data, and read and write are performed in a ping-pong operation mode. The Buffer RAM can store the operation results of four FFTs. When the external bus is busy, causing data to be unable to be written into the external output buffer Output Buffer in time, the operation data is temporarily stored in the Buffer RAM. When the Buffer RAM is full of data, the data operation of the FFT processing module is paused until the data is taken away from the Buffer RAM and written into the Output Buffer, and then the data operation of the FFT processing module continues.

[0075] The DMA write module is used to write the data stored in the internal storage module into the external output buffer when the value of the output read pointer is greater than the value of the output write pointer. The output read pointer is used to indicate the number of data taken from the internal storage module, and the output write pointer is used to indicate the number of data written into the external output buffer.

[0076] Based on Figure 1 and Figure 2 It can be known that the FFT hardware accelerator is mounted on the AHB bus of the CP subsystem through the internal system controller AHB Slave. The main controller RISC-V / DSP can access the internal registers of the FFT hardware accelerator through the AHB bus to complete the configuration of operation parameters, the start / stop of the FFT hardware accelerator, the query of the interrupt state and the like.

[0077] The FFT hardware accelerator is mounted on the AXI bus of the CP subsystem through the internal DMA module (the DMA read module and the DMA write module). After being started, the DMA module can automatically take data from the specified RAM space and write the operation results of the FFT processing module into the specified RAM space.

[0078] Specifically, the system controller AHB Slave can control the DMA read module, the FFT processing module, the address generation module, the internal storage module and the DMA write module inside the FFT hardware accelerator through a register interface. The DMA read module can read data from the external input buffer of the FFT hardware accelerator, transmit the data to the FFT processing module, the FFT processing module can process the data after receiving the data, obtain the corresponding operation result, and transmit the operation result to the address generation module, the address generation module can transmit the operation result after being output in reverse order to the internal storage module after reversing the address of the operation result, the internal storage module can store the operation result, and the DMA write module can obtain the operation result from the internal storage and write it to the external output buffer of the FFT hardware accelerator. Inside the FFT hardware accelerator, BIST / SCAN can interact with RAMBist and Scan in the system.

[0079] The FFT hardware accelerator provided in the embodiments of the present application adopts the base-2 2 The FFT algorithm, and a conversion unit is connected after each odd stage butterfly operation unit and the last stage butterfly operation unit in the plurality of butterfly operation units, so that the base-2 FFT algorithm can not only retain the characteristics of simple hardware structure and convenient control, but also has the advantage of small operation amount of the base-4 FFT algorithm, thereby achieving the purpose of reducing the number of multiplications and additions in the operation, and realizing simple hardware structure and convenient control. At the same time, full pipelining operation is realized, data transfer is performed through the DMA module inside the FFT hardware accelerator, base-2 2 FFT pipelined butterfly operation, and interaction with the host computer through interruption, so that real-time full processing of a large amount of data is realized through the pipeline, and the real-time performance of the FFT hardware accelerator is improved. Moreover, since the present application realizes the pipelined FFT structure, the input data can be processed in real time, the output data can be updated in real time, and the FFT point number and the FFT number of each calculation can be configured, and up to 255 times of FFT operation can be performed each time, thereby improving the configuration flexibility of the FFT hardware accelerator.

[0080] In some embodiments, the data processing method performed by the FFT hardware accelerator described above can refer to the method shown in Figure 4 The method comprises the following steps:

[0081] In step S401, the data to be processed is obtained, and the target butterfly operation unit is determined from the plurality of butterfly operation units included in the FFT hardware accelerator according to the configured FFT point number.

[0082] For example, when 11 butterfly operation units are included in the FFT hardware accelerator, and the butterfly operation point numbers corresponding to the butterfly operation units bfly0, bfly1, bfly2, bfly3, bfly4, bfly5, bfly6, bfly7, bfly8, bfly9 and bfly10 are 2048, 1024, 512, 256, 128, 64, 32, 16, 8, 4 and 2 respectively, if the configured FFT point number is 2048, bfly0, bfly1, bfly2, bfly3, bfly4, bfly5, bfly6, bfly7, bfly8, bfly9 and bfly10 can be used as target butterfly operation units; if the configured FFT point number is 1024, bfly1, bfly2, bfly3, bfly4, bfly5, bfly6, bfly7, bfly8, bfly9 and bfly10 can be used as target butterfly operation units; if the configured FFT point number is 256, bfly3, bfly4, bfly5, bfly6, bfly7, bfly8, bfly9 and bfly10 can be used as target butterfly operation units.

[0083] The plurality of butterfly operation units include even-level butterfly operation units and odd-level butterfly operation units. Each odd-level butterfly operation unit is connected with a conversion unit. The conversion unit is configured to exchange the real part and the imaginary part of the operation result of the upper-level butterfly operation unit connected with the conversion unit, and transmit the imaginary part after negating to the lower-level butterfly operation unit connected with the conversion unit; or transmit the operation result of the upper-level butterfly operation unit connected with the conversion unit to the lower-level butterfly operation unit connected with the conversion unit.

[0084] In step S402, the target butterfly operation unit is used to process the to-be-processed data to obtain a target operation result.

[0085] The target butterfly operation unit, the complex multiplier or the conversion unit is used to process the to-be-processed data to obtain a target operation result. The complex multiplier is configured to generate a complex rotation factor, and multiply the operation result of the upper-level butterfly operation unit connected with the complex multiplier by the complex rotation factor to obtain a result, and transmit the result to the lower-level butterfly operation unit connected with the complex multiplier.

[0086] Specifically, the first-level butterfly operation unit in the target butterfly operation unit is used to process the to-be-processed data to obtain a first operation result.

[0087] If the first stage butterfly operation unit is the last stage butterfly operation unit in the target butterfly operation unit, the first operation result is taken as the target operation result; otherwise, the first operation result is subjected to a second processing based on the complex multiplier or conversion unit connected with the first stage butterfly operation unit, a second operation result is obtained, the second operation result is taken as the data to be processed, and the process of subjecting the data to be processed to the first processing based on the other stage butterfly operation units in the target butterfly operation unit, obtaining the first operation result, subjecting the first operation result to the second processing based on the complex multiplier or conversion unit connected with the other stage butterfly operation unit, and obtaining the second operation result is sequentially performed until the other stage butterfly operation unit is the last stage butterfly operation unit in the target butterfly operation unit, and the obtained first operation result is taken as the target operation result.

[0088] For each butterfly operation unit in the target butterfly operation unit, the specific process of subjecting the data to be processed to the first processing to obtain the first operation result can be as shown in Figure 5

[0089] In step S501, the data to be processed is divided into at least one target data according to the butterfly operation point number corresponding to the butterfly operation unit.

[0090] Each target data has a length of N, and N is the butterfly operation point number corresponding to the butterfly operation unit.

[0091] In step S502, for each target data, when the target data with a length of N is input in series, the first N / 2 data of the target data is stored in the RAM with a storage data amount of N / 2, and each first data in the last N / 2 data of the target data is subjected to addition and subtraction operations with a second data.

[0092] The second data is a data in the first N / 2 data, and the second data is N / 2 data away from the first data, and N is the butterfly operation point number corresponding to the butterfly operation unit.

[0093] In step S503, the multiple data sums obtained by the addition operation are directly output, and the multiple data differences obtained by the subtraction operation are stored in the RAM and overwrite the first N / 2 data stored in the RAM.

[0094] In step S504, when the target data is input and the multiple data sums are all output, the multiple data differences stored in the RAM are read.

[0095] In step S505, the multiple data sums and the multiple data differences corresponding to the at least one target data are taken as the first operation result.

[0096] ​For example, when the hardware structure of the butterfly operation unit, complex multiplier, and conversion unit included in the FFT hardware accelerator is as follows: Figure 3 As shown, if the configured FFT points are 64, then the target butterfly operation units for processing the data to be processed can be determined as bfly5, bfly6, bfly7, bfly8, bfly9 and bfly10. Specifically, the data to be processed can be serially input into bfly5, and the length of the input data to be processed is 64. In bfly5, the first 32 data points of the data to be processed can be stored in RAM with a storage capacity of 32. For each data point in the last 32 data points of the data to be processed, addition and subtraction operations can be performed on the data point and the data point 32 data points away from the data point in the first 32 data points. The sum of the 32 data points obtained by the addition operation is directly output, and the difference of the 32 data points obtained by the subtraction operation is stored in RAM, overwriting the first 32 data points stored in RAM. When all the data to be processed has been input, the addition and subtraction operations are completed, and the sum of the 32 data points output by the addition operation is also output. At this time, the 32 difference values ​​stored in RAM are read out, and the obtained 32 sum values ​​and 32 difference values ​​are used as the operation result 1 and transmitted to Shift connected after bfly5.

[0097] After receiving the result 1, the Shift key connected to bfly5 can directly transmit the result 1 to bfly6, or multiply the result 1 by -j and transmit it to bfly6. Upon receiving the result 1 (length 64), bfly6 can divide it into two target data parts, each 32 bytes long. For each target data part, the first 16 bytes can be stored in RAM with a storage capacity of 16 bytes. For each of the last 16 bytes, addition and subtraction operations can be performed between this data and a data point 16 bytes away from it in the previous 16 data parts. The sum of the 16 data parts obtained from the addition operation is directly output, and the difference of the 16 data parts obtained from the subtraction operation is stored in RAM, overwriting the first 16 data parts stored in RAM. When all the target data has been input, the addition and subtraction operations are complete, and the 16 sums from the addition operation are also output. At this point, the 16 difference values ​​stored in RAM are read.

[0098] The bfly6 can transmit the 32 data sum values and the 32 data difference values obtained based on the above processing as operation result 2 to the Cordic connected after the bfly6, the Cordic can generate a complex rotation factor, and transmit the operation result 2 multiplied by the complex rotation factor to the bfly7. The bfly7 can divide the operation result 2 with a length of 64 into 4 target data, and each target data has a length of 16. For each target data, 8 data sum values and 8 data difference values corresponding to each target data can be obtained based on the same processing process as the bfly6.

[0099] The bfly7 can transmit the 32 data sum values and the 32 data difference values obtained based on the above processing as operation result 3 to the Shift connected after the bfly7, the Shift can transmit the operation result 3 directly to the bfly8, or multiply the operation result 3 by -j and transmit it to the bfly8. The bfly8 can divide the operation result 3 with a length of 64 into 8 target data, and each target data has a length of 8. For each target data, 4 data sum values and 4 data difference values corresponding to each target data can be obtained based on the same processing process as the bfly6.

[0100] The bfly8 can transmit the 32 data sum values and the 32 data difference values obtained based on the above processing as operation result 4 to the Cordic connected after the bfly8, the Cordic can generate a complex rotation factor, and transmit the operation result 4 multiplied by the complex rotation factor to the bfly9. The bfly9 can divide the operation result 4 with a length of 64 into 16 target data, and each target data has a length of 4. For each target data, 2 data sum values and 2 data difference values corresponding to each target data can be obtained based on the same processing process as the bfly6.

[0101] The bfly9 can transmit the 32 data sum values and the 32 data difference values obtained based on the above processing as operation result 5 to the Shift connected after the bfly9, the Shift can transmit the operation result 5 directly to the bfly10, or multiply the operation result 5 by -j and transmit it to the bfly10. The bfly10 can divide the operation result 5 with a length of 64 into 32 target data, and each target data has a length of 2. For each target data, 1 data sum value and 1 data difference value corresponding to each target data can be obtained based on the same processing process as the bfly6, and the 32 data sum values and the 32 data difference values obtained based on the above processing are taken as target data results.

[0102] Similarly, when the configured FFT point number is 2048, the target butterfly operation units for processing the to-be-processed data can be bfly0, bfly1, bfly2, bfly3, bfly4, bfly5, bfly6, bfly7, bfly8, bfly9 and bfly10, and the to-be-processed data is processed based on the target butterfly operation units bfly, the complex multiplier Cordic and the conversion unit Shift to obtain a target operation result. The process is similar to the process when the configured FFT point number is 64, and details are not repeated here.

[0103] In an embodiment, the data processing method performed by the FFT hardware accelerator described above can also refer to Figure 6 as shown, comprising the following steps:

[0104] Step S601, when the value of the input write pointer is greater than the value of the input read pointer, the DMA reading module obtains the to-be-processed data from the external input buffer, and transmits the to-be-processed data to the FFT processing module.

[0105] Specifically, the to-be-processed data processed in the input FFT hardware accelerator can be placed in the external input buffer Input Buffer of the FFT hardware accelerator, and the Input Buffer can be managed by two pointers, an input read pointer in_rd_ptr and an input write pointer in_wr_ptr. The in_wr_ptr is used to indicate the number of input data currently prepared, that is, the number of data currently stored in the Input Buffer; the in_rd_ptr is used to indicate the number of FFTs that have been processed by the FFT processing module in the FFT hardware accelerator, that is, the number of data that have been processed by the FFT processing module, and the in_rd_ptr is incremented by 1 after processing one FFT data.

[0106] After placing the input to-be-processed data in the Input Buffer, the value of the in_wr_ptr is configured. After detecting that the in_wr_ptr> in_rd_ptr, the DMA reading module in the FFT hardware accelerator is started, which is responsible for obtaining the to-be-processed data from the Input Buffer and transmitting the to-be-processed data to the FFT processing module.

[0107] Step S602, based on the target butterfly operation unit determined from the multiple butterfly operation units included in the FFT processing module, the to-be-processed data is processed to obtain a target operation result.

[0108] After receiving the event to be processed, the FFT processing module can determine the target butterfly operation unit from the plurality of butterfly operation units according to the configured FFT point number, and process the data to be processed based on the target butterfly operation unit, the complex multiplier or the conversion unit to obtain the target operation result.

[0109] The specific process of processing the data to be processed based on the target butterfly operation unit, the complex multiplier or the conversion unit to obtain the target operation result can refer to the step S402 described above, and will not be repeated here.

[0110] In step S603, when the difference between the input write pointer and the input read pointer is not greater than the first threshold value, the data to be processed is continuously written into the external input buffer.

[0111] The first threshold value in_buf_the is set, and when in_wr_ptr-in_rd_ptr<=in_buf_the, the in_buf_free interrupt is generated, and the data to be processed is continuously written into the Input Buffer.

[0112] In step S604, when the value of the output read pointer is greater than the value of the output write pointer, the DMA write module writes the target operation result stored in the internal storage module into the external output buffer.

[0113] After the FFT processing module outputs the target operation result, the target operation result can be transmitted to the address generation module. After the address generation module performs address reverse order on the target operation result, the target operation result after the reverse output can be transmitted to the internal storage module, so that the internal storage module stores the target operation result, and the DMA write module can write the target operation result out to the external output buffer after obtaining the target operation result from the internal storage module.

[0114] Specifically, the DMA write module can control the data in the internal storage module Buffer RAM to be written out to the external output buffer Output Buffer, and the Output Buffer is managed by two pointers, an output write pointer out_wr_ptr and an output read pointer out_rd_ptr. The out_rd_ptr is used to indicate the number of target received, and inform the FFT processing module that the data can be output to the position of the out_rd_ptr, i.e., indicate the number of data taken out from the Buffer RAM. The out_wr_ptr is used to indicate the number of FFTs that have been output, i.e., indicate the number of data written into the Output Buffer, and the out_wr_ptr is incremented by 1 every time a data is written into the Output Buffer. After detecting that the out_rd_ptr>out_wr_ptr, the DMA read module is started, and is responsible for writing the operation results stored in the Buffer RAM out to the Output Buffer.

[0115] In step S605, when the difference between the output read pointer and the output write pointer is not greater than a set second threshold value, the target operation result is taken out from the external input buffer.

[0116] The second threshold value out_buf_the is set, and when out_rd_ptr-out_wr_ptr<=out_buf_the, the out_buf_ready interrupt is generated, indicating that the storage data in the Output Buffer is close to full, and the output data needs to be taken out and processed as soon as possible.

[0117] The data processing method provided by the embodiment of the present application adopts the base-2 frequency extraction FFT algorithm, and a conversion unit is connected after each odd stage butterfly operation unit and the last stage butterfly operation unit in the FFT hardware accelerator, so that the structure of the FFT hardware accelerator is simple, the control is convenient, and the operation amount is small. 2 The FFT algorithm, and a conversion unit is connected after each odd stage butterfly operation unit and the last stage butterfly operation unit in the FFT hardware accelerator, so that the structure of the FFT hardware accelerator is simple, the control is convenient, and the operation amount is small.

[0118] According to an aspect of the present application, a computer program product or computer program is provided, which includes computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions, so that the computer device executes the data processing method in the above embodiment.

[0119] A program product can employ any combination of one or more computer-readable media. The computer-readable media can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include the following: an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0120] The above description is only specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered in the protection scope of the present application.

Claims

1. A fast Fourier transform (FFT) hardware accelerator, comprising: The FFT processing module comprises a plurality of butterfly operation units; the plurality of butterfly operation units comprise even-stage butterfly operation units and odd-stage butterfly operation units; wherein each odd-stage butterfly operation unit is connected with a conversion unit; the conversion unit is used for exchanging the real part and the imaginary part of the operation result of the upper-stage butterfly operation unit connected with the conversion unit, and after negating the exchanged imaginary part, the negated imaginary part is transmitted to the lower-stage butterfly operation unit connected with the conversion unit; or the conversion unit is used for transmitting the operation result of the upper-stage butterfly operation unit connected with the conversion unit to the lower-stage butterfly operation unit connected with the conversion unit. Each butterfly operation unit is used for, when a target data with a serial input length of N is input, storing the first N / 2 data of the target data in a random access memory (RAM) with a storage data amount of N / 2, and performing addition and subtraction operations on each first data in the last N / 2 data of the target data and a second data; the second data is a data in the first N / 2 data, and the second data is N / 2 data away from the first data; N is the butterfly operation point number corresponding to the butterfly operation unit. Each butterfly operation unit is further used for directly outputting a plurality of data sums obtained by the addition operation, and storing a plurality of data differences obtained by the subtraction operation in the RAM and covering the first N / 2 data stored in the RAM. Each butterfly operation unit is further used for reading the plurality of data differences stored in the RAM after the target data is completely input and the plurality of data sums are completely output.

2. The FFT hardware accelerator of claim 1, wherein, The FFT processing module further comprises at least one complex multiplier. Each complex multiplier is used for generating a complex rotation factor, and performing complex multiplication on the operation result of the upper-stage butterfly operation unit connected with the complex multiplier and the complex rotation factor, and transmitting the result of the complex multiplication to the lower-stage butterfly operation unit connected with the complex multiplier.

3. The FFT hardware accelerator of claim 1, wherein, The FFT hardware accelerator further comprises a system controller; the system controller is used for configuring the FFT point number and the FFT frequency of the FFT processing module for data processing.

4. The FFT hardware accelerator of claim 1, wherein, The FFT hardware accelerator further comprises an address generation module. The address generation module is used for performing address reverse order on the operation result obtained by the FFT processing module, obtaining a target operation result, and storing the target operation result in an internal storage module.

5. The FFT hardware accelerator of claim 1, wherein, The FFT hardware accelerator further comprises a direct memory access (DMA) read module. The DMA read module is used for, when the value of an input write pointer is greater than the value of an input read pointer, obtaining to-be-processed data from an external input buffer, and transmitting the to-be-processed data to the FFT processing module; the input write pointer is used for indicating the number of currently stored data in the external input buffer; and the input read pointer is used for indicating the number of data that have been completely processed by the FFT processing module.

6. The FFT hardware accelerator of claim 5, wherein, After the to-be-processed data is placed in the external input buffer, a value of the input write pointer is configured, and when the DMA read module detects that the value of the input write pointer is greater than the value of the input read pointer, the DMA read module is started and is responsible for loading the to-be-processed data from the external input buffer into the FFT processing module.

7. The FFT hardware accelerator of claim 1, wherein, The FFT hardware accelerator further comprises a direct memory access (DMA) write module and an internal storage module; The DMA write module is configured to write data stored in the internal storage module into an external output buffer when a value of an output read pointer is greater than a value of an output write pointer; the output read pointer is used to indicate the number of data taken out from the internal storage module, and the output write pointer is used to indicate the number of data written into the external output buffer.

8. A method of digital signal processing, characterized by, The method is applied to a fast Fourier transform (FFT) hardware accelerator, and the method comprises: Obtaining to-be-processed data, and determining a target butterfly operation unit from a plurality of butterfly operation units included in the FFT hardware accelerator according to a configured FFT point number; the plurality of butterfly operation units comprise even-level butterfly operation units and odd-level butterfly operation units; wherein each odd-level butterfly operation unit is connected with a conversion unit; the conversion unit is configured to exchange a complex real part and a complex imaginary part of an operation result of an upper-level butterfly operation unit connected with the conversion unit, and after negating the exchanged complex imaginary part, the negated complex imaginary part is transmitted to a lower-level butterfly operation unit connected with the conversion unit; or the conversion unit is configured to transmit an operation result of an upper-level butterfly operation unit connected with the conversion unit to a lower-level butterfly operation unit connected with the conversion unit; For each butterfly operation unit in the target butterfly operation unit, a first operation is performed on the to-be-processed data based on the butterfly operation unit to obtain a first operation result, and a second operation is performed on the first operation result based on a complex multiplier or a conversion unit connected with the butterfly operation unit to obtain a second operation result; wherein the complex multiplier is configured to generate a complex rotation factor, and after multiplying an operation result of an upper-level butterfly operation unit connected with the complex multiplier with the complex rotation factor, the multiplied result is transmitted to a lower-level butterfly operation unit connected with the complex multiplier; The first operation performed on the to-be-processed data based on the butterfly operation unit to obtain the first operation result comprises: According to a butterfly operation point number corresponding to the butterfly operation unit, the to-be-processed data is divided into at least one target data; the length of each target data is N; the N is the butterfly operation point number corresponding to the butterfly operation unit. For each target data, the following operations are performed: when the length of the serial input target data is N, the first N / 2 data of the target data are stored in a random access memory (RAM) with a storage capacity of N / 2; for each first data in the last N / 2 data of the target data, the first data is subjected to addition and subtraction operations with a second data, respectively; the second data is a data in the first N / 2 data, and the second data is N / 2 data away from the first data; the sum values obtained by the addition operations are directly outputted, and the difference values obtained by the subtraction operations are stored in the RAM, and the first N / 2 data stored in the RAM are overwritten; after the target data is inputted completely and the sum values are outputted completely, the difference values stored in the RAM are read. The sum values and the difference values corresponding to the at least one target data are taken as first operation results.

9. The method of claim 8, wherein, The method further comprises: When the value of an input write pointer is greater than the value of an input read pointer, the data to be processed is obtained from an external input buffer; the input write pointer is used to indicate the number of data currently stored in the external input buffer; the input read pointer is used to indicate the number of data that has been processed completely; When the value of an output read pointer is greater than the value of an output write pointer, the data stored in the FFT hardware accelerator is written into an external output buffer; the output read pointer is used to indicate the number of data taken out from the FFT hardware accelerator, and the output write pointer is used to indicate the number of data written into the external output buffer.

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