DDR expansion device and control method, device and medium

Abstract

The application discloses a DDR extension device and a control method and device thereof and a medium, relates to the field of DDR, and aims to increase the number of mounted DDR particles while keeping the DDR controller signal line unchanged. The DDR extension device provided by the application is characterized in that when the chip selection signal end CS of the DDR controller is at a high level, the chip selection signal end CS of the first DDR particle and the second DDR particle is at a high level; when the chip selection signal end CS of the DDR controller is at a low level, the chip selection signal end CS of the third DDR particle and the fourth DDR particle is at a high level through an inverter. The function mode of the BANK GROUP address selection signal end BG and the chip selection signal end CS between the DDR controller and the DDR particle is changed, the number of mounted DDR particles is increased, and the number of mounted DDR particles is doubled in any data bit width.

Description

Technical Field

[0001] This application relates to the field of DDR, and in particular to a DDR extension device and control method, apparatus, and medium. Background Technology

[0002] Double Data Rate Synchronous Dynamic Random Access Memory (DDR) is a type of synchronous dynamic random-access memory (SDRAM) with twice the data transfer rate, meaning its data transfer speed is twice the system clock frequency. Due to this increased speed, its transfer performance is superior to traditional SDRAM. A traditional DDR controller architecture with DDR chips mounted on it is shown in the diagram below. Figure 1 As shown in the diagram, the internal structure of the DDR chip is as follows: Figure 2 As shown, Figure 1 The DDR controller is connected to the DDR chip via signal lines, where ADDR[17:0] is the address signal, CS is the DDR chip select signal, BA[1:0] is the BANK address select signal, DQ[31:0] is the data signal, and BG[0] and BG[1] are the BANK GROUP address select signals.

[0003] Since the data width of DDR chips is only 16 bits and the data width of DDR controller is 32 bits, two DDR chips are mounted on the DDR controller. The lower 16-bit data signal DQ[15:0] of the DDR controller is connected to the data signal DQ[15:0] of the first DDR chip, and the higher 16-bit data signal DQ[31:16] of the DDR controller is connected to the data signal DQ[15:0] of the second DDR chip. The address signal ADDR[17:0] and the address selection signal BA[1:0] are connected to both DDR chips at the same time.

[0004] Figure 2 The DDR chips divide the storage space into two large blocks, namely BANK GROUP1 and BANK GROUP2. Figure 1 The BG[0] and BG[1] address selection signals are used to select the BANK GROUP address of the two DDR chips respectively. When BG[0] is 1'b1, BANK GROUP1 in the first DDR chip is selected, and when BG[0] is 1'b0, BANK GROUP2 in the first DDR chip is selected; when BG[1] is 1'b1, BANK GROUP1 in the second DDR chip is selected, and when BG[1] is 1'b0, BANK GROUP2 in the second DDR chip is selected.

[0005] The DDR controller and DDR chips are connected to complete the functions of DDR read / write and data storage. The number of DDR chips is determined by the data width of the DDR controller and DDR chips. Therefore, the total capacity of the DDR chips is also fixed. Since the data width of the DDR controller and DDR chips is fixed, the number of DDR chips that the CPU can read and write through the DDR controller is also fixed.

[0006] Therefore, how to increase the number of DDR chips mounted while keeping the DDR controller signal lines unchanged, thereby expanding the DDR memory capacity mounted by the DDR controller, is a technical problem that urgently needs to be solved by those in the field. Summary of the Invention

[0007] The purpose of this application is to provide a DDR expansion device that increases the number of mounted DDR chips while keeping the DDR controller signal lines unchanged, thereby expanding the DDR memory capacity mounted by the DDR controller.

[0008] To address the aforementioned technical problems, this application provides a DDR expansion device, comprising:

[0009] DDR controller, first DDR chip, second DDR chip, third DDR chip, fourth DDR chip, inverter;

[0010] The DDR controller's chip select signal terminal and first bank group address select signal terminal are connected to the chip select signal terminals and address select signal terminals of the first and second DDR chips, respectively. The DDR controller's chip select signal terminal is connected to the chip select signal terminals of the third and fourth DDR chips via an inverter. The DDR controller's second bank group address select signal terminal is connected to the address select signal terminals of the third and fourth DDR chips. The DDR controller's low-order data signal is connected to the data signal terminals of the first and third DDR chips, and its high-order data signal is connected to the data signal terminals of the second and fourth DDR chips. The DDR controller's bank address select signal terminal and address signal terminal are connected to the bank address select signal terminals and address signal terminals of the first, second, third, and fourth DDR chips, respectively. The DDR controller's chip select signal terminal (CS) is used to output high-level and low-level signals.

[0011] Preferably, the above-mentioned DDR expansion device further includes: a processor;

[0012] The processor is connected to the DDR controller.

[0013] Preferably, in the above-mentioned DDR expansion device, the processor includes a first processor, a second processor, and further includes an arbitrator;

[0014] The first processor, the second processor, and the arbitrator are connected to each other, and the arbitrator is connected to the DDR controller.

[0015] Preferably, in the above-mentioned DDR expansion device, the arbitrator is connected to the first processor and the second processor via a system bus.

[0016] To address the aforementioned technical problems, this application also provides a control method for a DDR expansion device, applied to a DDR expansion device, comprising: a DDR controller, a first DDR chip, a second DDR chip, a third DDR chip, a fourth DDR chip, and an inverter; the chip select signal terminal and the first BANK GROUP address selection signal terminal of the DDR controller are respectively connected to the chip select signal terminal and the address selection signal terminal of the first DDR chip and the second DDR chip; the chip select signal terminal of the DDR controller is connected to the chip select signal terminals of the third DDR chip and the fourth DDR chip via the inverter; the second BANK GROUP address selection signal terminal of the DDR controller is connected to the address selection signal terminals of the third DDR chip and the fourth DDR chip; the low-order data signal of the DDR controller is connected to the data signal terminals of the first DDR chip and the third DDR chip; the high-order data signal of the DDR controller is connected to the data signal terminals of the second DDR chip and the fourth DDR chip; and the BANK address selection signal terminal and the address signal terminal of the DDR controller are respectively connected to the BANK address selection signal terminal and the address signal terminal of the first DDR chip, the second DDR chip, the third DDR chip, and the fourth DDR chip.

[0017] This method includes:

[0018] Determine which DDR chip needs to be selected for connection;

[0019] If it is necessary to connect the first DDR chip and the second DDR chip, the chip select signal terminal should output a high-level signal.

[0020] If a third or fourth DDR chip needs to be connected, the chip select signal terminal should output a low-level signal.

[0021] Preferably, in the control method of the above-mentioned DDR expansion device, the DDR expansion device further includes: a first processor, a second processor, and an arbitrator; the first processor and the second processor are connected to the arbitrator, and the arbitrator is connected to the DDR controller;

[0022] To determine which DDR chip needs to be selected for connection, the following factors must be considered:

[0023] Receive the startup status of the first and second processors sent by the arbitrator;

[0024] If the first processor and the second processor start simultaneously, determine which processor the arbitrator is currently selecting;

[0025] If the first processor is selected, it is determined that the first DDR chip and the second DDR chip need to be connected.

[0026] If the second processor is selected, it is determined that a third and fourth DDR chip need to be connected.

[0027] Preferably, in the above-described control method for the DDR expansion device, if only the first processor or only the second processor is started, it further includes:

[0028] Determine the DDR chips that the currently booted processor needs to read or write;

[0029] If it is necessary to read or write the first DDR chip and the second DDR chip, it is determined that the first DDR chip and the second DDR chip need to be connected.

[0030] If it is necessary to read or write the third and fourth DDR chips, it is determined that the third and fourth DDR chips need to be connected.

[0031] To address the aforementioned technical problems, this application also provides a control device for a DDR expansion device, applied to a DDR expansion device, comprising: a DDR controller, a first DDR chip, a second DDR chip, a third DDR chip, a fourth DDR chip, and an inverter; the chip select signal terminal and the first BANK GROUP address selection signal terminal of the DDR controller are respectively connected to the chip select signal terminal and the address selection signal terminal of the first DDR chip and the second DDR chip; the chip select signal terminal of the DDR controller is connected to the chip select signal terminals of the third DDR chip and the fourth DDR chip via the inverter; the second BANK GROUP address selection signal terminal of the DDR controller is connected to the address selection signal terminals of the third DDR chip and the fourth DDR chip; the low-order data signal of the DDR controller is connected to the data signal terminals of the first DDR chip and the third DDR chip; the high-order data signal of the DDR controller is connected to the data signal terminals of the second DDR chip and the fourth DDR chip; and the BANK address selection signal terminal and the address signal terminal of the DDR controller are respectively connected to the BANK address selection signal terminal and the address signal terminal of the first DDR chip, the second DDR chip, the third DDR chip, and the fourth DDR chip.

[0032] This device includes:

[0033] The judgment module is used to determine the DDR chip that needs to be accessed at the current time;

[0034] The first selection module is used to control the chip select signal terminal to output a high-level signal if the first DDR chip and the second DDR chip need to be connected.

[0035] The second selection module is used to control the chip select signal terminal to output a low-level signal if a third or fourth DDR chip needs to be connected.

[0036] To address the aforementioned technical problems, this application also provides a control device for a DDR expansion device, comprising:

[0037] Memory, used to store computer programs;

[0038] A processor for executing a computer program to implement the steps of the control method for the DDR extension device as claimed in any one of claims 5 to 7.

[0039] To address the aforementioned technical problems, this application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the control method for a DDR extension device as described in any one of claims 5 to 7.

[0040] The DDR expansion device provided in this application includes: a DDR controller, a first DDR chip, a second DDR chip, a third DDR chip, a fourth DDR chip, and an inverter. The DDR chips are connected under a high-level chip select signal. Therefore, when the chip select signal terminal CS of the DDR controller is high, the chip select signal terminals CS of the first and second DDR chips are also high. After passing through the inverter, the chip select signal terminals CS of the third and fourth DDR chips are low, and at this time, the first and second DDR chips are connected. When the chip select signal terminal CS of the DDR controller is low, the chip select signal terminals CS of the first and second DDR chips are also low. After passing through the inverter, the chip select signal terminals CS of the third and fourth DDR chips are high, and at this time, the third and fourth DDR chips are connected. With a fixed data bit width for both the DDR controller and the DDR chips, the number of DDR chips that can be mounted is increased by changing the operation of the BANK GROUP address selection signal (BG) and chip select signal (CS) between the DDR controller and the DDR chips. This allows the number of mounted DDR chips to be doubled regardless of the data bit width, thereby expanding the DDR storage capacity mounted by the DDR controller. This changes the previous situation where the number of DDR chips could only be determined by the data bit width of the DDR controller and the DDR chips.

[0041] In addition, this application also provides a control method, device and medium for a DDR expansion device, which corresponds to the above-mentioned DDR expansion device and has the same effect. Attached Figure Description

[0042] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of an existing DDR mount;

[0044] Figure 2 This is a diagram of the internal structure of a DDR chip;

[0045] Figure 3 A structural diagram of a DDR expansion device provided in an embodiment of this application;

[0046] Figure 4 A flowchart illustrating a control method for a DDR expansion device provided in this application embodiment;

[0047] Figure 5 A structural diagram of a control device for a DDR expansion device provided in an embodiment of this application;

[0048] Figure 6 A structural diagram of a control device for another DDR expansion device provided in an embodiment of this application.

[0049] The reference numerals in the attached diagram are as follows: 11 is an inverter, 12 is a DDR controller, 13 is the first DDR chip, 14 is the second DDR chip, 15 is the third DDR chip, 16 is the fourth DDR chip, 17 is an arbitrator, 18 is the first processor, and 19 is the second processor. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0051] The core of this application is to provide a DDR expansion device and control method, device, and medium.

[0052] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0053] Desktop computer systems have evolved to primarily use DDR SDRAM, or Double Data Rate Synchronous Dynamic Random Access Memory, often abbreviated as DDR. DDR consists of a DDR controller and DDR memory chips. In storage system design, the storage controller is the most crucial component. The storage controller receives memory access requests, performs address translation and command scheduling, and returns or writes data. It utilizes optimized row buffer management, address mapping, and command scheduling mechanisms to maximize memory access bandwidth and minimize access latency. Figure 1 In order to ensure correct reading and writing of DDR chips, the values ​​of BG[0] and BG[1] are set to be the same, allowing a single CPU core to read and write BANK GROUP1 and BANK GROUP2 of two DDR chips at the same time. In practical applications, the DDR controller and DDR chips are connected to complete the functions of DDR reading and writing and storing data. The number of DDR chips is determined by the data bit width of the DDR controller and DDR chips. Therefore, the total capacity of DDR chips is also fixed. When the data bit width of the DDR controller and DDR chips is fixed, the DDR chips cannot be expanded. Therefore, the number of DDR chips that the CPU reads and writes through the DDR controller is also fixed.

[0054] To address the aforementioned technical problems, this application provides a DDR expansion device, such as... Figure 3 As shown, it includes:

[0055] DDR controller 12, first DDR chip 13, second DDR chip 14, third DDR chip 15, fourth DDR chip 16, inverter 11;

[0056] The chip select signal CS and the first BANK GROUP address selection signal BG[0] of the DDR controller 12 are respectively connected to the chip select signal CS and the address selection signal BG of the first DDR chip 13 and the second DDR chip 14. The chip select signal CS of the DDR controller 12 is connected to the chip select signal CS of the third DDR chip 15 and the fourth DDR chip 16 through the inverter 11. The second BANK GROUP address selection signal of the DDR controller 12 is connected to the first DDR chip 13 and the second DDR chip 14. The GROUP address selection signal terminal BG[1] is connected to the address selection signal terminal BG of the third DDR chip 15 and the fourth DDR chip 16. The low-order data signal DQ[15:0] of the DDR controller 12 is connected to the data signal terminal DQ[15:0] of the first DDR chip 13 and the third DDR chip 15. The high-order data signal DQ[31:16] of the DDR controller 12 is connected to the data signal terminal DQ[15:0] of the second DDR chip 14 and the fourth DDR chip 16. The BANK address selection signal terminal BA[1:0] and the address signal terminal ADDR[17:0] of the DDR controller 12 are connected to the BANK address selection signal terminal BA[1:0] and the address signal terminal ADDR[17:0] of the first DDR chip 13, the second DDR chip 14, the third DDR chip 15 and the fourth DDR chip 16, respectively. The chip select signal terminal CS of the DDR controller 12 is used to output high and low level signals to control the first DDR chip 13 and the second DDR chip 14 or the third DDR chip 15 and the fourth DDR chip 16 to work.

[0057] This embodiment does not limit the data bit width of the DDR controller 12; it can be set according to actual needs. For ease of description, this embodiment uses a 32-bit DDR controller 12 and a 16-bit DDR chip for description.

[0058] In this embodiment, when the chip select signal CS of the DDR controller 12 is high, the first DDR chip 13 and the second DDR chip 14 are enabled. The low-order data signal DQ[15:0] of the DDR controller 12 is connected to the data signal DQ[15:0] of the first DDR chip 13, and the high-order data signal DQ[31:16] of the DDR controller 12 is connected to the data signal DQ[15:0] of the second DDR chip 14. The address signal ADDR[17:0] and the BANK address selection signal BA[1:0] are connected to the first DDR chip 13 and the second DDR chip 14. The BANK GROUP is selected from the two DDR chips simultaneously through the first BANK GROUP address selection signal BG[0]. When the first BANK GROUP address selection signal BG[0] is low, BANK GROUP1 is selected from the two DDR chips. When the first BANK GROUP address selection signal BG[0] is high, BANK GROUP2 is selected from the two DDR chips.

[0059] When the chip select signal CS of the DDR controller 12 is low, the third DDR chip 15 and the fourth DDR chip 16 are enabled. The low-order data signal DQ[15:0] of the DDR controller 12 is connected to the data signal DQ[15:0] of the third DDR chip 15, and the high-order data signal DQ[31:16] of the DDR controller 12 is connected to the data signal DQ[15:0] of the fourth DDR chip 16. The address signal ADDR[17:0] and the BANK address selection signal BA[1:0] are connected to the third DDR chip 15 and the fourth DDR chip 16. The BANK GROUP is selected from the two DDR chips simultaneously through the second BANK GROUP address selection signal BG[1]. When the second BANK GROUP address selection signal BG[1] is low, BANK GROUP1 is selected from the two DDR chips. When the second BANK GROUP address selection signal BG[1] is high, BANK GROUP2 is selected from the two DDR chips.

[0060] While keeping the DDR controller 12 signal unchanged, the first BANK GROUP address selection signal terminal BG[0] is connected to the first DDR chip 13 and the second DDR chip 14 at the same time. The chip select signal terminal CS output by the DDR controller 12 is directly connected to the first DDR chip 13 and the second DDR chip 14, and then connected to the third DDR chip 15 and the fourth DDR chip 16 through the inverter 11. This enables the DDR controller 12 to carry 4 DDR chips while keeping the data bit width unchanged, which doubles the original storage capacity. DDR chips are connected when the chip select signal is at a high level. Therefore, when the chip select signal CS of the DDR controller 12 is high, the chip select signal CS of the first DDR chip 13 and the second DDR chip 14 is also high. After passing through the inverter 11, the chip select signal CS of the third DDR chip 15 and the fourth DDR chip 16 is low. At this time, the first DDR chip 13 and the second DDR chip 14 are connected. When the chip select signal CS of the DDR controller 12 is low, the chip select signal CS of the first DDR chip 13 and the second DDR chip 14 is also low. After passing through the inverter 11, the chip select signal CS of the third DDR chip 15 and the fourth DDR chip 16 is high. At this time, the third DDR chip 15 and the fourth DDR chip 16 are connected.

[0061] In summary, the DDR expansion device provided in this embodiment, with a fixed data bit width between the DDR controller 12 and the DDR chips, increases the number of mounted DDR chips by changing the operation of the BANK GROUP address selection signal terminal BG and the chip select signal terminal CS between the DDR controller 12 and the DDR chips. It can double the number of mounted DDR chips under any data bit width, thereby expanding the size of the DDR storage capacity mounted by the DDR controller 12, and changing the current situation where the number of DDR chips can only be determined based on the data bit width between the DDR controller 12 and the DDR chips.

[0062] According to the above embodiments, the DDR controller 12 needs to control the chip select signal terminal CS to output high and low potential electrical signals according to different needs. Therefore, this embodiment provides a preferred solution, which also includes: a processor;

[0063] The processor is connected to the DDR controller 12.

[0064] The processor mentioned in this embodiment includes, but is not limited to, a central processing unit (CPU) and a field-programmable gate array (FPGA). The processor is connected to the DDR controller 12 and controls the chip select signal terminal CS of the DDR controller 12 to output a high-level or low-level electrical signal to realize the access of the corresponding DRR chip.

[0065] According to the above embodiments, the DDR chips are expanded, and in practical applications, the processor is expanded to adapt to different needs. This embodiment provides a preferred solution that supports dual processors, the processors including a first processor 18 and a second processor 19, and also including: an arbitrator 17;

[0066] The first processor 18 and the second processor 19 are connected to the arbitrator 17, and the arbitrator 17 is connected to the DDR controller 12.

[0067] The main function of arbiter 17 is to determine which signal source should be responded to when multiple signal sources send requests at the same time, based on the current priority.

[0068] Therefore, arbitrator 17 enables dual-processor read / write of DDR chips. According to pre-set rules, arbitrator 17 selects either the first processor 18 or the second processor 19 to access the DDR chip for read / write.

[0069] This embodiment provides a preferred solution. If the first processor 18 and the second processor 19 are started simultaneously, the first processor 18 reads and writes the first DDR chip 13 and the second DDR chip 14, and the second processor 19 reads and writes the third DDR chip 15 and the fourth DDR chip 16. An arbitration selector selects which processor reads and writes the DDR chips at a given time. If only the first processor 18 or only the second processor 19 is started, either the first processor 18 or the second processor 19 can read and write the first DDR chip 13, the second DDR chip 14, the third DDR chip 15, and the fourth DDR chip 16. The chip select signal CS and the BANK GROUP address selection signal can be controlled to output high or low electrical signals as needed. This embodiment not only expands the storage capacity of the DDR chips mounted on the DDR controller 12, but also expands the number of DDR chips that the first processor 18 and the second processor 19 can read and write through the DDR controller 12. It supports dual-processor DDR read and write. Because the number of DDR chips is expanded, it can also meet the DDR read and write capacity required by dual processors. This design can be applied to scenarios with different data widths and supports different modes of starting dual-core or single-core processors.

[0070] Preferably, the arbitrator 17 is connected to the first processor 18 and the second processor 19 via a system bus.

[0071] The system bus is a separate computer bus and a major component connecting computer systems. This technology was developed to reduce costs and promote modularity. The system bus combines the functions of the data bus to carry information, the address bus to determine where information is sent, and the control bus to determine how actions are performed.

[0072] Preferably, the arbitrator 17 is connected to the DDR controller 12 via an AXI bus.

[0073] AXI (Advanced eXtensible Interface) is a bus protocol, a key component of ARM's AMBA (Advanced Microcontroller Bus Architecture) 3.0 protocol. It's a high-performance, high-bandwidth, low-latency on-chip bus. Its address / control and data phases are separated, supporting unaligned data transfers. In burst transfers, only the starting address is needed. It also features separate read / write data channels, supports outstanding transfer access and out-of-order access, and facilitates timing closure. AXI is a new high-performance protocol within AMBA.

[0074] Correspondingly, this embodiment provides a control method for a DDR expansion device, applied to a DDR expansion device, including: a DDR controller 12, a first DDR chip 13, a second DDR chip 14, a third DDR chip 15, a fourth DDR chip 16, and an inverter 11; the chip select signal terminal CS and the first BANK GROUP address selection signal terminal BG[0] of the DDR controller 12 are respectively connected to the chip select signal terminal CS and the address selection signal terminal BG of the first DDR chip 13 and the second DDR chip 14, respectively; the chip select signal terminal CS of the DDR controller 12 is connected to the chip select signal terminals CS of the third DDR chip 15 and the fourth DDR chip 16 through the inverter 11; the second BANK GROUP address selection signal terminal of the DDR controller 12 is connected to the second BANK GROUP address selection signal terminal BG[0]. The GROUP address selection signal terminal BG[1] is connected to the address selection signal terminal BG of the third DDR chip 15 and the fourth DDR chip 16. The low-order data signal DQ[15:0] of the DDR controller 12 is connected to the data signal terminal DQ[15:0] of the first DDR chip 13 and the third DDR chip 15. The high-order data signal DQ[31:16] of the DDR controller 12 is connected to the data signal terminal DQ[15:0] of the second DDR chip 14 and the fourth DDR chip 16. The BANK address selection signal terminal BA[1:0] and the address signal terminal ADDR[17:0] of the DDR controller 12 are connected to the BANK address selection signal terminal BA[1:0] and the address signal terminal ADDR[17:0] of the first DDR chip 13, the second DDR chip 14, the third DDR chip 15 and the fourth DDR chip 16, respectively.

[0075] This method includes:

[0076] S21: Determine the DDR chip that needs to be accessed at the current time;

[0077] S22: If it is necessary to connect the first DDR chip 13 and the second DDR chip 14, control the chip select signal terminal CS to output a high-level signal;

[0078] S23: If it is necessary to connect the third DDR chip 15 and the fourth DDR chip 16, control the chip select signal terminal CS to output a low-level signal.

[0079] When the chip select signal CS of the DDR controller 12 is high, the chip select signal CS of the first DDR chip 13 and the second DDR chip 14 are also high. After passing through the inverter 11, the chip select signal CS of the third DDR chip 15 and the fourth DDR chip 16 are low. At this time, the first DDR chip 13 and the second DDR chip 14 are connected. When the chip select signal CS of the DDR controller 12 is low, the chip select signal CS of the first DDR chip 13 and the second DDR chip 14 are also low. After passing through the inverter 11, the chip select signal CS of the third DDR chip 15 and the fourth DDR chip 16 are high. At this time, the third DDR chip 15 and the fourth DDR chip 16 are connected. The control method for the DDR expansion device provided in this embodiment increases the number of mounted DDR chips by changing the operation mode of the BANK GROUP address selection signal terminal BG and the chip select signal terminal CS between the DDR controller 12 and the DDR chips, under the condition that the data bit width of the DDR controller 12 and the DDR chips is fixed. It can double the number of mounted DDR chips under any data bit width, thereby expanding the size of the DDR storage capacity mounted by the DDR controller 12, changing the current situation that the number of DDR chips can only be determined according to the data bit width of the DDR controller 12 and the DDR chips.

[0080] According to the above embodiments, this embodiment provides another preferred solution for the control method of a DDR expansion device. The DDR expansion device further includes: a first processor 18, a second processor 19, and an arbitrator 17; the first processor 18 and the second processor 19 are connected to the arbitrator 17, and the arbitrator 17 is connected to the DDR controller 12.

[0081] To determine which DDR chip needs to be selected for connection, the following factors must be considered:

[0082] Receive the startup status of the first processor 18 and the second processor 19 sent by the arbitrator 17;

[0083] If the first processor 18 and the second processor 19 are started at the same time, determine which processor is currently selected by the arbitrator 17;

[0084] If the first processor 18 is selected, it is determined that the first DDR chip 13 and the second DDR chip 14 need to be connected.

[0085] If the second processor 19 is selected, it is determined that the third DDR chip 15 and the fourth DDR chip 16 need to be connected.

[0086] If the first processor 18 and the second processor 19 are started at the same time, the first processor 18 reads and writes the first DDR chip 13 and the second DDR chip 14, and the second processor 19 reads and writes the third DDR chip 15 and the fourth DDR chip 16. The arbitration selector selects which processor reads and writes the DDR chip at a certain time.

[0087] If the first processor 18 and the second processor 19 start simultaneously, and the arbitrator 17 selects the first processor 18, it is determined that the first DDR chip 13 and the second DDR chip 14 need to be connected, and the chip select signal terminal CS outputs a high-level signal; the first DDR chip 13 and the second DDR chip 14 are enabled, and the first BANK GROUP address selection signal terminal BG[0] selects the BANK GROUP of the two DDR chips at the same time. When the first BANK GROUP address selection signal terminal BG[0] is low, BANK GROUP1 of the two DDR chips is selected, and when the first BANK GROUP address selection signal terminal BG[0] is high, BANK GROUP2 of the two DDR chips is selected.

[0088] If the first processor 18 and the second processor 19 start simultaneously, and the arbitrator 17 selects the second processor 19, it is determined that the third DDR chip 15 and the fourth DDR chip 16 need to be connected. The chip select signal terminal CS outputs a low-high level signal. The third DDR chip 15 and the fourth DDR chip 16 are enabled. The second BANK GROUP address selection signal terminal BG[1] selects the BANK GROUP of the two DDR chips at the same time. When the second BANK GROUP address selection signal terminal BG[1] is low, BANK GROUP1 of the two DDR chips is selected. When the second BANK GROUP address selection signal terminal BG[1] is high, BANK GROUP2 of the two DDR chips is selected.

[0089] In this embodiment, when the first processor 18 and the second processor 19 are started simultaneously, by changing the function of the BANK GROUP address selection signal and the chip select signal, dual-processor read and write DDR can be supported, which can meet the DDR read and write capacity required by the dual processors. This design can be applied to scenarios with different data bit widths and supports different modes of starting dual-core or single-core processors.

[0090] According to the above embodiments, if only the first processor 18 or only the second processor 19 is started, the method further includes:

[0091] Determine the DDR chips that the currently booted processor needs to read or write;

[0092] If it is necessary to read or write the first DDR chip 13 and the second DDR chip 14, it is determined that the first DDR chip 13 and the second DDR chip 14 need to be connected.

[0093] If it is necessary to read or write the third DDR chip 15 and the fourth DDR chip 16, it is determined that the third DDR chip 15 and the fourth DDR chip 16 need to be connected.

[0094] If it is necessary to read or write the first DDR chip 13 and the second DDR chip 14, it is determined that the first DDR chip 13 and the second DDR chip 14 need to be connected, and the chip select signal terminal CS outputs a high-level signal; the first DDR chip 13 and the second DDR chip 14 are enabled, and the first processor 18 or the second processor 19 reads or writes the first DDR chip 13 and the second DDR chip 14. The first BANK GROUP address selection signal terminal BG[0] selects the BANK GROUP of the two DDR chips at the same time. When the first BANK GROUP address selection signal terminal BG[0] is low, BANK GROUP1 of the two DDR chips is selected. When the first BANK GROUP address selection signal terminal BG[0] is high, BANK GROUP2 of the two DDR chips is selected.

[0095] If it is necessary to read or write the third DDR chip 15 and the fourth DDR chip 16, it is determined that the third DDR chip 15 and the fourth DDR chip 16 need to be connected, and the chip select signal terminal CS outputs a low-high level signal; the third DDR chip 15 and the fourth DDR chip 16 are enabled, and the first processor 18 or the second processor 19 reads or writes the third DDR chip 15 and the fourth DDR chip 16. The second BANKGROUP address selection signal terminal BG[1] selects the BANK GROUP of the two DDR chips at the same time. When the second BANK GROUP address selection signal terminal BG[1] is low, BANK GROUP1 of the two DDR chips is selected. When the second BANK GROUP address selection signal terminal BG[1] is high, BANK GROUP2 of the two DDR chips is selected.

[0096] If only the first processor 18 or only the second processor 19 is started, the first processor 18 or the second processor 19 can read and write the first DDR chip 13, the second DDR chip 14, the third DDR chip 15, and the fourth DDR chip 16. The chip select signal CS and the BANK GROUP address selection signal can be controlled to output high or low electrical signals as needed. This not only expands the storage capacity of the DDR chips mounted on the DDR controller 12, but also expands the number of DDR chips that the first processor 18 and the second processor 19 can read and write through the DDR controller 12. It supports dual-processor DDR read and write. Because the number of DDR chips is expanded, it can also meet the DDR read and write capacity required by dual processors. This design can be applied to scenarios with different data widths and supports different modes of starting dual-core or single-core processors.

[0097] In the above embodiments, the control method for the DDR expansion device has been described in detail. This application also provides embodiments corresponding to the control device for the DDR expansion device. It should be noted that this application describes the embodiments of the device part from two perspectives: one is based on the functional module, and the other is based on the hardware.

[0098] Figure 5 This application provides a structural diagram of a control device for a DDR expansion device, applied to a DDR expansion device. The device includes: a DDR controller 12, a first DDR chip 13, a second DDR chip 14, a third DDR chip 15, a fourth DDR chip 16, and an inverter 11. The chip select signal terminal and the first BANK GROUP address selection signal terminal of the DDR controller 12 are respectively connected to the chip select signal terminals and address selection signal terminals of the first DDR chip 13 and the second DDR chip 14. The chip select signal terminal of the DDR controller 12 is connected to the chip select signal terminals of the third DDR chip 15 and the fourth DDR chip 16 via the inverter 11. The second BANK GROUP address selection signal terminal of the DDR controller 12 is... The GROUP address selection signal terminal is connected to the address selection signal terminals of the third DDR chip 15 and the fourth DDR chip 16. The low-order data signal of the DDR controller 12 is connected to the data signal terminals of the first DDR chip 13 and the third DDR chip 15. The high-order data signal of the DDR controller 12 is connected to the data signal terminals of the second DDR chip 14 and the fourth DDR chip 16. The BANK address selection signal terminal and the address signal terminal of the DDR controller 12 are respectively connected to the BANK address selection signal terminal and the address signal terminal of the first DDR chip 13, the second DDR chip 14, the third DDR chip 15 and the fourth DDR chip 16.

[0099] This device includes:

[0100] Judgment module 31 is used to determine the DDR chip that needs to be selected for access at the moment;

[0101] The first selection module 32 is used to control the chip select signal terminal to output a high-level signal if the first DDR chip 13 and the second DDR chip 14 need to be connected.

[0102] The second selection module 33 is used to control the chip select signal terminal to output a low-level signal if the third DDR chip 15 and the fourth DDR chip 16 need to be connected.

[0103] When the chip select signal CS of the DDR controller 12 is high, the chip select signal CS of the first DDR chip 13 and the second DDR chip 14 are also high. After passing through the inverter 11, the chip select signal CS of the third DDR chip 15 and the fourth DDR chip 16 are low. At this time, the first DDR chip 13 and the second DDR chip 14 are connected. When the chip select signal CS of the DDR controller 12 is low, the chip select signal CS of the first DDR chip 13 and the second DDR chip 14 are also low. After passing through the inverter 11, the chip select signal CS of the third DDR chip 15 and the fourth DDR chip 16 are high. At this time, the third DDR chip 15 and the fourth DDR chip 16 are connected. The control method for the DDR expansion device provided in this embodiment increases the number of mounted DDR chips by changing the operation mode of the BANK GROUP address selection signal terminal BG and the chip select signal terminal CS between the DDR controller 12 and the DDR chips, under the condition that the data bit width of the DDR controller 12 and the DDR chips is fixed. It can double the number of mounted DDR chips under any data bit width, thereby expanding the size of the DDR storage capacity mounted by the DDR controller 12, changing the current situation that the number of DDR chips can only be determined according to the data bit width of the DDR controller 12 and the DDR chips.

[0104] Also includes:

[0105] The receiving subunit is used to receive the startup status of the first processor 18 and the second processor 19 sent by the arbitrator 17;

[0106] If the first processor 18 and the second processor 19 are started at the same time, the first judgment subunit is used to determine which processor is currently selected by the arbitrator 17.

[0107] If the first processor 18 is selected, it is determined that the first DDR chip 13 and the second DDR chip 14 need to be connected, and the first selection module 32 is triggered.

[0108] If the second processor 19 is selected, it is determined that the third DDR chip 15 and the fourth DDR chip 16 need to be connected, triggering the second selection module 33;

[0109] If only the first processor 18 or only the second processor 19 is started, the second judgment subunit is used to determine the DDR chips that the currently started processor needs to read or write.

[0110] If it is necessary to read or write the first DDR chip 13 and the second DDR chip 14, it is determined that the first DDR chip 13 and the second DDR chip 14 need to be connected, and the first selection module 32 is triggered.

[0111] If it is necessary to read or write the third DDR chip 15 and the fourth DDR chip 16, it is determined that the third DDR chip 15 and the fourth DDR chip 16 need to be connected, and the second selection module 33 is triggered.

[0112] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus, which will not be repeated here.

[0113] Figure 6 A structural diagram of the control device for another DDR expansion device provided in this application embodiment is shown below. Figure 6 As shown, the control device for the DDR extension device includes: a memory 40 for storing computer programs;

[0114] The processor 41 is configured to implement the steps of the method for obtaining user operation habit information as described in the above embodiment (control method for DDR extension device) when executing a computer program.

[0115] The control device for the DDR extension device provided in this embodiment may include, but is not limited to, smartphones, tablets, laptops, or desktop computers.

[0116] The processor 41 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 41 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 41 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 41 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 41 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.

[0117] The memory 40 may include one or more computer-readable storage media, which may be non-transitory. The memory 40 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 40 is used to store at least the following computer program 401, which, after being loaded and executed by the processor 41, is capable of implementing the relevant steps of the control method for the DDR extension device disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 40 may also include an operating system 402 and data 403, and the storage method may be temporary storage or permanent storage. The operating system 402 may include Windows, Unix, Linux, etc. The data 403 may include, but is not limited to, data involved in implementing the control method for the DDR extension device.

[0118] In some embodiments, the control device of the DDR expansion device may further include a display screen 42, an input / output interface 43, a communication interface 44, a power supply 45, and a communication bus 46.

[0119] Those skilled in the art will understand that Figure 6 The structure shown does not constitute a limitation on the control device of the DDR extension device and may include more or fewer components than shown.

[0120] The control device for the DDR expansion device provided in this application embodiment includes a memory and a processor. When the processor executes the program stored in the memory, it can implement the following method: a control method for the DDR expansion device, wherein when the chip select signal terminal CS of the DDR controller 12 is high, the chip select signal terminals CS of the first DDR chip 13 and the second DDR chip 14 are high, and after passing through the inverter 11, the chip select signal terminals CS of the third DDR chip 15 and the fourth DDR chip 16 are low, at which time the first DDR chip 13 and the second DDR chip 14 are connected; when the chip select signal terminal CS of the DDR controller 12 is low, the chip select signal terminals CS of the first DDR chip 13 and the second DDR chip 14 are low, and after passing through the inverter 11, the chip select signal terminals CS of the third DDR chip 15 and the fourth DDR chip 16 are high, at which time the third DDR chip 15 and the fourth DDR chip 16 are connected. The control method for the DDR expansion device provided in this embodiment increases the number of mounted DDR chips by changing the operation mode of the BANK GROUP address selection signal terminal BG and the chip select signal terminal CS between the DDR controller 12 and the DDR chips, under the condition that the data bit width of the DDR controller 12 and the DDR chips is fixed. It can double the number of mounted DDR chips under any data bit width, thereby expanding the size of the DDR storage capacity mounted by the DDR controller 12, changing the current situation that the number of DDR chips can only be determined according to the data bit width of the DDR controller 12 and the DDR chips.

[0121] Finally, this application also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps described in the above-described embodiment of the control method for a DDR extension device (which may be a method corresponding to the server side, a method corresponding to the diagnostic device side, or a method corresponding to both the server side and the diagnostic device side).

[0122] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0123] The computer-readable storage medium provided in this embodiment stores a computer program. When the processor executes the program, the following method can be implemented: a control method for a DDR expansion device. When the chip select signal terminal CS of the DDR controller 12 is high, the chip select signal terminals CS of the first DDR chip 13 and the second DDR chip 14 are high. After passing through the inverter 11, the chip select signal terminals CS of the third DDR chip 15 and the fourth DDR chip 16 are low. At this time, the first DDR chip 13 and the second DDR chip 14 are connected. When the chip select signal terminal CS of the DDR controller 12 is low, the chip select signal terminals CS of the first DDR chip 13 and the second DDR chip 14 are low. After passing through the inverter 11, the chip select signal terminals CS of the third DDR chip 15 and the fourth DDR chip 16 are high. At this time, the third DDR chip 15 and the fourth DDR chip 16 are connected. The control method for the DDR expansion device provided in this embodiment increases the number of mounted DDR chips by changing the operation mode of the BANK GROUP address selection signal terminal BG and the chip select signal terminal CS between the DDR controller 12 and the DDR chips, under the condition that the data bit width of the DDR controller 12 and the DDR chips is fixed. It can double the number of mounted DDR chips under any data bit width, thereby expanding the size of the DDR storage capacity mounted by the DDR controller 12, changing the current situation that the number of DDR chips can only be determined according to the data bit width of the DDR controller 12 and the DDR chips.

[0124] The DDR extension device, control method, apparatus, and medium provided in this application have been described in detail above. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0125] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A DDR extension device, characterized by, The application relates to a DDR (Double Data Rate) memory system. The chip selection signal end of the DDR controller (12) is connected with the chip selection signal end of the first DDR particle (13) and the second DDR particle (14) through the inverter (11), the chip selection signal end of the DDR controller (12) is connected with the chip selection signal end of the third DDR particle (15) and the fourth DDR particle (16), the second BANK GROUP address selection signal end of the DDR controller (12) is connected with the address selection signal end of the third DDR particle (15) and the fourth DDR particle (16), the low bit data signal of the DDR controller (12) is connected with the data signal end of the first DDR particle (13) and the third DDR particle (15), the high bit data signal of the DDR controller (12) is connected with the data signal end of the second DDR particle (14) and the fourth DDR particle (16), the BANK address selection signal end and the address signal end of the DDR controller (12) are connected with the BANK address selection signal end and the address signal end of the first DDR particle (13), the second DDR particle (14), the third DDR particle (15) and the fourth DDR particle (16), and the chip selection signal end CS of the DDR controller (12) is used for outputting a high level signal and a low level signal. The application further comprises:

2. The DDR extension apparatus according to claim 1, wherein a processor; the processor is connected with the DDR controller (12). The application further comprises:

3. The DDR extension apparatus according to claim 2, wherein an arbitrator (17), the processor comprises a first processor (18) and a second processor (19); the first processor (18) and the second processor (19) are connected with the arbitrator (17), and the arbitrator (17) is connected with the DDR controller (12). the arbitrator (17) is connected with the first processor (18) and the second processor (19) through a system bus.

4. The DDR extension apparatus according to claim 3, wherein ​ 5. A control method of a DDR extension device, characterized by, The application is applied to a DDR expansion device, which comprises a DDR controller (12), a first DDR particle (13), a second DDR particle (14), a third DDR particle (15), a fourth DDR particle (16) and an inverter (11). The chip selection signal end of the DDR controller (12) is connected with the chip selection signal end and the address selection signal end of the first DDR particle (13) and the second DDR particle (14) respectively. The chip selection signal end of the DDR controller (12) is connected with the chip selection signal end of the third DDR particle (15) and the fourth DDR particle (16) through the inverter (11). The second BANK GROUP address selection signal end of the DDR controller (12) is connected with the address selection signal end of the third DDR particle (15) and the fourth DDR particle (16). The low-bit data signal of the DDR controller (12) is connected with the data signal end of the first DDR particle (13) and the third DDR particle (15). The high-bit data signal of the DDR controller (12) is connected with the data signal end of the second DDR particle (14) and the fourth DDR particle (16). The BANK address selection signal end and the address signal end of the DDR controller (12) are connected with the BANK address selection signal end and the address signal end of the first DDR particle (13), the second DDR particle (14), the third DDR particle (15) and the fourth DDR particle (16) respectively. The method comprises: judging the DDR particle to be accessed currently; if the first DDR particle (13) and the second DDR particle (14) are to be accessed, controlling the chip selection signal end to output a high-level signal; if the third DDR particle (15) and the fourth DDR particle (16) are to be accessed, controlling the chip selection signal end to output a low-level signal.

6. The control method of the DDR extension device according to claim 5, wherein The DDR expansion device further comprises a first processor (18), a second processor (19) and an arbitrator (17). The first processor (18) and the second processor (19) are connected with the arbitrator (17), and the arbitrator (17) is connected with the DDR controller (12). The judgment of the DDR particle to be accessed currently comprises: receiving the start state of the first processor (18) and the second processor (19) sent by the arbitrator (17); if the first processor (18) and the second processor (19) start at the same time, judging which processor is selected by the arbitrator (17) currently; if the first processor (18) is selected, judging that the first DDR particle (13) and the second DDR particle (14) are to be accessed; if the second processor (19) is selected, judging that the third DDR particle (15) and the fourth DDR particle (16) are to be accessed.

7. The control method of the DDR extension device according to claim 6, wherein if only the first processor (18) starts or only the second processor (19) starts, further comprising: Judge the current processor needs to read and write DDR particles; If the first DDR particles (13) and the second DDR particles (14) need to be read and written, it is judged that the first DDR particles (13) and the second DDR particles (14) need to be accessed; If the third DDR particles (15) and the fourth DDR particles (16) need to be read and written, it is judged that the third DDR particles (15) and the fourth DDR particles (16) need to be accessed.

8. A control device of a DDR extension device, characterized by, The application is applied to DDR expansion device, including: DDR controller (12), first DDR particles (13), second DDR particles (14), third DDR particles (15), fourth DDR particles (16), inverter (11); The chip selection signal end of the DDR controller (12), the first BANK GROUP address selection signal end is connected with the chip selection signal end, the address selection signal end of the first DDR particles (13) and the second DDR particles (14), the chip selection signal end of the DDR controller (12) is connected with the chip selection signal end of the third DDR particles (15) and the fourth DDR particles (16) through the inverter (11), the second BANK GROUP address selection signal end of the DDR controller (12) is connected with the address selection signal end of the third DDR particles (15) and the fourth DDR particles (16), the low bit data signal of the DDR controller (12) is connected with the data signal end of the first DDR particles (13) and the third DDR particles (15), the high bit data signal of the DDR controller (12) is connected with the data signal end of the second DDR particles (14) and the fourth DDR particles (16), the BANK address selection signal end, the address signal end of the DDR controller (12) is connected with the BANK address selection signal end, the address signal end of the first DDR particles (13), the second DDR particles (14), the third DDR particles (15) and the fourth DDR particles (16); The device comprises: The judging module is used for judging the DDR particles that need to be accessed currently; The first selection module is used for outputting high level signal to the chip selection signal end if the first DDR particles (13) and the second DDR particles (14) need to be accessed. The second selection module is used for outputting low level signal to the chip selection signal end if the third DDR particles (15) and the fourth DDR particles (16) need to be accessed.

9. A control device of a DDR extension device, characterized by, It comprises: The memory is used for storing computer program; The processor is used for executing the computer program to realize the steps of the control method of the DDR expansion device according to any one of claims 5 to 7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer program, and the computer program is executed by the processor to realize the steps of the control method of the DDR expansion device according to any one of claims 5 to 7.

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