electronic components

Abstract

The present disclosure provides an electronic component. The electronic component includes: a plurality of multilayer capacitors stacked in a plurality of rows and a plurality of columns, each of the plurality of multilayer capacitors having external electrodes located at both ends of the multilayer capacitor in a first direction; and a board including a main body and a connecting portion. The connecting portion includes: a plurality of positive electrode pad patterns; a plurality of negative electrode pad patterns; a positive electrode terminal pattern and a negative electrode terminal pattern formed on the lower surface of the main body so as to be separated from each other in the first direction; a positive electrode connecting portion connecting the plurality of positive electrode pad patterns to the positive electrode terminal pattern; and a negative electrode connecting portion connecting the plurality of negative electrode pad patterns to the negative electrode terminal pattern.

Description

[0001] This application is a divisional application of the invention patent application with application date of January 24, 2019, application number 201910067853.X, and invention name “Electronic Component”. Technical Field

[0002] The present disclosure relates to an electronic assembly. Background Art

[0003] The multilayer capacitor is manufactured by stacking a plurality of thin sheets in which organic materials and inorganic materials are combined, cutting the stacked sheets, and calcining and sintering the cut sheet portions.

[0004] Therefore, as the size of the product increases, it may become more difficult to cut the product, and the stress applied to the product when cutting may further increase.

[0005] Furthermore, as the size of the product increases, there are difficulties in burning out and sintering the organic material deep within the product during calcination and sintering.

[0006] Therefore, when a product has a size of a predetermined level or more, there are difficulties in the manufacturing process, and reliability or defect rate of the product may be deteriorated due to occurrence of electrostrictive central cracks or warping cracks at edges.

[0007] Meanwhile, recently, as the number of electronic components used in the industrial field and the electronics field has increased, the demand for large-sized electronic components requiring high capacity, high voltage, and high reliability has increased.

[0008] Therefore, there has been a need for a method of stacking a plurality of multilayer capacitors manufactured using a simple manufacturing process, ensuring a predetermined level of reliability of a product, and reducing a defect rate of the product to a predetermined level or lower. Summary of the Invention

[0009] One aspect of the present disclosure may provide an electronic component having a plurality of multilayer capacitors stacked therein, the electronic component having a simple manufacturing process, ensuring high capacitance, ensuring product reliability at a predetermined level, and reducing product defect rate to a predetermined level or lower.

[0010] According to one aspect of the present disclosure, an electronic component may include: a plurality of multilayer capacitors stacked in a plurality of rows and a plurality of columns, and each multilayer capacitor having external electrodes located on both ends of the multilayer capacitor in a first direction; and a plate including a main body and a connecting portion, wherein the connecting portion on both sides of the main body of the multilayer capacitor includes: a plurality of positive electrode pad patterns, arranged on the upper surface of the main body to be separated from each other in the first direction, and the positive external electrodes of the multilayer capacitor are mounted on the plurality of positive electrode pad patterns; a plurality of negative electrode pad patterns, arranged on the upper surface of the main body to alternate with the positive electrode pad patterns in the first direction, and the negative external electrodes of the multilayer capacitor are mounted on the plurality of negative electrode pad patterns; positive electrode terminal patterns and negative electrode terminal patterns, formed on the lower surface of the main body to be separated from each other in the first direction; a positive electrode connecting portion connecting the plurality of positive electrode pad patterns to the positive electrode terminal pattern; and a negative electrode connecting portion connecting the plurality of negative electrode pad patterns to the negative electrode terminal pattern.

[0011] One of the positive electrode pad patterns may be exposed to a first edge of the main body in the first direction, one of the negative electrode pad patterns may be exposed to a second edge of the main body opposite to the first edge of the main body, the positive electrode terminal pattern may be exposed to a third edge of the main body in the first direction, the negative electrode terminal pattern may be exposed to a fourth edge of the main body opposite to the third edge of the main body, one of the positive electrode connecting portions may be a positive electrode connecting pattern formed on a first surface of the main body in the first direction, and one of the negative electrode connecting portions may be a negative electrode connecting pattern formed on a second surface of the main body opposite to the first surface of the main body in the first direction.

[0012] A plurality of grooves may be formed in the first and second surfaces of the body, and the positive electrode connection pattern and the negative electrode connection pattern may be formed in the plurality of grooves, respectively.

[0013] The positive electrode connecting portion may include at least one positive via electrode and at least one positive electrode conductive layer formed in the plate along a thickness direction, and the negative electrode connecting portion may include at least one negative via electrode and at least one negative electrode conductive layer formed in the plate along the thickness direction.

[0014] Adjacent positive external electrodes of the plurality of multilayer capacitors may be connected to each other and adjacent negative external electrodes may be connected to each other to form a single capacitor block, and the plurality of capacitor blocks may be stacked on the board in a plurality of rows and a plurality of columns.

[0015] In the capacitor block, the adhesive portion may be formed between the positive external electrodes and between the negative external electrodes of adjacent multilayer capacitors.

[0016] The adjacent positive external electrodes are directly connected to each other, and the adjacent negative external electrodes are directly connected to each other.

[0017] A conductive adhesive layer may be formed between the capacitor block and the board.

[0018] The conductive adhesive layer may be flux or solder.

[0019] The positive electrode pad pattern may include a first positive electrode pad pattern exposed to a first edge of the main body in the first direction and a second positive electrode pad pattern provided on the upper surface of the main body to be separated from the first positive electrode pad pattern in the first direction, the negative electrode pad pattern may include a first negative electrode pad pattern exposed to a second edge of the main body opposite to the first edge of the main body and a second negative electrode pad pattern provided on the upper surface of the main body and located between the first positive electrode pad pattern and the second positive electrode pad pattern, the positive electrode terminal pattern may include a first main body portion exposed to a third edge of the main body in the first direction and at least one first extension portion extending from the first main body portion to a position corresponding to the second positive electrode pad pattern, and the negative electrode terminal pattern may include a second main body portion exposed to a fourth edge of the main body opposite to the third edge of the main body and a second extension portion extending from the second main body portion to a position corresponding to the second positive electrode pad pattern. at least one second extension portion at a position corresponding to the second negative electrode pad pattern, the positive electrode connecting portion may include a positive electrode connecting pattern formed on the first surface of the main body in the first direction and connecting the first positive electrode pad pattern and the first main body portion to each other, and a first via electrode connecting the second positive electrode pad pattern and the first extension portion to each other, the negative electrode connecting portion may include a negative electrode connecting pattern formed on the second surface of the main body opposite to the first surface of the main body in the first direction and connecting the first negative electrode pad pattern and the second main body portion to each other, and a second via electrode connecting the second negative electrode pad pattern and the second extension portion to each other, and the first external electrode of the multilayer capacitor may be installed on the first positive electrode pad pattern and the second positive electrode pad pattern, and the second external electrode of the multilayer capacitor may be installed on the first negative electrode pad pattern and the second negative electrode pad pattern.

[0020] The electronic component may further include an insulating layer formed to cover upper portions of the plurality of multilayer capacitors.

[0021] The multilayer capacitor may include a capacitor body including first and second inner electrodes stacked to be alternately exposed to both surfaces of the capacitor body in a length direction, and the first and second inner electrodes may be connected to the first and second outer electrodes, respectively.

[0022] In the multilayer capacitor, a first plating layer and a second plating layer may be formed on the first external electrode and the second external electrode, respectively.

[0023] The first plating layer and the second plating layer may be tin (Sn) plating layers.

[0024] Adjacent multilayer capacitors are directly connected to each other through the tin (Sn) plating layers of the first and second external electrodes, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0026] Figure 1 is a perspective view schematically showing a multilayer capacitor applied to an electronic component according to an exemplary embodiment of the present disclosure;

[0027] Figure 2 It is along Figure 1 A cross-sectional view taken along line II';

[0028] Figure 3 yes Figure 1 An exploded perspective view of the subject;

[0029] Figure 4 is a perspective view of an electronic component according to an exemplary embodiment of the present disclosure;

[0030] Figure 5 yes Figure 4 A cross-sectional view of an electronic component in the XZ direction;

[0031] Figure 6 yes Figure 4 A front view of a board of electronic components;

[0032] Figure 7 yes Figure 4 A rear view of the board with electronic components;

[0033] Figure 8 is a perspective view of an electronic component according to another exemplary embodiment of the present disclosure;

[0034] Figure 9 yes Figure 8 A front view of a board of electronic components;

[0035] Figure 10 yes Figure 8 a rear view of the board of electronic components; and

[0036] Figure 11 It is shown in Figure 8 A perspective view showing a case where an insulating layer is further formed on an electronic component. DETAILED DESCRIPTION

[0037] Hereinafter, exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0038] The directions of the hexahedron will be defined to clearly describe the exemplary embodiments of the present disclosure. X, Y, and Z shown in the drawings represent the length direction, width direction, and thickness direction, respectively. Here, the thickness direction may be the same as the stacking direction of the dielectric layers in the multilayer capacitor.

[0039] Furthermore, for convenience of explanation, surfaces of the body opposing each other in the Z direction will be defined as first and second surfaces, and surfaces of the body opposing each other in the X direction will be defined as third and fourth surfaces.

[0040] Multilayer capacitors

[0041] Figure 1 is a perspective view schematically showing a multilayer capacitor of an electronic component according to an exemplary embodiment in the present disclosure, Figure 2 It is along Figure 1 The cross-sectional view taken along line II' is shown in FIG. Figure 3 yes Figure 1 An exploded perspective view of the subject.

[0042] Reference Figures 1 to 3 , the multilayer capacitor 100 according to the present exemplary embodiment may include a capacitor body 110 ; and first and second external electrodes 131 and 132 .

[0043] The capacitor body 110 may be formed by stacking a plurality of dielectric layers 111 in the Z direction and sintering the stacked dielectric layers 111. In this case, the shape and size of the capacitor body 110 and the number of stacked dielectric layers 111 may be variously changed and are not limited to those of the present exemplary embodiment.

[0044] Furthermore, the plurality of dielectric layers 111 constituting the capacitor body 110 may be in a sintered state, and adjacent dielectric layers 111 may be integrated with each other such that boundaries between adjacent dielectric layers 111 may not be apparent without a scanning electron microscope (SEM).

[0045] Furthermore, the capacitor body 110 may include an active area 115 as a portion contributing to forming capacitance of the capacitor, and upper and lower covers 112 and 113 formed on upper and lower surfaces of the active area 115 as upper and lower edge portions, respectively.

[0046] The active area 115 may be formed by repeatedly stacking a plurality of first internal electrodes 121 and a plurality of second internal electrodes 122 in the Z direction with the dielectric layer 111 interposed therebetween.

[0047] In this case, the thickness of the dielectric layer 111 may be appropriately changed according to the capacitance design of the multilayer capacitor 100 .

[0048] In addition, the dielectric layer 111 may include ceramic powder having a high dielectric constant, such as barium titanate (BaTiO 3 )-based powder or strontium titanate (SrTiO 3 )-based powder. However, the material of the dielectric layer 111 is not limited thereto.

[0049] The upper and lower covers 112 and 113 may have the same material and configuration as those of the dielectric layer 111 of the active area 115 , except that the internal electrodes are not included in the upper and lower covers 112 and 113 .

[0050] The upper cover 112 and the lower cover 113 may be formed by stacking one or two or more dielectric layers on the upper and lower surfaces of the active area 115 in the thickness direction, respectively, and generally serve to prevent the first and second internal electrodes 121 and 122 from being damaged by physical stress or chemical stress.

[0051] The first and second internal electrodes 121 and 122 , which are electrodes having different polarities from each other, may be formed by printing a conductive paste containing a conductive metal on the dielectric layer 111 at a predetermined thickness.

[0052] In this case, the conductive metal contained in the conductive paste may be, for example, nickel (Ni), copper (Cu), palladium (Pd), or an alloy thereof However, the conductive metal is not limited thereto.

[0053] In addition, as a printing method of the conductive paste, for example, a screen printing method, a gravure printing method, etc. can be used. However, the printing method is not limited thereto.

[0054] The first and second internal electrodes 121 and 122 may be alternately stacked in the capacitor body 110 to face each other in a stacking direction of the dielectric layer 111 .

[0055] Therefore, the first and second internal electrodes 121 and 122 may be disposed to be alternately exposed to both surfaces of the capacitor body 110 in the X direction with the dielectric layer 111 interposed therebetween. In this case, the first and second internal electrodes 121 and 122 may be electrically insulated from each other by the dielectric layer 111 disposed therebetween.

[0056] In addition, the portions of the first and second internal electrodes 121 and 122 alternately exposed to the two end surfaces of the capacitor body 110 in the X direction can be mechanically contacted with the first and second connecting portions of the first and second external electrodes 131 and 132 to be described below, respectively, so that the first and second internal electrodes 121 and 122 can be electrically connected to the first and second external electrodes 131 and 132, respectively.

[0057] Therefore, when voltage is applied to the first and second external electrodes 131 and 132, charges are accumulated between the first and second internal electrodes 121 and 122 facing each other. In this case, the capacitance of the multilayer capacitor 100 may be proportional to the area of ​​the overlapping region between the first and second internal electrodes 121 and 122 in the active area 115.

[0058] In addition, the thicknesses of the first and second internal electrodes 121 and 122 may be determined according to their uses.

[0059] The first and second external electrodes 131 and 132 may be formed using a conductive paste including a conductive metal.

[0060] Here, the conductive metal may be, for example, nickel (Ni), copper (Cu), palladium (Pd), gold (Au), or an alloy thereof However, the conductive metal is not limited thereto.

[0061] The first external electrode 131 as described above may include a first connection portion 131 a and a first band portion 131 b , and the second external electrode 132 may include a second connection portion 132 a and a second band portion 132 b .

[0062] In the first external electrode 131 and the second external electrode 132, the first connection portion 131a and the second connection portion 132a can be portions respectively arranged on two surfaces of the capacitor body 110 in the X direction, and the first band portion 131b and the second band portion 132b can be portions respectively extending from the first connection portion 131a and the second connection portion 132a to the portion of the lower surface (mounting surface) of the capacitor body 110.

[0063] Here, the first and second band portions 131 b and 132 b may further extend up to the upper surface of the capacitor body 110 and at least one of the two surfaces of the capacitor body 110 in the Y direction.

[0064] In addition, although the present exemplary embodiment describes and illustrates a situation in which the first band portion 131b of the first external electrode 131 and the second band portion 132b of the second external electrode 132 both extend from the first connecting portion 131a and the second connecting portion 132a to a portion of the upper surface of the capacitor body 110 and a portion of both surfaces of the capacitor body 110 in the Y direction to cover both end portions of the capacitor body 110, the first band portion 131b and the second band portion 132b are not limited to this.

[0065] electronic components

[0066] Figure 4 is a perspective view of an electronic component according to an exemplary embodiment of the present disclosure, Figure 5 yes Figure 4 A cross-sectional view of an electronic component along the XZ direction, Figure 6 yes Figure 4 A front view of the board with electronic components, and Figure 7 yes Figure 4 Rear view of the board with electronic components.

[0067] Reference Figures 4 to 7 , an electronic component 1 according to an exemplary embodiment in the present disclosure may include a plurality of multilayer capacitors 100 and a board 200 having an upper surface on which the plurality of multilayer capacitors 100 are stacked in a plurality of rows and a plurality of columns and including a body 210 and a connection portion.

[0068] The multilayer capacitor 100 may include a body 110 including first and second internal electrodes 121 and 122 stacked to be alternately exposed to both surfaces of the body 110 in the X direction (see FIG. 1 ). Figure 2 ), wherein the first inner electrode 121 and the second inner electrode 122 may be electrically connected to the first outer electrode 131 and the second outer electrode 132, respectively.

[0069] Furthermore, in the multilayer capacitor 100 , a first plating layer and a second plating layer may be formed on the first and second external electrodes 131 and 132 , respectively.

[0070] Here, the first plating layer and the second plating layer may be formed using tin (Sn) plating.

[0071] In this exemplary embodiment, multiple multilayer capacitors 100 can be arranged adjacent to each other in parallel, and an adhesive portion 241 formed using flux or the like can be formed between the positive external electrodes and the negative external electrodes of adjacent multilayer capacitors, and multiple capacitors 100 can be connected to each other through the adhesive portion 241 to form a single capacitor block 101.

[0072] Alternatively, adjacent multilayer capacitors 100 may be directly bonded to each other via the first plating layer of the first external electrode 131 and the second plating layer of the second external electrode 132. For example, when the tin (Sn) of the plating melts and diffuses during the reflow process, adjacent first external electrodes 131 and adjacent second external electrodes 132 may be bonded without the need for solder or other added adhesive. Thus, adjacent external electrodes may be integrally formed.

[0073] Although the case where three multilayer capacitors 100 are adhered to each other in the Y direction by the adhesive portion 241 to form a single capacitor block 101 is described in the present exemplary embodiment, the number of capacitor blocks in the present disclosure is not limited to three.

[0074] The electronic component 1 according to the present disclosure may have a structure in which a plurality of capacitor blocks 101 are stacked in a plurality of rows and a plurality of columns on a board 200 using a surface mount technology (SMT) device.

[0075] Although the case where the electronic component 1 has capacitors provided in a 2×3×2 (X×Y×Z) arrangement is shown and described in the present exemplary embodiment, the electronic component 1 is not limited thereto.

[0076] Here, a conductive adhesive layer 251 may be formed between the board 200 and the capacitor block 101 .

[0077] The conductive adhesive layer 251 may be flux or solder.

[0078] Furthermore, the board 200 on which the capacitor block 101 is stacked may be subjected to a reflow process so that the capacitor block 101 and the board 200 may be securely fixed to each other by plating expansion or solder melting.

[0079] As described above, in the case where an electronic component 1 is constructed by stacking a plurality of multilayer capacitors 100 in at least two rows and at least two columns (2 rows × 2 columns), in order to connect the multilayer capacitors 100 in parallel, it is necessary to design a circuit so that all the multilayer capacitors 100 are connected in parallel to each other on the board 200 in the lower part of the electronic component 1.

[0080] Hereinafter, connection portions of the board 200 for designing a circuit as described above will be described in detail.

[0081] The connection portion may include a plurality of positive electrode pad patterns 211 a and 214 , a plurality of negative electrode pad patterns 212 a and 213 , positive and negative electrode terminal patterns 211 c and 212 c , and positive and negative electrode connection portions, respectively.

[0082] In addition, the connection portion may be formed by a conductive paste including a conductive metal.

[0083] Here, the conductive metal may be, for example, nickel (Ni), copper (Cu), palladium (Pd), gold (Au), or an alloy thereof However, the conductive metal is not limited thereto.

[0084] In addition, a plating layer such as nickel (Ni) / tin (Sn) plating layer may be formed on the surface of the connection portion.

[0085] A plurality of positive electrode pad patterns 211 a and 214 may be provided on the upper surface of the body 210 to be spaced apart from each other in the X direction, and the first external electrode 131 corresponding to the positive electrode of the multilayer capacitor 100 may be mounted on the plurality of positive electrode pad patterns 211 a and 214 .

[0086] Here, one positive electrode pad pattern 211a may be exposed to a first edge of the body 210 in the X direction. In addition, another positive electrode pad pattern 214 may be disposed to be separated from the first edge in the X direction.

[0087] A plurality of negative electrode pad patterns 212 a and 213 may be alternately arranged on the upper surface of the body 210 to be separated from the positive electrode pad patterns 211 a and 214 in the X direction, and the second external electrode 132 corresponding to the negative electrode of the multilayer capacitor 100 may be mounted on the plurality of negative electrode pad patterns 212 a and 213 .

[0088] Here, one negative electrode pad pattern 212a may be exposed to a second edge of the body 210 opposite to the first edge of the body 210 in the X direction. In addition, another negative electrode pad pattern 213 may be disposed spaced apart from the second edge in the X direction and disposed between the positive electrode pad patterns 211a and 214.

[0089] A positive electrode terminal pattern 211 c and a negative electrode terminal pattern 212 c may be formed on a lower surface of the body 210 to be spaced apart from each other in the X-direction.

[0090] The positive electrode terminal pattern 211 c and the negative electrode terminal pattern 212 c may serve as terminals for mounting electronic components in an external device.

[0091] Here, the positive electrode terminal pattern 211 c may be exposed to a third edge of the body 210 in the X direction, and the negative electrode terminal pattern 212 c may be exposed to a fourth edge of the body 210 opposite to the third edge of the body 210 in the X direction.

[0092] The positive electrode connecting portion may be used to connect the plurality of positive electrode pad patterns 211 a and 214 to the positive electrode terminal pattern 211 c .

[0093] The positive electrode connection portion as described above may include a positive electrode connection pattern 211b formed on a first surface of the body 210 in the X direction, at least one positive via electrode 232 formed in the body 210 of the board 200 along the Z direction, and at least one positive electrode conductive layer 234 for connecting the positive via electrodes 232 to each other.

[0094] In addition, a plurality of grooves 221 may be formed in the first surface of the body 210 in the X direction, and the positive electrode connection pattern 211 b may be formed in each of the plurality of grooves 221 .

[0095] The negative electrode connecting portion may be used to connect the plurality of negative electrode pad patterns 212 a and 213 to the negative electrode terminal pattern 212 c .

[0096] The negative electrode connection portion as described above may include a negative electrode connection pattern 212b formed on a second surface of the body 210 opposite to the first surface of the body 210 in the X direction, at least one negative via electrode 231 formed in the body 210 of the board 200 along the Z direction, and at least one negative electrode conductive layer 233 for connecting the negative via electrodes 231 to each other.

[0097] In addition, a plurality of grooves 222 may be formed in the second surface of the body 210 in the X direction, and a negative electrode connection pattern 212 b may be formed in each of the plurality of grooves 222 .

[0098] According to the structure described above, the first external electrode 131 of the multilayer capacitor 100 can be connected to the positive electrode terminal pattern 211c through the positive electrode pad pattern 211a and the positive electrode connection pattern 211b or through the positive electrode pad pattern 214, the positive via electrode 232 and the positive electrode conductive layer 234.

[0099] Furthermore, the second external electrode 132 of the multilayer capacitor 100 may be connected to the negative electrode terminal pattern 212 c through the negative electrode pad pattern 212 a and the negative electrode connection pattern 212 b or through the negative electrode pad pattern 213 , the negative via electrode 231 and the negative electrode conductive layer 233 .

[0100] The measured capacitance of the electronic component constructed as described above can be equal to a value calculated by multiplying the capacitance of a single multilayer capacitor by the total number of multilayer capacitors, so that the electronic component has the advantage of being able to use the same mounting pads as those of large-sized multilayer capacitors according to the prior art without capacitance loss.

[0101] Therefore, since the electronic component 1 according to this exemplary embodiment is formed by stacking a plurality of multilayer capacitors having a size with a simple manufacturing process and a high yield, it has the following advantages: a super-sized and high-capacitance product having a size of 4532 (4.5 mm × 3.2 mm) or larger can be manufactured.

[0102] Modified exemplary embodiments

[0103] Figure 8 is a perspective view of an electronic component according to another exemplary embodiment of the present disclosure, Figure 9 yes Figure 8 A front view of the board with electronic components, and Figure 10 yes Figure 8 Rear view of the board with electronic components.

[0104] Reference Figures 8 to 10 , the electronic component according to the present exemplary embodiment may include a first positive electrode pad pattern 311a exposed to a first edge of a body 310 of a board 300 in the X direction and a second positive electrode pad pattern 314 provided on an upper surface of the body 310 to be separated from the first positive electrode pad pattern 311a in the X direction.

[0105] In addition, the negative electrode pad pattern may include a first negative electrode pad pattern 312a exposed to a second edge of the body 310 opposite to the first edge of the body 310 and a second negative electrode pad pattern 313 arranged on the upper surface of the body 310 and located between the first positive electrode pad pattern 311a and the second positive electrode pad pattern 314.

[0106] In addition, the positive electrode terminal pattern may include a first body portion 311c exposed to a third edge of the body 310 in the X direction and at least one first extension portion 311d extending from the first body portion 311c to a portion of the lower surface of the body 310 corresponding to the second positive electrode pad pattern 314 in the Z direction.

[0107] Here, the plurality of first extension portions 311 d may be disposed to be separated from each other in the Y direction.

[0108] In addition, the negative electrode terminal pattern may include a second body portion 312c exposed to a fourth edge of the body 310 opposite to the third edge of the body 310 in the X direction and at least one second extension portion 312d extending from the second body portion 312c to a portion of the lower surface of the body 310 corresponding to the second negative electrode pad pattern 313 in the Z direction.

[0109] Here, the plurality of second extension portions 312 d may be disposed to be separated from each other in the Y direction.

[0110] In addition, the positive electrode connection portion may include a positive electrode connection pattern 311b formed on the first surface of the body 310 in the X direction and connecting the first positive electrode pad pattern 311a and the first body portion 311c to each other, and a first via electrode 316 connecting the second positive electrode pad pattern 314 and the first extension portion 311d to each other.

[0111] In addition, the negative electrode connection portion may include a negative electrode connection pattern 312b formed on a second surface of the body 310 opposite to the first surface of the body 310 in the X direction and connecting the first negative electrode pad pattern 312a and the second body portion 312c to each other, and a second via electrode 315 connecting the second negative electrode pad pattern 313 and the second extension portion 312d to each other.

[0112] Here, the first external electrode 131 of the multilayer capacitor 100 may be mounted on the first positive electrode pad pattern 311a and the second positive electrode pad pattern 314, and the second external electrode 132 of the multilayer capacitor 100 may be mounted on the first negative electrode pad pattern 312a and the second negative electrode pad pattern 313. In addition, the first external electrode 131 of the middle multilayer capacitor 100 may be mounted on the second positive electrode pad pattern 314, and the second external electrode 132 of the middle multilayer capacitor 100 may be mounted on the second negative electrode pad pattern 313.

[0113] According to this structure, the first external electrode 131 of the multilayer capacitor 100 can be connected to the first main body 311c of the positive electrode terminal pattern through the first positive electrode pad pattern 311a and the positive electrode connection pattern 311b, and connected to the first extension portion 311d of the positive electrode terminal pattern through the second positive electrode pad pattern 314 and the first via electrode 316.

[0114] In addition, the second external electrode 132 of the multilayer capacitor 100 can be connected to the second main body 312c of the negative electrode terminal pattern through the first negative electrode pad pattern 312a and the negative electrode connection pattern 312b, and connected to the second extension 312d of the negative electrode terminal pattern through the second negative electrode pad pattern 313 and the second via electrode 315.

[0115] At the same time, if Figure 11 As shown in FIG, an insulating layer 400 may be formed to cover upper portions of the plurality of multilayer capacitors 100 .

[0116] The insulating layer 400 as described above can make the upper portions of the plurality of multilayer capacitors 100 flat, thereby preventing pickup defects when performing surface mount technology (SMT) pickup and preventing short circuits with other components adjacent thereto on the upper portions of the multilayer capacitors.

[0117] As described above, according to the exemplary embodiments in the present disclosure, multiple multilayer capacitors can be stacked and connected in parallel with each other, the manufacturing process can be simple, high capacitance can be achieved, the reliability of the product can be ensured at a predetermined level or higher, and the defect rate can be reduced to a predetermined level or lower.

[0118] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present invention as defined by the appended claims.

Claims

1. An electronic component comprising: a plurality of multilayer capacitors stacked in a plurality of rows and a plurality of columns, each multilayer capacitor having a positive external electrode and a negative external electrode located on both ends of the multilayer capacitor in a first direction; as well as A plate comprising a main body and a connecting portion, Wherein, the connecting portion includes: a plurality of positive electrode pad patterns provided on an upper surface of the body to be spaced apart from each other in the first direction, and the positive external electrodes of the multilayer capacitor are mounted on the plurality of positive electrode pad patterns; a plurality of negative electrode pad patterns disposed on the upper surface of the body to alternate with the positive electrode pad patterns in the first direction, and the negative external electrode of the multilayer capacitor is mounted on the plurality of negative electrode pad patterns; a positive electrode terminal pattern and a negative electrode terminal pattern provided on a lower surface of the body to be separated from each other in the first direction; a positive electrode connecting portion connecting the plurality of positive electrode pad patterns to the positive electrode terminal pattern; and a negative electrode connecting portion connecting the plurality of negative electrode pad patterns to the negative electrode terminal pattern, wherein the positive electrode pad pattern includes a first positive electrode pad pattern exposed to a first edge of the main body in the first direction and a second positive electrode pad pattern provided on the upper surface of the main body to be separated from the first positive electrode pad pattern in the first direction, The negative electrode pad pattern includes a first negative electrode pad pattern exposed to a second edge of the body opposite to the first edge of the body and a second negative electrode pad pattern disposed on the upper surface of the body and located between the first positive electrode pad pattern and the second positive electrode pad pattern, The positive electrode terminal pattern includes a first body portion exposed to a third edge of the body in the first direction and at least one first extension portion extending from the first body portion to a position corresponding to the second positive electrode pad pattern. the negative electrode terminal pattern including a second body portion exposed to a fourth edge of the body opposite to the third edge of the body and at least one second extension portion extending from the second body portion to a position corresponding to the second negative electrode pad pattern, The plurality of multilayer capacitors are arranged in at least three rows, The positive external electrodes of the multilayer capacitors in the lowermost middle row are mounted on the second positive electrode land pattern, and The negative external electrodes of the multilayer capacitors of the lowermost middle row are mounted on the second negative electrode land pattern.

2. The electronic component according to claim 1, wherein One of the positive electrode pad patterns is exposed to a first edge of the body in the first direction, one of the negative electrode pad patterns is exposed to a second edge of the body opposite to the first edge of the body, the positive electrode terminal pattern is exposed to a third edge of the body in the first direction, the negative electrode terminal pattern is exposed to a fourth edge of the body opposite to the third edge of the body, One of the positive electrode connection parts is a positive electrode connection pattern formed on a first surface of the main body in the first direction, and One of the negative electrode connection parts is a negative electrode connection pattern formed on a second surface of the body opposite to the first surface of the body in the first direction.

3. The electronic component according to claim 2, wherein A plurality of grooves are formed in the first and second surfaces of the body, and the positive electrode connection pattern and the negative electrode connection pattern are formed in the plurality of grooves, respectively.

4. The electronic component according to claim 1, wherein The positive electrode connecting portion includes at least one positive via electrode formed in the plate in a thickness direction, and The negative electrode connecting portion includes at least one negative via electrode formed in the plate along the thickness direction.

5. The electronic component according to claim 4, wherein The positive electrode connecting portion further includes at least one positive electrode conductive layer provided in the plate, The negative electrode connecting part further includes at least one negative electrode conductive layer provided in the plate. The electronic component according to claim 1 , wherein: Adjacent positive external electrodes of the plurality of multilayer capacitors are connected to each other and adjacent negative external electrodes are connected to each other to form a single capacitor block, and the plurality of capacitor blocks are stacked in a plurality of rows and a plurality of columns on the board.

7. The electronic component according to claim 6, wherein In the capacitor block, the adhesive portion is provided between the positive external electrodes and between the negative external electrodes of adjacent multilayer capacitors.

8. The electronic component according to claim 6, wherein The adjacent positive external electrodes are directly connected to each other, and the adjacent negative external electrodes are directly connected to each other.

9. The electronic component according to claim 6, wherein A conductive adhesive layer is disposed between the capacitor block and the board.

10. The electronic component according to claim 9, wherein The conductive adhesive layer is flux or solder.

11. The electronic component according to claim 1, wherein The positive electrode connection portion includes a positive electrode connection pattern provided on a first surface of the body in the first direction and connecting the first positive electrode pad pattern and the first body portion to each other, and a first via electrode connecting the second positive electrode pad pattern and the first extension portion to each other. The negative electrode connecting portion includes a negative electrode connecting pattern provided on a second surface of the body opposite to the first surface of the body in the first direction and connecting the first negative electrode pad pattern and the second body portion to each other, and a second via electrode connecting the second negative electrode pad pattern and the second extension portion to each other, and The positive external electrode of the multilayer capacitor is mounted on the first and second positive electrode pad patterns, and the negative external electrode of the multilayer capacitor is mounted on the first and second negative electrode pad patterns. 12 . The electronic component according to claim 11 , further comprising an insulating layer covering upper portions of the plurality of multilayer capacitors.

13. The electronic component according to claim 1, wherein The multilayer capacitor includes a capacitor body including first and second inner electrodes stacked to be alternately exposed to both surfaces of the capacitor body in a length direction, and the first and second inner electrodes are connected to the positive and negative outer electrodes, respectively.

14. The electronic component according to claim 13, wherein In the multilayer capacitor, a first plating layer is provided on the positive external electrode, and a second plating layer is provided on the negative external electrode.

15. The electronic component according to claim 14, wherein The first plating layer and the second plating layer are tin plating layers.

16. The electronic component according to claim 15, wherein Adjacent multilayer capacitors are directly connected to each other through the tin plating layer on the positive external electrode and the tin plating layer on the negative external electrode, respectively.

Images