SJ-IGBT device and method of forming the same

Abstract

An SJ-IGBT device and a forming method thereof, the method comprising: providing a semiconductor substrate; performing P-type body region ion implantation into the semiconductor substrate to form a P-type body doped region; forming a P-type column in the semiconductor substrate, wherein a first distance between a top surface of the P-type column and a surface of the semiconductor substrate is greater than a second distance between a bottom surface of the P-type body doped region and the surface of the semiconductor substrate; forming a dielectric layer covering the P-type body doped region and the P-type column and isolating adjacent P-type body doped regions and P-type columns. The present application can reduce production cost, improve production efficiency and reduce process limitations.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to an SJ-IGBT device and its fabrication method. Background Technology

[0002] An insulated-gate bipolar transistor (IGBT) is a composite fully controllable voltage-driven power semiconductor device composed of a bipolar junction transistor (BJT) and an insulated-gate field-effect transistor (MOSFET). It combines the advantages of MOSFETs, such as high input impedance, simple driving, and high switching speed, with the advantages of BJTs, such as high current density, low saturation voltage drop, and strong current handling capability, making it a relatively ideal fully controllable device.

[0003] A superjunction (SJ) can include alternating N-type and P-type pillars located within the drift region of the IGBT. It can reduce the forward conduction power consumption, improve the forward conduction performance, and increase the power density of the device.

[0004] In existing SJ-IGBT devices, there may be a P-type doped region above the drift region, and the P-type doped region and the P-type pillar may have contact areas or even overlap areas, which causes carriers (such as holes) to be extracted when the device is forward-conducting, affecting the device performance.

[0005] However, existing methods for improving SJ-IGBT devices are complex, resulting in high production costs, and impose significant limitations on the sequence of SJ-IGBT device fabrication processes. Summary of the Invention

[0006] The technical problem solved by this invention is to provide an SJ-IGBT device and its formation method, which can reduce production costs, improve production efficiency, and reduce process limitations.

[0007] To address the aforementioned technical problems, this invention provides a method for forming an SJ-IGBT device, comprising: providing a semiconductor substrate; performing P-type body ion implantation into the semiconductor substrate to form a P-type body doped region; forming a P-type pillar in the semiconductor substrate, wherein a first distance between the top surface of the P-type pillar and the surface of the semiconductor substrate is greater than a second distance between the bottom surface of the P-type body doped region and the surface of the semiconductor substrate; forming a dielectric layer that covers the P-type body doped region and the P-type pillar, and isolates adjacent P-type body doped regions from the P-type pillar.

[0008] Optionally, forming a P-type pillar within the semiconductor substrate includes: forming a P-type pillar material layer, the top surface of which is flush with or higher than the surface of the semiconductor substrate; and etching back the P-type pillar material layer to obtain the P-type pillar.

[0009] Optionally, forming a P-type pillar material layer includes: etching the semiconductor substrate to obtain P-type pillar trenches; forming P-type pillar material within the P-type pillar trenches; and planarizing the P-type pillar material to obtain the P-type pillar material layer.

[0010] Optionally, the back etching of the P-type pillar material layer includes: using a dry etching process to back etch the P-type pillar material layer; wherein the etching thickness of the dry etching process is determined based on the second distance, and the larger the second distance, the larger the etching thickness.

[0011] Optionally, the method further includes forming a gate structure in the semiconductor substrate before performing P-type body region ion implantation in the semiconductor substrate.

[0012] Optionally, the method further includes forming a gate structure in the semiconductor substrate after performing P-type body region ion implantation in the semiconductor substrate and before forming P-type pillars in the semiconductor substrate.

[0013] Optionally, the method further includes forming a gate structure in the semiconductor substrate after forming a P-type pillar and before forming the dielectric layer.

[0014] To address the aforementioned technical problems, this invention provides an SJ-IGBT device, comprising: a semiconductor substrate; a P-type body doped region located within the semiconductor substrate; a P-type pillar located within the semiconductor substrate, wherein a first distance between the top surface of the P-type pillar and the surface of the semiconductor substrate is greater than a second distance between the bottom surface of the P-type body doped region and the surface of the semiconductor substrate; and a dielectric layer covering the P-type body doped region and the P-type pillar, and isolating adjacent P-type body doped regions and P-type pillars.

[0015] Optionally, the SJ-IGBT device further includes: a gate structure located within the semiconductor substrate; wherein the gate structure is formed prior to the formation of the P-type body doped region.

[0016] Optionally, the SJ-IGBT device further includes: a gate structure located within the semiconductor substrate; wherein the gate structure is formed after the formation of the P-type body doped region and before the formation of the P-type pillar.

[0017] Optionally, the SJ-IGBT device further includes: a gate structure located within the semiconductor substrate; wherein the gate structure is formed after the formation of the P-type pillar and before the formation of the dielectric layer.

[0018] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0019] In this embodiment of the invention, by forming a P-type body doped region and a P-type pillar, and wherein the first distance between the top surface of the P-type pillar and the surface of the semiconductor substrate is greater than the second distance between the bottom surface of the P-type body doped region and the surface of the semiconductor substrate, the electrical connection between the P-type body doped region and the P-type pillar can be disconnected. Furthermore, by isolating adjacent P-type body doped regions and P-type pillars through a subsequently formed dielectric layer, the problem of carrier (such as holes) being extracted during forward conduction of the device can be effectively mitigated, enhancing device performance. Compared to the prior art, which requires an additional isolation material layer, leading to increased production costs, the technical solution of this embodiment can reduce production costs and improve production efficiency. Furthermore, by adopting the above solution, since both the P-type body doped region and the gate structure are located within the semiconductor substrate, the formation order of the gate structure is not restricted, and there are no limitations on process improvement and process parameter adjustment, which is beneficial for device performance optimization.

[0020] Furthermore, a P-type pillar material layer with its top surface flush with or higher than the surface of the semiconductor substrate is formed. Then, the P-type pillar material layer is etched back to obtain the P-type pillar. The depth of the top surface of the P-type pillar can be more precisely controlled by using the surface of the semiconductor substrate as a reference position.

[0021] Furthermore, a P-type pillar material is first formed in the P-type pillar trench, and then the P-type pillar material is planarized to obtain the P-type pillar material layer. Before the back etching, the surface of the P-type pillar material can be made flush with or close to flush with the surface of the semiconductor substrate. Thus, the surface of the semiconductor substrate can be used as the starting reference position for the back etching, further improving the accuracy of controlling the depth of the top surface of the P-type pillar.

[0022] Furthermore, various process sequences can be used to form the P-type body doped region, P-type pillar, and gate structure in SJ-IGBT devices. The formation sequence of the gate structure is not strictly limited, which effectively improves process flexibility, facilitates process improvement and process parameter adjustment, and helps to optimize device performance. Attached Figure Description

[0023] Figures 1 to 5 This is a schematic diagram of the cross-sectional structure of a device corresponding to some steps in a method for forming an SJ-IGBT device in the prior art;

[0024] Figure 6 This is a flowchart of a method for forming an SJ-IGBT device according to an embodiment of the present invention;

[0025] Figures 7 to 15 This is a schematic diagram of the device cross-sectional structure corresponding to each step in the method for forming an SJ-IGBT device in an embodiment of the present invention.

[0026] Figure label:

[0027] Semiconductor substrate 100; protective layer 101; P-type pillar trench 111; P-type pillar 110; N-type epitaxial isolation layer 120; P-type body doped region 130; gate structure 140; semiconductor substrate 200; P-type body doped region 230; protective layer 201; P-type pillar trench 211; P-type pillar material 212; P-type pillar material layer 213; P-type pillar 210; gate structure 240; dielectric layer 250; plug structure 260; metal layer 270; capping layer 271. Detailed Implementation

[0028] In existing SJ-IGBT devices, a P-type doped region may exist above the drift region, and this P-type doped region and the P-type pillar may have contact areas or even overlap. This can lead to the extraction of charge carriers (such as holes) during forward conduction, affecting device performance. However, existing methods for improving SJ-IGBT devices are complex, resulting in high production costs, and impose significant limitations on the fabrication process sequence.

[0029] Figures 1 to 5 This is a schematic diagram of the cross-sectional structure of a device corresponding to some steps in a method for forming an SJ-IGBT device in the prior art.

[0030] Reference Figure 1 A semiconductor substrate 100 is provided, and a patterned protective layer 101 is formed on the surface of the semiconductor substrate 100. The semiconductor substrate 100 is etched using the patterned protective layer 101 as a mask to obtain a P-type pillar trench 111.

[0031] Reference Figure 2 A P-shaped column 110 is formed within the P-shaped column groove 111.

[0032] It is understandable that, in order to form an alternating arrangement of N-type pillars and P-type pillars SJ, an N-type doped region can be pre-formed in the semiconductor substrate 100, and a P-type pillar 110 can be formed within the N-type doped region.

[0033] Reference Figure 3 An N-type epitaxial isolation layer 120 is formed on the surface of a semiconductor substrate 100.

[0034] The inventors of this invention discovered through research that, in existing methods for improving SJ-IGBT devices, adding an additional layer of insulating material (i.e., Figure 3 The technical solution shown (N-type epitaxial isolation layer 120) leads to increased production costs and affects production efficiency.

[0035] Reference Figure 4 P-type body ion implantation is performed into the N-type epitaxial isolation layer 120 to form a P-type body doped region 130.

[0036] Reference Figure 5 A gate structure 140 is formed, and the gate structure 140 penetrates the N-type epitaxial isolation layer 120.

[0037] Understandably, in subsequent processes, dielectric layers, plug structures, metal layers, passivation layers, etc., can be formed to complete the entire SJ-IGBT device. The subsequent operations in the existing technology will not be elaborated upon here.

[0038] The inventors of this invention further discovered through research that in existing methods for improving SJ-IGBT devices, the technical solution of adding an additional N-type epitaxial isolation layer 120 imposes restrictions on the formation sequence of the P-type body doped region 130 and the gate structure 140, since the P-type body doped region 130 is located within the N-type epitaxial isolation layer 120 and the gate structure 140 penetrates through the N-type epitaxial isolation layer 120. It requires strict adherence to the process sequence of "first forming the N-type epitaxial isolation layer 120, then forming the P-type body doped region 130, and finally forming the gate structure 140." The gate structure 140, which is of higher importance, must be formed in the last step. This significantly limits process improvement and process parameter adjustment, hindering device performance optimization.

[0039] In this embodiment of the invention, by forming a P-type body doped region and a P-type pillar, and wherein the first distance between the top surface of the P-type pillar and the surface of the semiconductor substrate is greater than the second distance between the bottom surface of the P-type body doped region and the surface of the semiconductor substrate, the electrical connection between the P-type body doped region and the P-type pillar can be disconnected. Furthermore, by isolating adjacent P-type body doped regions and P-type pillars through a subsequently formed dielectric layer, the problem of carrier (such as holes) being extracted during forward conduction of the device can be effectively mitigated, enhancing device performance. Compared to the prior art, which requires an additional isolation material layer, leading to increased production costs, the technical solution of this embodiment can reduce production costs and improve production efficiency. Furthermore, by adopting the above solution, since both the P-type body doped region and the gate structure are located within the semiconductor substrate, the formation order of the gate structure is not restricted, and there are no limitations on process improvement and process parameter adjustment, which is beneficial for device performance optimization.

[0040] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0041] Reference Figure 6 , Figure 6 This is a flowchart illustrating a method for forming an SJ-IGBT device according to an embodiment of the present invention. The method for forming the SJ-IGBT device may include steps S61 to S64:

[0042] Step S61: Provide a semiconductor substrate;

[0043] Step S62: P-type body ion implantation is performed into the semiconductor substrate to form a P-type body doped region;

[0044] Step S63: Form a P-type pillar in the semiconductor substrate, wherein a first distance between the top surface of the P-type pillar and the surface of the semiconductor substrate is greater than a second distance between the bottom surface of the P-type doped region and the surface of the semiconductor substrate;

[0045] Step S64: Form a dielectric layer that covers the P-type body doped region and the P-type pillar, and isolates adjacent P-type body doped regions and P-type pillars.

[0046] The following is combined Figures 7 to 15 The steps described above will be explained.

[0047] Figures 7 to 15 This is a schematic diagram of the device cross-sectional structure corresponding to each step in the method for forming an SJ-IGBT device in an embodiment of the present invention.

[0048] Reference Figure 7 A semiconductor substrate 200 is provided, and P-type body ion implantation is performed in the semiconductor substrate 200 to form a P-type body doped region 230.

[0049] The semiconductor substrate 200 may be a silicon substrate, or the material of the semiconductor substrate 200 may include germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium. The semiconductor substrate 200 may also be a silicon substrate on an insulator or a germanium substrate on an insulator, or a substrate with an epitaxy layer (Epi layer) grown on it.

[0050] In this embodiment of the invention, the semiconductor substrate 200 is used to form an SJ-IGBT device, and therefore various suitable substrate doping methods that can be used to form an SJ-IGBT device can be adopted.

[0051] As a non-limiting example, a buffer zone and a drift region located above the buffer zone can be formed in the semiconductor substrate 200. The buffer zone can be, for example, heavily N-type doped, and the drift region can be, for example, lightly N-type doped, formed, for example, by epitaxial growth or by doping. It should be noted that the SJ with alternating N-type and P-type pillars can be obtained by forming P-type pillars within the drift region in a subsequent process.

[0052] In specific implementation, conventional ion implantation processes and their process parameters can be used to form the P-type bulk doped region 230. The embodiments of the present invention do not limit the specific process parameters.

[0053] Reference Figure 8A patterned protective layer 201 is formed on the surface of a semiconductor substrate 200. Using the patterned protective layer 201 as a mask, the semiconductor substrate 200 is etched to obtain a P-type pillar trench 211.

[0054] The patterned protective layer 201 may include a hard mask layer, a photoresist layer, and a dielectric protective layer located on the substrate surface.

[0055] It should be noted that, in order to improve the forward conduction effect of the device, the etching depth of the P-type pillar trench 211 can be greater than the preset depth, so as to achieve deep trench etching and obtain a P-type pillar with a larger depth.

[0056] Reference Figure 9 P-shaped column material 212 is formed in the P-shaped column groove 211.

[0057] Specifically, an epitaxial filling process can be used, and P-type doping can be performed during the formation process to obtain P-type pillar material 212.

[0058] It is understood that the top surface of the P-type pillar material 212 may be higher than the surface of the semiconductor substrate 200.

[0059] Reference Figure 10 The P-shaped column material 212 is planarized (Chemical Mechanical Polishing, CMP) to obtain the P-shaped column material layer 213.

[0060] In this embodiment of the invention, a P-type pillar material 212 is first formed in the P-type pillar trench 211, and then the P-type pillar material 212 is planarized to obtain the P-type pillar material layer 213. Before the back etching, the surface of the P-type pillar material 212 can be made flush with or close to flush with the surface of the semiconductor substrate 200, so that the surface of the semiconductor substrate 200 can be used as the starting reference position for the back etching, further improving the accuracy of controlling the depth of the top surface of the P-type pillar.

[0061] In this embodiment of the invention, other suitable methods can also be used to form a P-type pillar material layer 213 with its top surface flush with or higher than the surface of the semiconductor substrate 200, and then the P-type pillar material layer 213 is etched back to obtain the P-type pillar 210. The depth of the top surface of the P-type pillar 210 can be controlled more precisely by using the surface of the semiconductor substrate 200 as a reference position.

[0062] Reference Figure 11The P-shaped column material layer 213 is etched back to obtain the P-shaped column 210.

[0063] like Figure 11 As shown, the distance between the top surface of the P-type pillar 210 and the surface of the semiconductor substrate 200 is the first distance D1, and the distance between the bottom surface of the P-type body doped region 230 and the surface of the semiconductor substrate 200 is the second distance D2.

[0064] Specifically, D1 is greater than D2, so that there is a certain distance between the adjacent P-type body doped region 230 and the P-type pillar 210.

[0065] In practice, the difference between D1 and D2 can disconnect the electrical connection between the P-type body doped region 230 and the P-type pillar 210.

[0066] As a non-limiting example, the ratio of the first distance to the second distance can be greater than a preset ratio, wherein the preset ratio is a rational number greater than 1, for example selected from 1.1 to 1.5, such as 1.2.

[0067] Furthermore, the step of re-etching the P-type pillar material layer 213 may include: using a dry etching process to re-etch the P-type pillar material layer 213; wherein, the etching thickness of the dry etching process is determined based on the second distance, and the larger the second distance, the larger the etching thickness.

[0068] Furthermore, during the etch-back process, a patterned protective layer 201 can be used as a mask layer for etch-back.

[0069] In this embodiment of the invention, by making the first distance D1 greater than the second distance D2, the electrical connection between the P-type body doped region 230 and the P-type pillar 210 can be disconnected, which effectively reduces the problem of carriers (such as holes) being extracted when the device is forward-conducting and enhances the device performance.

[0070] Furthermore, after forming the P-type pillar 210 in the semiconductor substrate 200 and before forming the dielectric layer, a gate structure 240 may be formed in the semiconductor substrate 200.

[0071] Reference Figure 12 A gate structure 240 is formed within a semiconductor substrate 200.

[0072] Specifically, a gate trench (not shown) can be formed in the semiconductor substrate 200 first, then a gate oxide layer (not shown) can be formed on the bottom surface and sidewall surface of the gate trench, and then a gate conductive layer (not shown) can be formed on the surface of the gate oxide layer to form a gate structure 240.

[0073] The gate structure 240 can penetrate the P-type body doped region 230, or it can be located at other suitable positions within the semiconductor substrate 200.

[0074] In specific implementations, according to the formation process of SJ-IGBT devices, after forming the gate structure 240, a source doped region can be formed in the semiconductor substrate 200 on both sides of the gate structure 240.

[0075] It should be noted that the gate structure 240 can be as follows: Figures 7 to 12 The process flow shown is formed after the formation of the P-shaped column 240 and before the formation of the dielectric layer 250, and can also be formed in other process steps.

[0076] In another specific embodiment of the present invention, a gate structure 240 may be formed in the semiconductor substrate 200 before P-type body region ion implantation is performed in the semiconductor substrate 200.

[0077] Specifically, it is possible Figure 7 Prior to the process steps shown, a semiconductor substrate 200 is provided, and a gate structure 240 is formed within the semiconductor substrate 200.

[0078] In another specific embodiment of the present invention, the gate structure 240 may be formed in the semiconductor substrate 200 after P-type body region ion implantation and before P-type pillars 210 are formed in the semiconductor substrate 200.

[0079] Specifically, it is possible Figures 7 to 8 Between the process steps shown, a gate structure 240 is formed within a semiconductor substrate 200.

[0080] In this embodiment of the invention, the P-type body doped region 230, P-type pillar 210 and gate structure 240 in the SJ-IGBT device can be formed using a variety of process sequences. The formation sequence of the gate structure 240 is not strictly limited, which effectively improves process flexibility, facilitates process improvement and process parameter adjustment, and helps to improve device performance optimization.

[0081] Reference Figure 13 A dielectric layer 250 is formed, which covers the P-type body doped region 230 and the P-type pillar 210, and isolates adjacent P-type body doped regions 230 and P-type pillars 210.

[0082] In specific implementations, the dielectric layer 250 can be selected from: a stacked structure of silicon oxide and silicon nitride, a silicon oxide layer, or a silicon nitride layer. The silicon oxide can be, for example, SiO2, and the silicon nitride can be, for example, Si3N4.

[0083] It is understandable that after the P-type pillar material layer 213 is etched back, there is a recessed area on the surface of the semiconductor substrate 200. Therefore, after the dielectric layer 250 is formed, there may also be a recess. At this time, the dielectric layer 250 can be planarized to provide a better process basis for subsequent metal layer processes.

[0084] In this embodiment of the invention, by forming a P-type body doped region 230 and a P-type pillar 210, and wherein the first distance D1 between the top surface of the P-type pillar 210 and the surface of the semiconductor substrate 200 is greater than the second distance D2 between the bottom surface of the P-type body doped region 230 and the surface of the semiconductor substrate 200, the electrical connection between the P-type body doped region 230 and the P-type pillar 210 can be disconnected. Furthermore, by isolating adjacent P-type body doped regions 230 and P-type pillars 210 through a subsequently formed dielectric layer 250, the problem of carriers (such as holes) being extracted during forward conduction of the device can be effectively mitigated, thereby enhancing device performance. Compared to the prior art, which requires an additional isolation material layer, leading to increased production costs, the technical solution of this embodiment of the invention can reduce production costs and improve production efficiency. Furthermore, by adopting the above scheme, since both the P-type body doped region 230 and the gate structure 240 are located within the semiconductor substrate 200, the formation order of the gate structure 240 is not restricted, and there is no limitation on process improvement and process parameter adjustment, which is beneficial to device performance optimization.

[0085] Reference Figure 14 This forms a plug structure (Contact, CT)260.

[0086] Specifically, the dielectric layer 250 can be etched to form a plug hole (not shown), and then a plug structure 260 can be formed in the plug hole.

[0087] The plug structure 260 can be formed at the location of the P-type body doped region 230, or at other suitable locations.

[0088] Reference Figure 15 A metal layer 270 is formed on the surface of the dielectric layer 250, and a capping layer 271 is formed on the surface of the metal layer 270.

[0089] The metal layer 270 can be electrically connected to the plug structure 260, and the plug material in the plug structure 260 that is not covered by the metal layer 270 can be removed during the metal etching process.

[0090] The cover layer 271 is used to protect the metal layer 270, and may include, for example, a passivation layer or a polymer material layer.

[0091] It should be noted that, in the embodiments of the present invention, the back side of the semiconductor substrate 200 may also be processed as needed, such as performing back thinning, forming a field stop layer, forming a shallow doped P-type anode layer on the back side, performing back metallization, etc. The embodiments of the present invention do not impose specific limitations on the processing method and process of the back side.

[0092] In this embodiment of the invention, an SJ-IGBT device is also disclosed, with reference to... Figure 15 It may include: a semiconductor substrate 200; a P-type body doped region 230 located within the semiconductor substrate 200; and a P-type pillar 210 located within the semiconductor substrate 200, wherein a first distance D1 (refer to) is defined between the top surface of the P-type pillar 210 and the surface of the semiconductor substrate 200. Figure 11 The distance D2 between the bottom surface of the P-type bulk doped region 230 and the surface of the semiconductor substrate 200 is greater than the second distance D2 (refer to) Figure 11 The dielectric layer 250 covers the P-type body doped region 230 and the P-type pillar 210, and isolates adjacent P-type body doped regions 230 and P-type pillars 210.

[0093] In this embodiment of the invention, by forming a P-type body doped region 230 and a P-type pillar 210, and wherein the first distance D1 between the top surface of the P-type pillar 210 and the surface of the semiconductor substrate 200 is greater than the second distance D2 between the bottom surface of the P-type body doped region 230 and the surface of the semiconductor substrate 200, the electrical connection between the P-type body doped region 230 and the P-type pillar 210 can be disconnected. Furthermore, by isolating adjacent P-type body doped regions 230 and P-type pillars 210 through a subsequently formed dielectric layer 250, the problem of carriers (such as holes) being extracted during forward conduction of the device can be effectively mitigated, thereby enhancing device performance. Compared to the prior art, which requires an additional isolation material layer, leading to increased production costs, the technical solution of this embodiment of the invention can reduce production costs and improve production efficiency. Furthermore, by adopting the above scheme, since both the P-type body doped region 230 and the gate structure 240 are located within the semiconductor substrate 200, the formation order of the gate structure 240 is not restricted, and there is no limitation on process improvement and process parameter adjustment, which is beneficial to device performance optimization.

[0094] Furthermore, the SJ-IGBT device may further include: a gate structure 240 located within the semiconductor substrate 200; wherein the gate structure 240 is formed prior to the formation of the P-type body doped region 230.

[0095] Furthermore, the SJ-IGBT device may further include: a gate structure 240 located within the semiconductor substrate 200; wherein the gate structure 240 is formed after the formation of the P-type body doped region 230 and before the formation of the P-type pillar 210.

[0096] Furthermore, the SJ-IGBT device may further include: a gate structure 240 located within the semiconductor substrate 200; wherein the gate structure 240 is formed after the formation of the P-type pillar 210 and before the formation of the dielectric layer 250.

[0097] For the principles, specific implementation, and beneficial effects of the SJ-IGBT device, please refer to the previous description of the formation method of the SJ-IGBT device; it will not be repeated here.

[0098] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0099] In the embodiments of this application, "multiple" refers to two or more.

[0100] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0101] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming an SJ-IGBT device, characterized in that, include: Provide semiconductor substrates; P-type body ion implantation is performed into the semiconductor substrate to form a P-type body doped region; A P-type pillar is formed within the semiconductor substrate, wherein a first distance between the top surface of the P-type pillar and the surface of the semiconductor substrate is greater than a second distance between the bottom surface of the P-type doped region and the surface of the semiconductor substrate; A dielectric layer is formed, which covers the P-type body-doped region and the P-type pillar, and isolates adjacent P-type body-doped regions and P-type pillars to disconnect the electrical connection between the P-type body-doped region and the P-type pillar; wherein Before performing P-type body ion implantation into the semiconductor substrate, a gate structure is formed in the semiconductor substrate; or After P-type body ion implantation into the semiconductor substrate and before the formation of P-type pillars in the semiconductor substrate, a gate structure is formed in the semiconductor substrate; or After forming the P-type pillars in the semiconductor substrate and before forming the dielectric layer, a gate structure is formed in the semiconductor substrate.

2. The method for forming the SJ-IGBT device according to claim 1, characterized in that, Forming P-type pillars within the semiconductor substrate includes: A P-type pillar material layer is formed, wherein the top surface of the P-type pillar material layer is flush with or higher than the surface of the semiconductor substrate; The P-shaped column material layer is etched back to obtain the P-shaped column.

3. The method for forming an SJ-IGBT device according to claim 2, characterized in that, Forming a P-shaped columnar material layer includes: The semiconductor substrate is etched to obtain P-type pillar trenches; P-shaped column material is formed within the P-shaped column groove; The P-shaped column material is planarized to obtain the P-shaped column material layer.

4. The method for forming an SJ-IGBT device according to claim 2, characterized in that, Etching back the P-type columnar material layer includes: The P-type columnar material layer is etched back using a dry etching process; The etching thickness of the dry etching process is determined based on the second distance; the larger the second distance, the larger the etching thickness.

5. An SJ-IGBT device, characterized in that, include: Semiconductor substrate; The P-type bulk doped region is located within the semiconductor substrate; A P-type pillar is located within the semiconductor substrate, wherein a first distance between the top surface of the P-type pillar and the surface of the semiconductor substrate is greater than a second distance between the bottom surface of the P-type doped region and the surface of the semiconductor substrate; A dielectric layer covers the P-type body doped region and the P-type pillar, and isolates adjacent P-type body doped regions and P-type pillars so that the electrical connection between the P-type body doped region and the P-type pillar is disconnected. A gate structure is located within the semiconductor substrate; wherein The gate structure is formed before the formation of the P-type body doped region; or The gate structure is formed after the formation of the P-type body doped region and before the formation of the P-type pillar; or The gate structure is formed after the P-type pillar is formed and before the dielectric layer is formed.

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