Capacitor, semiconductor element, and method for manufacturing the capacitor

Abstract

The present disclosure provides a capacitor, a semiconductor element having the capacitor, and a method of manufacturing the capacitor. The semiconductor element has a plurality of memory cells, at least one of which includes a capacitor. The capacitor has a first electrode including titanium nitride and disposed on a substrate, a dielectric film disposed on the first electrode, a multilayer film disposed on the dielectric film, and a second electrode including titanium nitride and disposed on the multilayer film. The method of manufacturing the capacitor includes forming the first electrode including titanium nitride on the substrate, forming a dielectric film on the first electrode, forming the multilayer film on the dielectric film, and forming the second electrode including titanium nitride on the multilayer film.

Description

[0001] CROSS REFERENCE

[0002] This application claims priority to and the benefit of U.S. Nonprovisional Application No. 17 / 358,195, filed June 25, 2021, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates to a capacitor, a semiconductor device having the same, and a method of manufacturing the same. In particular, it relates to a structurally stable capacitor and a method of manufacturing the same. BACKGROUND

[0004] The semiconductor industry has experienced rapid growth due to improvements in integration density. However, as device features shrink and the size of each unit capacitor of a plurality of memory cells shrinks, conformal and thin film formation of stacked capacitors is often required. Due to the collapse and deformation of the lower electrode, the stacked capacitors often exhibit a wobbling phenomenon, which can result in excessive leakage current and device failure. Therefore, there is a great need for structurally stable capacitors and methods of manufacturing such capacitors for semiconductor devices.

[0005] The above description of background art is provided merely for better understanding of the present disclosure and should not be taken in any way as an acknowledgement or any form of suggestion that the prior art described herein is prior art of the present disclosure, and any description of the prior art in the above should not be considered as part of the present disclosure. SUMMARY

[0006] One embodiment of the present disclosure provides a capacitor, comprising a first electrode comprising a tensile portion disposed on a substrate; a dielectric film comprising a compressive portion disposed on the first electrode, wherein the first electrode and the dielectric film form a hybrid lower electrode; a multi-layer film disposed on the dielectric film; and a second electrode comprising titanium nitride disposed on the multi-layer film.

[0007] In some embodiments, the dielectric film comprises aluminum oxide.

[0008] In some embodiments, the first electrode, the dielectric film, and the multi-layer film are configured to structurally stabilize the capacitor.

[0009] In some embodiments, the multi-layer film is configured as a stacked structure comprising a first material layer, a second material layer disposed on the first material layer, a third material layer disposed on the second material layer, and a fourth material layer disposed on the third material layer.

[0010] In some embodiments, the first material layer comprises hafnium.

[0011] In some embodiments, the second material layer and the fourth material layer comprise zirconium oxide.

[0012] In some embodiments, the third material layer comprises aluminum oxide.

[0013] Another embodiment of the disclosure provides a semiconductor device, comprising a plurality of memory cells, at least one of the memory cells comprising a capacitor, the capacitor comprising: a first electrode comprising a tensile portion disposed on a substrate; a dielectric film comprising a compressive portion disposed on the first electrode, wherein the first electrode and the dielectric film form a hybrid lower electrode; a multilayer film disposed on the dielectric film; and a second electrode comprising titanium nitride disposed on the multilayer film.

[0014] In some embodiments, the dielectric film comprises aluminum oxide.

[0015] In some embodiments, the dielectric film and the multilayer film are configured to structurally stabilize the capacitor.

[0016] In some embodiments, the multilayer film is configured as a stack structure comprising a first material layer, a second material layer, a third material layer, and a fourth material layer, the second material layer disposed on the first material layer, the third material layer disposed on the second material layer, and the fourth material layer disposed on the third material layer.

[0017] In some embodiments, the first material layer comprises hafnium.

[0018] In some embodiments, the second material layer and the fourth material layer comprise zirconium oxide.

[0019] In some embodiments, the third material layer comprises aluminum oxide.

[0020] Another embodiment of the disclosure provides a method of manufacturing a semiconductor device. The method of manufacturing comprises forming a first electrode comprising a tensile portion on a substrate; forming a dielectric film comprising a compressive portion on the first electrode, wherein the first electrode and the dielectric film form a hybrid lower electrode; forming a multilayer film on the dielectric film; and forming a second electrode comprising titanium nitride on the multilayer film.

[0021] In some embodiments, the dielectric film comprises aluminum oxide.

[0022] In some embodiments, the method of manufacturing further comprises configuring the dielectric film and the multilayer film to structurally stabilize the capacitor.

[0023] In some embodiments, the method of making further comprises configuring the multilayer film into a stack structure comprising a first material layer, a second material layer, a third material layer, and a fourth material layer, the second material layer disposed on the first material layer, the third material layer disposed on the second material layer, and the fourth material layer disposed on the third material layer.

[0024] In some embodiments, the first material layer comprises hafnium, and the second material layer and the fourth material layer comprise zirconium oxide.

[0025] In some embodiments, the third material layer comprises aluminum oxide.

[0026] Accordingly, the capacitors described in the various embodiments of the present disclosure maintain structural stability in the memory cells of the semiconductor devices. Configuring the first electrode, the high dielectric constant dielectric film, and the multilayer film balances the stress and strain profile on the capacitor to structurally stabilize the capacitor. Because the hybrid lower electrode of the capacitor includes tensile and compressive films formed from the first electrode, the dielectric film, and the multilayer film, the capacitor maintains structural stability after oxide removal because the stress and strain profile on the cylindrical portion of the capacitor has been optimally adjusted. Accordingly, the capacitor has desirable characteristics such as leakage current minimization and can be used in semiconductor devices such as DRAMs even as device features shrink.

[0027] The foregoing has outlined rather broadly the technical features and advantages of the present disclosure so that the detailed description of the present disclosure that follows can be better understood. Additional technical features and advantages of the present disclosure will be described below. The present disclosure is directed to all such technical features and advantages of the present disclosure. It should be appreciated that the concepts and technologies disclosed herein can be employed in a variety of other specific embodiments and examples without departing from the spirit and scope of the present disclosure. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments described herein. It is therefore to be understood that any embodiments disclosed herein are merely examples used to describe and enable those skilled in the art to practice the present disclosure. Numerous modifications and adaptations will be apparent to those skilled in the art without departing from the spirit and scope of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0028] The present disclosure will be more fully understood from the following detailed description taken in connection with the accompanying drawings, in which like reference numerals refer to like elements throughout the figures, and in which:

[0029] Figure 1 is a schematic cross-sectional view illustrating a capacitor of some embodiments of the present disclosure.

[0030] Figure 2 is a schematic cross-sectional view illustrating a capacitor of some embodiments of the present disclosure.

[0031] Figure 3 This is a cross-sectional schematic diagram illustrating a memory cell of some embodiments of the present disclosure.

[0032] Figure 4 This is a three-dimensional schematic diagram illustrating a semiconductor element according to some embodiments of the present disclosure.

[0033] Figure 5 This is a flowchart illustrating a method for preparing a capacitor according to some embodiments of the present disclosure.

[0034] Figure 6 This is a flowchart illustrating several additional steps in the method for preparing the capacitor according to some embodiments of this disclosure.

[0035] Figure 7 This is a block diagram illustrating an electronic system comprising multiple semiconductor elements having multiple capacitors, according to some embodiments of the present disclosure.

[0036] Figure 8 This is a block diagram illustrating a memory card comprising multiple semiconductor elements having multiple capacitors, according to some embodiments of the present disclosure.

[0037] Explanation of reference numerals in the attached figures:

[0038] 10: Capacitor

[0039] 20: Capacitor

[0040] 24: Transistor

[0041] 30: Memory cell

[0042] 40: Semiconductor components

[0043] 101: Base

[0044] 102: First electrode

[0045] 103: Dielectric film

[0046] 104: First material layer

[0047] 105: Second material layer

[0048] 106: Third material layer

[0049] 107: Fourth Material Layer

[0050] 108: Second electrode

[0051] 110: Hybrid Lower Electrode

[0052] 140: Multilayer film

[0053] 201: Base

[0054] 202: first electrode

[0055] 203: dielectric film

[0056] 204: first material layer

[0057] 205: second material layer

[0058] 206: third material layer

[0059] 207: fourth material layer

[0060] 208: second electrode

[0061] 210: source

[0062] 212: drain

[0063] 214: gate

[0064] 240: multilayer film

[0065] 500: manufacturing method

[0066] 1100: electronic system

[0067] 1110: controller

[0068] 1120: input / output device

[0069] 1130: memory

[0070] 1140: interface

[0071] 1150: bus

[0072] 1200: memory card

[0073] 1210: memory

[0074] 1221: static random access memory

[0075] 1222: central processing unit

[0076] 1223: host interface

[0077] 1224: error correction code

[0078] 1225: memory interface

[0079] 1230: host

[0080] BL: bit line

[0081] S501: step

[0082] S502: step

[0083] S503: Step

[0084] S504: Step

[0085] S505: Step

[0086] S506: Step

[0087] WL: word line DETAILED DESCRIPTION

[0088] Embodiments or examples of the disclosure shown in the drawings are now described using specific language. It will be understood that the scope of the present disclosure is not intended to be limited thereby. Any modifications or improvements of the described embodiments, and any further applications of the principles described herein, are contemplated by those skilled in the art to which the present disclosure pertains. Element numbers can be repeated throughout the embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they share the same element number.

[0089] It should be understood that although the terms “first,” “second,” “third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a “first element,” “component,” “region,” “layer,” or “section” discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

[0090] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and / or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0091] As used herein, the term "feature" refers to a portion of a pattern, such as a line, space, via, pillar, trench, slot, or moat. As used herein, the term "core" refers to a mask feature formed at a vertical level. As used herein, the term "target layer" refers to a layer in which a pattern cup of a semiconductor structure is formed. A target layer can be a metal layer, a semiconductor layer, and / or an isolation layer formed on the substrate.

[0092] As used herein, the terms "patterning" or "patterned" are used in the present disclosure to describe an operation of forming a predetermined pattern on a surface. The patterning operation includes different steps and processes and varies depending on different embodiments. In some embodiments, a patterning process is adapted to pattern an existing film or layer. The patterning process includes forming a mask on the existing film or layer, and removing the film or layer not masked by an etching process or other removal process. The mask can be a photoresist or a hard mask. In some embodiments, a patterning process is adapted to directly form a patterned layer on a surface. The patterning process includes forming a photoresist film on the surface; performing a photolithography process; and performing a developing process. The remaining photoresist film is retained and integrated into the semiconductor device.

[0093] Figure 1 is a cross-sectional schematic diagram illustrating a capacitor 10 of some embodiments of the present disclosure. Please refer to Figure 1 The capacitor 10 can be a metal-insulator-metal (MIM) capacitor and include a substrate 101, a first electrode 102, a dielectric film 103, a multi-layer film 140, and a second electrode 108. In some embodiments, the first electrode 102 and the dielectric film 103 form a hybrid lower electrode 110 of the capacitor 10, and the hybrid lower electrode 110 includes a tensile portion implemented by the first electrode 102 and a compressive portion implemented by the dielectric film 103; conversely, the second electrode 108 acts as an upper electrode of the MIM capacitor 10. In some embodiments, the first electrode 102 can include titanium nitride (TiN) and can be disposed on the substrate 101. The first electrode 102 can be a tensile film configured to optimize the tensile strength of the capacitor 10. The dielectric film 103 can include aluminum oxide (AI2O3) and can be disposed on the first electrode 102. In some embodiments, the dielectric film 103 can be a compressive film configured to optimize the compressive strength of the capacitor 10.

[0094] Please refer to Figure 1A multi-layer film 140 is disposed on the dielectric film 103 and serves as a capacitor insulator between the two metal electrodes of the MIM capacitor. In some embodiments, the multi-layer film 140 can be configured as a stack structure including a first material layer 104, a second material layer 105 disposed on the first material layer 104, a third material layer 106 disposed on the second material layer 105, and a fourth material layer 107 disposed on the third material layer 106.

[0095] In some embodiments, the first material layer 104 includes hafnium (Hf), although the present disclosure is not limited thereto. In some embodiments, for example, the first material layer 104 can include at least one of Si, Sn, Sr, Ti, Y, La, Ga, Gd, Ge, Al, Co, or combinations thereof. In some embodiments, the second electrode 108 includes TiN and can be disposed on the multi-layer film 140. It should be understood that in other embodiments of the present disclosure, for example, one or both of the first electrode 102 and the second electrode 108 can include other materials, such as titanium oxide (TiO). In some embodiments, the second material layer 105 and the fourth material layer 107 include zirconium oxide (ZrO2). In some embodiments, the third material layer 106 includes Al2O3, and thus the multi-layer film 140 can be configured as a HZAZ stack structure (i.e., Hf / ZrO2 / Al2O3 / ZrO2) on the dielectric film 103.

[0096] In some embodiments, the substrate 101 can include any suitable material, including Si, SiC, SiGe, SiGeC, GaAs, InP, InAs, and other II-VI or III / V compound semiconductors, although the present disclosure is not limited thereto. In some embodiments, the substrate 101 can also include other elements, such as transistors, resistors, capacitors, diodes, and the like. In some embodiments, the substrate 101 can also include an interconnect structure (not shown), including an interleaved stack of wiring layers and vias disposed above the elements, and one or more interlayer dielectrics surrounding the wiring layers and vias (not shown). For example, the substrate 101 can include a semiconductor wafer, a semiconductor chip, or a wafer portion. The substrate 101 can include interleaved dielectrics and interconnect layers disposed on an upper metal layer (not shown). It should be understood that the substrate 101 can be any variation of other different structures known to those skilled in the art, including ceramic and organic-based substrates, although the present disclosure is not limited thereto.

[0097] Figure 2 is a cross-sectional view illustrating a capacitor 10 in accordance with some embodiments of the present disclosure. Please refer to Figure 2In some embodiments, configuring the first electrode 102, the high-k dielectric film 103, and the multi-layer film 140 balances the stress and strain distribution on the capacitor 10 to structurally stabilize the capacitor 10. Since the hybrid lower electrode of the capacitor 10, which includes the tensile and compressive films formed by the first electrode 102, the dielectric film 103, and the multi-layer film 140, the capacitor 10 can maintain structural stability after oxide removal because the stress and strain distribution on the cylindrical portion of the capacitor 10 has been optimally adjusted. Thus, the capacitor 10 has desirable characteristics such as leakage current minimization and can be used in semiconductor devices such as DRAMs even when device features are scaled down to ~10 nm technology nodes.

[0098] During the formation of the capacitor 10, before forming the multi-layer film 140 on the hybrid lower electrode and forming the second electrode 108 on the multi-layer film 140, the fabrication technique of the hybrid lower electrode in the cylindrical profile includes an oxide removal process, and the hybrid lower electrode in the cylindrical profile can maintain structural stability after the oxide removal process because the stress and strain distribution on the cylindrical hybrid lower electrode has been optimally adjusted. Thus, the capacitor 10 has desirable characteristics such as leakage current minimization and can be used in semiconductor devices such as DRAMs even when device features are scaled down.

[0099] Figure 3 is a cross-sectional schematic diagram illustrating a memory cell 30 of some embodiments of the present disclosure. Figure 4 is a perspective schematic diagram illustrating a semiconductor device 40 of some embodiments of the present disclosure. Please refer to Figure 3 and Figure 4In some embodiments, the semiconductor element 40 can be a DRAM including a plurality of memory cells 30. At least one of the memory cells 30 can include a capacitor 20 and a transistor 24. The transistor 24 of the memory cell 30 can be a vertical pillar metal-oxide-semiconductor (MOS) transistor having a gate 214, a source 210, and a drain 212. The gate 214 is typically connected to a word line WL, and one of the source 210 and the drain 212 is connected to a bit line BL. The capacitor 20 has a lower or storage electrode (e.g., a first electrode 202) and an upper or plate electrode (e.g., a second electrode 208). In some embodiments, the storage electrode can be connected to the other one of the source 210 and the drain 212, and the plate electrode can be connected to a reference potential conductor. When the transistor 24 is turned on by an active level of the word line, data is read from or written into the capacitor 20 via the bit line.

[0100] In some embodiments, the capacitor 20 can be similar to the capacitor 10 previously described in this disclosure. The capacitor 20 includes a substrate 201, a first electrode 202, a dielectric film 203, a multi-layer film 240, and a second electrode 208. In some embodiments, the first electrode 202 can include TiN and can be disposed on the substrate 201. The first electrode 202 can be a tensile film configured to optimize the tensile strength of the capacitor 20. The dielectric film 203 can include AI2O3 and can be disposed on the first electrode 202. In some embodiments, the dielectric film 203 can be a high dielectric constant compressive film configured to optimize the compressive strength of the capacitor. The multi-layer film 240 is disposed on the dielectric film 203. In some embodiments, the multi-layer film 240 can be configured as a stack structure including a first material layer 204, a second material layer 205 disposed on the first material layer 204, a third material layer 206 disposed on the second material layer 205, and a fourth material layer 207 disposed on the third material layer 206.

[0101] In some embodiments, the first material layer 204 comprises hafnium (Hf), although this disclosure is not limited thereto. In some embodiments, for example, the first material layer 204 may comprise at least one of the following: Si, Sn, Sr, Ti, Y, La, Ga, Gd, Ge, Al, Co, or combinations thereof. In some embodiments, the second electrode 208 comprises TiN and may be disposed on the multilayer film 240. It should be understood that in other embodiments of this disclosure, for example, one or both of the first electrode 202 and the second electrode 208 may comprise other materials, such as titanium oxide (TiO), or other conductive metal nitrides, such as cobalt nitride, nickel nitride, molybdenum nitride, tantalum nitride, titanium aluminum nitride, tungsten nitride, or combinations thereof. In some embodiments, the second material layer 205 and the fourth material layer 207 comprise zirconium oxide (ZrO2). In some embodiments, the third material layer 206 comprises Al2O3, and thus the multilayer film 240 may be configured as an HZAZ stacked structure (i.e., Hf / ZrO2 / Al2O3 / ZrO2) on the dielectric film 203.

[0102] Please refer to the capacitors 10 and 20 described earlier in this disclosure, and a method for manufacturing a capacitor may also be described in detail. Figure 5 This is a flowchart illustrating a method 500 for preparing a capacitor 10 according to some embodiments of the present disclosure. Figure 6 This is a flowchart illustrating several additional steps in the method 500 for fabricating capacitor 10, as described in some embodiments of this disclosure. Please refer to... Figure 5 and Figure 6 The method 500 for fabricating capacitor 10 may include forming a first electrode 102 containing TiN on a substrate 101 (step S501). For example, the titanium nitride fabrication technique for the first electrode 102 may include PVD, PECVD, CVD, or ALD. In some embodiments, the first electrode 102 may be optionally subjected to an RTA annealing treatment before the dielectric film 103 and the multilayer film 140 are formed. In step S502, the dielectric film 103 is disposed on the first electrode 102; and in step S503, the multilayer film 140 is disposed on the dielectric film 103. For example, the fabrication techniques for the dielectric film 103 and the multilayer film 140 may include ALD, PE-ALD, PECVD, or CVD. In step S504, a second electrode 108 containing TiN is disposed on the multilayer film 140 (step S504). The titanium nitride fabrication technique for the second electrode 108 may include PVD, PECVD, CVD, or ALD. In some embodiments, for example, capacitor 10 may also be subjected to pre-metal annealing (PMS) treatment.

[0103] In some embodiments, the dielectric film 103 comprises Al2O3. In some embodiments, the fabrication technique for the compressed dielectric film 103 may include a BPSG wet oxide etching process. In some embodiments, such as Figure 6 As shown, the preparation method 500 further includes configuring a dielectric film 103 and a multilayer film 140 to structurally stabilize the capacitor 10 (step S505). In some embodiments, the dielectric film 103 may be a high dielectric constant compression film configured to optimize the compression strength of the capacitor 10. In some embodiments, the preparation method 500 may further include configuring the multilayer film 1140 into a stacked structure, which includes a first material layer 104; a second material layer 105 disposed on the first material layer 104; a third material layer 106 disposed on the second material layer 105; and a fourth material layer 107 disposed on the third material layer 106 (step S506). In some embodiments, the first material layer 104 contains hafnium, while the second material layer 105 and the fourth material layer 107 contain zirconium oxide. In some embodiments, the third material layer 106 contains Al2O3.

[0104] Figure 7 This is a block diagram illustrating an electronic system 1100 comprising multiple semiconductor elements having multiple capacitors, according to some embodiments of this disclosure. Please refer to... Figure 7According to some embodiments of the present disclosure, the electronic system 1100 can include a controller 1110, an input / output (I / O) device 1120, a memory 1130, an interface 1140, and a bus 1150. The controller 1110, the I / O device 1120, the memory 1130, and / or the interface 1140 can be connected to each other via the bus 1150. The bus 1150 can correspond to a path through which data moves. The controller 1110 can include at least one of a microprocessor, a digital signal processor, a microcontroller, and a plurality of logic elements capable of performing functions similar to those performed by the elements. The I / O device 1120 can include a keypad, a keyboard, a display device, and the like. The memory 1130 can store data and / or instructions. According to some embodiments of the present disclosure, the memory 1130 can include a plurality of semiconductor elements. For example, the memory 1130 can include a DRAM. The interface 1140 can transmit / receive data to / from a communication network. The interface 1140 can be wired or wireless. For example, the interface 1140 can include an antenna or a wired / wireless transceiver. In some embodiments, the electronic system 1100 can be applied to a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or any form of electronic device capable of transmitting / receiving information in a wireless environment.

[0105] Figure 8 is a block diagram illustrating a memory card including a plurality of semiconductor elements having a plurality of capacitors according to some embodiments of the present disclosure. Referring to Figure 8 A memory card 1200 including the semiconductor elements according to various embodiments of the present disclosure can be used. In some embodiments, the memory card 1200 can include a memory controller 1220 that controls data conversion between a host 1230 and a memory 1210. A static random access memory (SRAM) 1221 can be used as an operation memory of a central processing unit (CPU) 1222. A host interface 1223 can include a protocol for exchanging data by allowing the host 1230 to be connected to the memory card 1200. An error correction code (ECC) 1224 can detect an error from data read from the memory 1210 and then correct the detected error. A memory interface 1225 can be connected with the memory 1210. The CPU 1222 can perform overall control operations associated with data conversion of the memory controller 1220.

[0106] Accordingly, in various embodiments described in the present disclosure, the capacitors maintain structural stability in the memory cell structures of the semiconductor devices. The first electrode 102, the high-k dielectric film 103, and the multi-layer film 140 are configured to stabilize the capacitor 10 structurally by balancing the stress and strain distribution on the capacitor 10. Because of the hybrid lower electrode of the capacitor 10, which includes the tensile and compressive films formed by the first electrode 102, the dielectric film 103, and the multi-layer film 140, the capacitor can maintain structural stability after oxide removal because the stress and strain distribution on the cylindrical portion of the capacitor has been optimally adjusted. Thus, the capacitor 10 has desirable characteristics such as leakage current minimization and can be used in semiconductor devices such as DRAMs even when device features are scaled down.

[0107] One embodiment of the present disclosure provides a capacitor, comprising a first electrode including a tensile portion disposed on a substrate; a dielectric film including a compressive portion disposed on the first electrode, wherein the first electrode and the dielectric film form a hybrid lower electrode; a multi-layer film disposed on the dielectric film; and a second electrode comprising titanium nitride disposed on the multi-layer film.

[0108] Another embodiment of the present disclosure provides a semiconductor device, comprising a plurality of memory cells, at least one of the memory cells including a capacitor, the capacitor comprising: a first electrode including a tensile portion disposed on a substrate; a dielectric film including a compressive portion disposed on the first electrode, wherein the first electrode and the dielectric film form a hybrid lower electrode; a multi-layer film disposed on the dielectric film; and a second electrode comprising titanium nitride disposed on the multi-layer film.

[0109] While the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the techniques described above can be implemented in different methodologies than those described above, and other techniques or combinations thereof can be employed in the practice of the present disclosure.

[0110] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Accordingly, the disclosure of one or more embodiments of the present application is intended to be illustrative, but not limiting, of the scope of the present application. Thus, the scope of the present application should be determined by the appended claims and equivalents thereof.

Claims

1. A capacitor, comprising: a first electrode comprising a tensile portion disposed on a substrate; a dielectric film comprising a compressive portion disposed on the first electrode, wherein the first electrode and the dielectric film form a hybrid down electrode; a multilayer film disposed on the dielectric film, wherein the multilayer film is configured in a stack structure comprising a first material layer, a second material layer, a third material layer, and a fourth material layer, the first material layer being disposed directly on the dielectric film, the second material layer being disposed on the first material layer, the third material layer being disposed on the second material layer, the fourth material layer being disposed on the third material layer, and wherein the first material layer comprises hafnium, the second material layer and the fourth material layer comprise zirconium oxide, and the third material layer comprises aluminum oxide; and a second electrode comprising titanium nitride disposed on the multilayer film.

2. The capacitor of claim 1, wherein the first electrode comprises titanium nitride, and the dielectric film comprises aluminum oxide.

3. The capacitor of claim 1, wherein the first electrode, the dielectric film, and the multilayer film are configured to structurally stabilize the capacitor.

4. A semiconductor device, comprising: a plurality of memory cells, at least one of the plurality of memory cells comprising a capacitor, the capacitor comprising: a first electrode comprising a tensile portion disposed on a substrate; a dielectric film comprising a compressive portion disposed on the first electrode, wherein the first electrode and the dielectric film form a hybrid down electrode; a multilayer film disposed on the dielectric film, wherein the multilayer film is configured in a stack structure comprising a first material layer, a second material layer, a third material layer, and a fourth material layer, the first material layer being disposed directly on the dielectric film, the second material layer being disposed on the first material layer, the third material layer being disposed on the second material layer, the fourth material layer being disposed on the third material layer, and wherein the first material layer comprises hafnium, the second material layer and the fourth material layer comprise zirconium oxide, and the third material layer comprises aluminum oxide; and a second electrode comprising titanium nitride disposed on the multilayer film.

5. The semiconductor device of claim 4, wherein the first electrode comprises titanium nitride, and the dielectric film comprises aluminum oxide.

6. The semiconductor device of claim 4, wherein the first electrode, the dielectric film, and the multilayer film are configured to structurally stabilize the capacitor.

7. A method of fabricating a semiconductor device, comprising: forming a first electrode comprising a tensile portion on a substrate; forming a dielectric film comprising a compressive portion on the first electrode, wherein the first electrode and the dielectric film form a hybrid down electrode; depositing a multilayer film on the dielectric film in a stack structure, wherein the stack structure includes a first material layer, a second material layer, a third material layer, and a fourth material layer, the first material layer is directly deposited on the dielectric film, the second material layer is deposited on the first material layer, the third material layer is deposited on the second material layer, the fourth material layer is deposited on the third material layer, and wherein the first material layer includes hafnium, the second material layer and the fourth material layer include zirconium oxide, and the third material layer includes aluminum oxide; and forming a second electrode including titanium nitride on the multilayer film.

8. The method of claim 7, wherein the first electrode includes titanium nitride, and the dielectric film includes aluminum oxide.

9. The method of claim 7, further comprising configuring the first electrode, the dielectric film, and the multilayer film to structurally stabilize a capacitor.

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