Wafer testing method, device, equipment and storage medium

Abstract

The present disclosure provides a wafer testing method, apparatus, device, and storage medium. The wafer testing method includes: obtaining wafer batch information and multiple sets of preset test conditions; based on each set of preset test conditions, testing a preset number of bare die in the same batch of wafers, obtaining target sampling time points corresponding to each set of preset test conditions; and testing the remaining bare die in the same batch of wafers based on each set of preset test conditions and their corresponding target sampling time points. By obtaining target sampling points for a preset number of bare die in the same batch of wafers under each set of preset test conditions, and then testing the remaining bare die under the same conditions based on the preset test conditions and wafer batch information for obtaining the target sampling points, the difference between the sampling time points during the wafer testing process and the time points of the bare die's output signals is reduced, thereby improving the accuracy of wafer testing and the yield of the bare die.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a wafer testing method, apparatus, device, and storage medium. Background Art

[0002] After wafer manufacturing is complete, a certain amount of defective die will be found among the dies distributed across the wafer. Wafer testing is used to identify these defective dies, thereby improving product yield and reducing production costs. During the testing process, the timing of the wafer's output signal varies significantly due to factors such as the manufacturing process, test temperature, and test voltage. Therefore, the accuracy of the timing of sampling the die's output signal has a significant impact on the die's yield.

[0003] Currently, when sampling the output signal of a bare chip, testers usually manually set the sampling time point. This sampling time point may differ from the time point of the output signal, resulting in low wafer test accuracy and loss of bare chip yield. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] The present disclosure provides a wafer testing method, apparatus, equipment and storage medium.

[0006] According to a first aspect of an embodiment of the present disclosure, a wafer testing method is provided, the wafer testing method comprising:

[0007] Obtain wafer batch information and multiple sets of preset test conditions;

[0008] Based on each set of the preset test conditions, a preset number of dies in the same batch of wafers are tested respectively to obtain a target sampling time point corresponding to each set of the preset test conditions;

[0009] The remaining dies in the same batch of wafers are tested according to each set of the preset test conditions and the corresponding target sampling time point.

[0010] According to some embodiments of the present disclosure, each set of preset test conditions includes temperature information and multiple voltage information.

[0011] According to some embodiments of the present disclosure, based on each set of preset test conditions, a preset number of dies in the same batch of wafers are tested separately to obtain target sampling time points corresponding to each set of the preset test conditions, including:

[0012] Under each set of preset test conditions, performing write and read operations on each of the preset number of bare chips to collect test information of the bare chips;

[0013] When the test information meets the preset conditions, the test is stopped and the time information of the test stopping moment is obtained as reference time information;

[0014] The target sampling time point corresponding to each set of the preset test conditions is determined according to the reference time information.

[0015] According to some embodiments of the present disclosure, performing write and read operations on each of the preset number of dies under each set of preset test conditions to collect test information of the dies includes:

[0016] Start testing under the preset test conditions and wait for a first preset time period;

[0017] After waiting for the first preset time period, a write / read operation is performed on each of the preset number of dies at intervals of a second preset time period, and test information corresponding to the write / read operation is collected.

[0018] According to some embodiments of the present disclosure, the wafer testing method further includes:

[0019] When the cumulative test duration of each die reaches a third preset duration since the start of the test, and all the obtained test information does not meet a preset condition, the test is stopped and it is determined that the die has an abnormality.

[0020] According to some embodiments of the present disclosure, the wafer testing method further includes:

[0021] If the collected test information does not meet the preset condition, the number of times the preset condition is not met is recorded, and the test is continued.

[0022] According to some embodiments of the present disclosure, the test information includes sampled voltage information, and the preset condition includes a reference voltage value;

[0023] The test information meets the preset conditions, including:

[0024] The sampled voltage information is greater than the reference voltage value.

[0025] According to some embodiments of the present disclosure, determining the target sampling time point corresponding to each set of the preset test conditions according to the reference time information includes:

[0026] Acquiring period information of the sampled voltage information;

[0027] The sum of the preset multiple of the period information and the reference time information is used as the target sampling time point.

[0028] According to some embodiments of the present disclosure, a method for determining the reference time information includes:

[0029] Calculating the product of the number of times the test information fails to meet the preset condition and the second preset time length;

[0030] The sum of the product and the first preset time length is used as the reference time information.

[0031] According to some embodiments of the present disclosure, the preset multiple is one quarter to three quarters; and / or,

[0032] The first preset time length is 4ns to 6ns; and / or,

[0033] The second preset time length is 0.15ns to 0.25ns;

[0034] The third preset time length is 14ns to 16ns.

[0035] According to some embodiments of the present disclosure, testing the remaining dies in the wafer batch according to the target sampling time point includes:

[0036] Under each set of the preset test conditions, testing the remaining dies according to the target sampling time points corresponding to the preset test conditions;

[0037] Acquire sampling information of each of the remaining dies, and if each of the sampling information satisfies the preset condition, the remaining dies are normal;

[0038] If the sampling information in the remaining dies does not meet the preset condition, the die corresponding to the sampling information that does not meet the preset condition is abnormal.

[0039] According to a second aspect of an embodiment of the present disclosure, a wafer testing device is provided, comprising:

[0040] an acquisition module configured to acquire wafer batch information and multiple sets of preset test conditions;

[0041] The first testing module is configured to test a preset number of dies in the same batch of wafers based on each set of preset testing conditions, and obtain a target sampling time point corresponding to each set of preset testing conditions;

[0042] The second testing module is configured to test the remaining bare dies in the same batch of wafers according to each set of the preset testing conditions and the corresponding target sampling time point.

[0043] According to some embodiments of the present disclosure, the first test module includes:

[0044] A collection device is configured to perform write and read operations on each of the preset number of the bare chips under each set of the preset test conditions to collect test information of the bare chips;

[0045] A first determining module is configured to stop the test and obtain time information of the test stopping moment as reference time information when the test information meets a preset condition;

[0046] The second determining module is configured to determine the target sampling time point corresponding to each set of the preset test conditions according to the reference time information.

[0047] According to some embodiments of the present disclosure, the second test module includes:

[0048] a third testing module configured to test the remaining dies under each set of the preset test conditions according to the target sampling time points corresponding to the preset test conditions;

[0049] a third determining module configured to obtain sampling information of each of the remaining dies, and if each of the sampling information satisfies the preset condition, the remaining dies are normal;

[0050] The fourth determining module is configured to determine that, if the sampling information in the remaining dies does not meet the preset condition, the die corresponding to the sampling information that does not meet the preset condition is abnormal.

[0051] According to a third aspect of an embodiment of the present disclosure, a wafer testing device is provided, comprising:

[0052] processor;

[0053] a memory for storing processor-executable instructions;

[0054] Among them, the processor is configured to execute the wafer testing method described in the first aspect of the embodiment of the present disclosure.

[0055] According to the fourth aspect of the embodiment of the present disclosure, a non-temporary computer-readable storage medium is provided. When the instructions in the storage medium are executed by the processor of the wafer testing equipment, the wafer testing equipment is enabled to perform the wafer testing method described in the first aspect of the embodiment of the present disclosure.

[0056] In the wafer testing method, apparatus, device, and storage medium provided by the embodiments of the present disclosure, based on different production batch information of wafers and multiple sets of preset test conditions, target sampling points of a preset number of bare dies in the same batch of wafers under each set of preset test conditions are obtained, and then the remaining bare dies under the same conditions are tested according to the preset test conditions and wafer batch information for obtaining the target sampling points, so as to reduce the difference between the sampling time point during the wafer testing process and the time point of the output signal of the bare die, thereby improving the accuracy of wafer testing and the yield of the bare die.

[0057] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The accompanying drawings, which are incorporated into and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, not all embodiments. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0059] Figure 1 is a flow chart showing a wafer testing method according to an exemplary embodiment;

[0060] Figure 2 is a schematic diagram showing multiple groups of preset test conditions according to an exemplary embodiment;

[0061] Figure 3 is a flow chart showing a wafer testing method according to an exemplary embodiment;

[0062] Figure 4 is a schematic diagram showing test information of a bare die according to an exemplary embodiment;

[0063] Figure 5 is a flow chart showing a wafer testing method according to an exemplary embodiment;

[0064] Figure 6 is a flowchart of a wafer testing method according to an exemplary embodiment;

[0065] Figure 7 is a structural block diagram of a wafer testing device according to an exemplary embodiment;

[0066] Figure 8 The figure is a block diagram of a wafer testing device according to an exemplary embodiment. DETAILED DESCRIPTION

[0067] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that, in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0068] After wafer manufacturing is complete, a certain amount of defective die will be found among the dies distributed across the wafer. Wafer testing is used to identify these defective dies, thereby improving the yield rate of shipped products and reducing production costs. ATE (Automatic Test Equipment) is typically used to test wafers. During testing, probes on the ATE connect the pins on the die to the ATE tester, providing test power and signal transmission to the die on the wafer. During the testing process, the timing of the wafer's output signals varies significantly due to factors such as varying manufacturing processes, test temperatures, and test voltages. Therefore, the accuracy of the timing of sampling the die's signal output significantly impacts the die's yield rate.

[0069] Currently, when sampling die signal outputs, testers typically manually set the sampling time by adding or subtracting time from a fixed base sampling point based on a small amount of debugging data and test conditions. This sampling time may differ from the output signal timing, resulting in low wafer test accuracy and a loss in die yield. Furthermore, this method increases the test program's dependence on testers, increasing labor costs.

[0070] In view of this, the present disclosure provides a wafer testing method, comprising: obtaining wafer batch information and multiple sets of preset test conditions; testing a preset number of dies in the same batch of wafers based on each set of preset test conditions, and obtaining target sampling time points corresponding to each set of preset test conditions; and testing the remaining dies in the same batch of wafers based on each set of preset test conditions and their corresponding target sampling time points. By obtaining target sampling points for a preset number of dies in the same batch of wafers under each set of preset test conditions, and then testing the remaining dies under the same conditions based on the preset test conditions and wafer batch information for obtaining the target sampling points, the difference between the sampling time points during the wafer testing process and the time points of the die output signals is reduced, thereby improving the accuracy of wafer testing and the yield of the die, and enhancing the automation of wafer testing.

[0071] The present disclosure is described below with reference to the accompanying drawings and specific embodiments. The exemplary embodiment of the present disclosure provides a wafer testing method, such as Figure 1 As shown, Figure 1 A wafer testing method according to an exemplary embodiment includes:

[0072] Step S100: obtaining wafer batch information and multiple sets of preset test conditions;

[0073] Step S200: Based on each set of preset test conditions, a preset number of dies in the same batch of wafers are tested respectively to obtain a target sampling time point corresponding to each set of preset test conditions;

[0074] Step S300: testing the remaining dies in the same batch of wafers according to each set of preset test conditions and their corresponding target sampling time points.

[0075] In step S100, the manufacturing process of wafers produced in different batches may have slight differences, which may affect the time point of the output signal during the test of the bare die on the wafer. Before starting the test, the batch information of the wafer currently being tested can be obtained to facilitate recording the target sampling time point of the wafers in that batch. The batch information of the wafer can be obtained from the manufacturing end database, or it can be obtained by marking the production batch number on the wafer and reading the production batch number. The batch information of the wafer can be the production batch of the wafer. Wafers of the same production batch can represent that the production process of the wafer is exactly the same.

[0076] Preset test conditions can be pre-designed by testers based on wafer specifications and test requirements. These conditions can be pre-set in the ATE prior to wafer testing to facilitate access and wafer testing based on the preset test conditions. Preset test conditions can include one or more test conditions such as test temperature, test voltage, and test current. Preset test conditions can be arranged and combined to form multiple groups of preset test conditions, allowing for testing of whether the wafer can perform various functions normally under various circumstances, thereby achieving the purpose of wafer testing.

[0077] In step S200, before the wafer begins testing, the pins of the dies on the wafer are connected to the test machine through probes so that the dies on the wafer can be tested under preset test conditions. The test machine sequentially obtains each set of preset test conditions in a plurality of sets of preset test conditions and tests the wafer on the current test machine. For ease of explanation, this embodiment and subsequent embodiments illustrate the wafer testing method of the present disclosure by performing wafer testing based on a set of preset test conditions. In some embodiments, since the production process of wafers in the same batch is the same, during the testing process, the wafer batch can be used as a distinguishing condition, and a preset number of wafers in the same batch of wafers can be tested under a set of preset test conditions to obtain corresponding target sampling points, or a preset number of dies in the same batch of wafers can be tested to obtain corresponding target sampling points. In other embodiments, taking a single wafer in the same batch as a unit, during the testing process, under a set of preset test conditions, all dies on the wafer can be tested simultaneously, or some of the dies on the wafer can be tested simultaneously, or the dies on the wafer can be tested sequentially in a certain order.

[0078] In this embodiment, a preset number of dies from the same batch of wafers are tested separately. The preset number can be pre-set in the test machine based on actual testing requirements, and can be, for example, 5, 10, or the like. By testing the preset number of dies and obtaining the time point of each die's output signal under the current preset test conditions, the target sampling time point corresponding to the time point of the output signal of the wafer corresponding to each die under the current preset test conditions can be determined based on the time point of each die's output signal. Because the target sampling time point is determined based on the current actual preset test conditions, the difference between the obtained target sampling time point and the time point of the output signal is very small, thereby improving the accuracy of wafer testing.

[0079] In some possible implementations, each set of preset test conditions includes temperature information and multiple voltage information.

[0080] refer to Figure 2 As shown, Figure 2 It is a schematic diagram of multiple sets of preset test conditions. In order to ensure that the chips produced by the bare die on the wafer can work normally in harsh environments of high and low temperatures, it is necessary to test the wafer in a high and low temperature environment after heating or cooling it in the test machine. The temperature information can be the temperature of the wafer during the wafer test. For example, the temperature range in the preset test conditions can be, for example, 125°C to -65°C. For example, 125°C, -40°C, and 98°C can be selected to test whether the wafer can work normally at different temperatures. The wafer can be heated or cooled by the heating layer and the cooling layer on the wafer carrier in the test machine so that the temperature of the wafer reaches the test temperature.

[0081] In order to enable the chip to have storage and reading functions, an internal circuit is provided in the die. The voltage information can be the voltage provided to the internal circuit of the die by the probe, so that the die can perform the corresponding function. Based on the design of the internal circuit in the die, the voltage provided to the die may include multiple voltage information such as VDD1, VDD2 and VDDQ. Among them, VDD1 represents a high voltage, VDD2 represents a low voltage, and VDDQ represents the power supply voltage of the memory chip output buffer. Generally, the voltage value of VDD2 and VDDQ is the same. For example, since wafer testing needs to test multiple functions of the die, that is, multiple test items, such as pre-charge, refresh, read, write and other functions, different test items require different voltages. Therefore, it is necessary to set the voltages such as VDD1, VDD2 and VDDQ to different values ​​to form different voltage combinations. A voltage combination can represent multiple voltage information required to execute a test item.

[0082] Each set of preset test conditions can include a temperature value from the temperature information and one of the multiple voltage combinations formed by multiple voltage information. For example, 125°C and voltage combination a form one set of preset test conditions, while 125°C and voltage combination b form another set of preset test conditions. Testing the wafer under each set of preset test conditions verifies whether the die on the wafer function properly when executing the test item corresponding to that voltage combination at the current temperature.

[0083] In some possible implementations, such as Figure 3 As shown, in step S200, based on each set of preset test conditions, a preset number of dies in the same batch of wafers are tested separately to obtain a target sampling time point corresponding to each set of preset test conditions, including:

[0084] Step S210: Under each set of preset test conditions, perform write and read operations on each of the preset number of dies to collect test information of the dies;

[0085] Step S220: When the test information meets the preset conditions, stop the test and obtain the time information of the test stop moment as reference time information;

[0086] Step S230: Determine the target sampling time point corresponding to each set of preset test conditions according to the reference time information.

[0087] In step S210, the wafer test temperature is set to be consistent with the temperature information in the current preset test conditions, and a voltage combination formed by multiple voltages such as VDD1, VDD2, and VDDQ is provided to a preset number of bare chips in the wafer, and the voltage combination provided to each bare chip is the same. The internal circuit in the bare chip will perform signal inversion upon receiving the external voltage and output the signal. By controlling the test machine to transmit read and write signals to each bare chip, write and read operations are performed on the bare chip, so that the test machine can collect test information of the bare chip at the location specified by the write and read operations. The test information can be the signal output information of the bare chip under the current preset test conditions, for example, it can be an output voltage signal.

[0088] In some possible implementations, in step S210, under each set of preset test conditions, performing write and read operations on each of the preset number of dies to collect test information of the dies includes:

[0089] Step S211: Start testing under preset test conditions and wait for a first preset time period;

[0090] Step S212: After waiting for the first preset time, perform a write / read operation on each of the preset number of dies at intervals of a second preset time, and collect test information corresponding to the write / read operation.

[0091] In this embodiment, the test temperature of the wafer is set to be consistent with the temperature information in the current preset test conditions, and the test begins when a voltage combination formed by multiple voltages such as VDD1, VDD2 and VDDQ is provided to a preset number of bare chips in the wafer. Figure 4 , Figure 4 The figure is a schematic diagram of die test information. Since the signal transition from the start of the test to the appearance of signal output information requires a certain amount of time, namely, a first preset time. The first preset time can be set to different lengths based on different wafer specifications, for example, it can be anywhere from 4ns to 6ns, such as 5ns. That is, during the test process, from the start of the test, the internal circuit of the die will not output test information, i.e., output signal, until the first preset time has passed. After waiting for the first preset time, a write / read operation is performed on each of a predetermined number of dies at intervals of a second preset time, allowing the test machine to collect test information corresponding to the write / read operation at the location specified by the write / read operation. The second preset time can be, for example, anywhere from 0.15ns to 0.25ns, such as 0.2ns. The second preset time is the interval between write / read operations. By performing write / read operations at intervals to collect test information, the output signal corresponding to the die's test information can be quickly captured and reference time information determined.

[0092] In step S220, the tester can pre-set preset conditions in the test machine and determine whether the collected test information meets the preset conditions to determine whether the die corresponding to the test information is normal or abnormal. The test information can be, for example, sampled voltage information, such as the sampled output voltage value, and the preset condition can be, for example, a reference voltage value. To determine whether the test information meets the preset conditions, for example, it can be determined whether the sampled voltage information is greater than the reference voltage value. When the sampled voltage information is less than the reference voltage value, the test information is determined to not meet the preset conditions; when the sampled voltage information is greater than the reference voltage value, the test information is determined to meet the preset conditions. When the test information meets the preset conditions, the die corresponding to the test information is determined to be normal, and the test machine stops testing. At the same time, the time information of the moment the test stops is obtained as reference time information. The reference time information is a reference parameter for obtaining the target sampling time point.

[0093] In some possible implementations, the wafer testing method further includes:

[0094] When the cumulative test duration of each die reaches a third preset duration since the start of the test and all test information obtained does not meet the preset conditions, the test is stopped and it is determined that the die has an abnormality.

[0095] In this embodiment, due to certain chip timing requirements, namely, the chip is required to output test information that meets preset conditions within a certain time period, therefore, since the start of the test, when the cumulative test time of the die reaches a third preset time period (e.g., equal to or greater than the third preset time period), and all the test information obtained fails to meet the preset conditions, the test is stopped and the die is determined to have an abnormality. The cumulative test time of the die includes a first preset time period for signal toggle and a second preset time period for performing multiple write and read operations. The third time period can be, for example, any time period between 14ns and 16ns, such as 15ns. The third preset time period can correspond to a timing set by the customer or industry standard. By setting the third preset time period, the timing of the normal die can be ensured to be within the permitted range.

[0096] In some possible implementations, the wafer testing method further includes:

[0097] If the collected test information does not meet the preset conditions, the number of times the preset conditions are not met is recorded and the test is continued.

[0098] In this embodiment, due to the influence of different manufacturing processes, test temperatures, test voltages, and other conditions, the time it takes for a wafer to output test information that meets preset conditions can vary significantly. Therefore, when test information collected during a write or read operation fails to meet the preset conditions, the test information is recorded as a fail. The number of times the preset conditions are not met (i.e., the number of fails) is recorded, and a determination is made as to whether the cumulative test duration of the die has reached a third preset duration. If the third preset duration has not been reached, testing continues, i.e., the write or read operations continue to be performed to collect test information. If the third preset duration has been reached, testing is stopped and a determination is made that the die has an abnormality.

[0099] In some possible implementations, in step S220, the method for determining the reference time information includes:

[0100] Step S221: Calculate the product of the number of times the test information fails to meet the preset condition and the second preset time length;

[0101] Step S222: The sum of the product and the first preset duration is used as reference time information.

[0102] In this embodiment, since the reference time information is the time information of the moment when the test information meets the preset conditions and the test is stopped, during the process from the start of the test to the stop of the test, after waiting for the first preset time for the signal flipping time, and after waiting for the first preset time, due to the influence of different manufacturing processes, test temperatures, test voltages and other conditions, for example, the test information obtained by the first write and read operation may meet the preset conditions, or it may meet the preset conditions after multiple failures. Therefore, the product of the number of times the test information fails to meet the preset conditions and the second preset time is calculated, which is the time it takes for the test to meet the preset conditions. The sum of this product and the first preset time is used as the reference time information. The reference time information represents the time it takes from the start of the test to the test information meeting the preset conditions. The reference time information is expressed as: reference time information = first preset time + number of failures * second preset time.

[0103] In step S230, the obtained reference time information is used as a reference parameter to determine the target sampling time point of the bare die in the wafer under the current preset test conditions, so as to reduce the difference between the target sampling time point and the time point of the output signal, improve the accuracy of the wafer test, and reduce the yield loss of the wafer.

[0104] In some possible implementations, in step S230, determining the target sampling time point corresponding to each set of preset test conditions according to the reference time information includes:

[0105] Step S231, obtaining period information of sampled voltage information;

[0106] Step S232: The sum of the preset multiple of the period information and the reference time information is used as the target sampling time point.

[0107] In this embodiment, reference Figure 4 As shown, the sampled voltage information of the die is the output voltage signal obtained by testing the die under preset test conditions. Depending on the actual operation of the chip, the sampled voltage information that meets the preset conditions has a certain signal waveform, such as a regular signal waveform. For example, the sampled voltage information can be a sine signal waveform or a cosine signal waveform. The period information of the sampled voltage information is obtained, and the period information is, for example, the time required to output one cycle of the sampled voltage information.

[0108] The time information corresponding to the reference time information is the time when the test is stopped. Since there may be slight process differences in the wafer production process, the peak value of the sampled voltage information that meets the preset test conditions is determined, and the time information corresponding to the peak value of the sampled voltage information is used as the target sampling time point. The time information corresponding to the peak value of the sampled voltage information is the preset multiple of the period information, so as to reduce the difference between the target sampling time point and the time point of the actual output signal of the bare chip, and ensure the accuracy of the obtained target sampling time point. Figure 4 The sampled voltage information is a sinusoidal waveform with two peaks in one cycle. The preset multiples correspond to one-quarter and three-quarters of the time required in one cycle, respectively. Therefore, the sampling time point can be determined as the time corresponding to one-quarter to three-quarters of the sampled voltage information cycle. For example, it can be the time point corresponding to the first peak corresponding to one-quarter of the cycle. This ensures the accuracy of the sampling time point while saving unnecessary test time. The sum of the preset multiples of the cycle information and the reference time information is used as the target sampling time point. The target sampling time point represents the duration from the start of the test to the final sampling by the ATE. The target sampling time point is expressed as: target sampling time point = reference time information + cycle information of the sampled voltage information * [1 / 4 to 3 / 4]. In other words, the target sampling time point = first preset duration + number of failures * second preset duration + cycle information of the sampled voltage information * [1 / 4 to 3 / 4].

[0109] In step S300, the ATE tests the remaining dies in the same batch of wafers under the same preset test conditions based on the target sampling time point obtained under the current preset test conditions. When testing the remaining dies in the same batch of wafers, all the remaining dies can be tested simultaneously, or the remaining dies can be tested sequentially. Since the target sampling time point used is determined based on the current actual preset test conditions, the difference between the target sampling time point and the time point of the output signal is very small, thereby reducing misjudgments caused by sampling time point errors, thereby improving the accuracy of wafer testing and the yield of dies and wafers.

[0110] In some possible implementations, reference Figure 5 As shown, in step S300, the remaining dies in the same batch of wafers are tested according to the target sampling time point, including:

[0111] Step S310: Under each set of preset test conditions, test the remaining dies according to the target sampling time points corresponding to the preset test conditions;

[0112] Step S320: acquiring sampling information of each of the remaining dies. If each sampling information satisfies a preset condition, the remaining dies are normal.

[0113] Step S330: If there is sampling information in the remaining dies that does not meet the preset condition, the die corresponding to the sampling information that does not meet the preset condition is abnormal.

[0114] In step S310, under each set of preset test conditions, the remaining die are tested according to the target sampling time point corresponding to the preset test conditions. That is, for wafers from the same batch as the one for which the target sampling time point was obtained, or for the same single wafer as the one for which the target sampling time point was obtained, when the remaining die are tested under the same preset test conditions, the target sampling time point obtained is used to sample the remaining die. For example, under preset test condition X, by testing a preset number of die in wafer x, the target sampling time point obtained is 9.6 ns, i.e., 9.6 ns is the calculated target time for sampling the die signal output after the start of the test. Under the same preset test condition X, when the remaining die in wafer x are tested, the target sampling time point is used to sample the remaining die, i.e., the die signal output is sampled 9.6 ns after the start of the test, thereby reducing misjudgments caused by sampling time point errors and improving wafer testing accuracy.

[0115] In step S320, sampling information is obtained for each of the remaining dies. The sampling information for each die is obtained by sampling at the target sampling time point. The sampling information may be, for example, sampled voltage information. By comparing the sampling information with a preset condition, if the sampling information for each of the remaining dies meets the preset condition, i.e., the sampled voltage information for each die is greater than a reference voltage value, then each of the remaining dies is determined to be normal.

[0116] In step S330, if any of the remaining dies have sampled information that does not meet the preset condition, the die corresponding to the sampled information that does not meet the preset condition is considered abnormal. That is, during the test process, if the sampled voltage information of one or more dies is less than the reference voltage value, the die corresponding to the sampled voltage information is considered abnormal.

[0117] It should be noted that since there are multiple sets of preset test conditions during the wafer test process, Figure 2 , for the same batch of wafers, or a single wafer, they all need to be tested in sequence based on each set of preset test conditions, where the target sampling time point corresponding to each set of preset test conditions needs to be re-acquired and determined based on the current preset test conditions during the test process. After multiple sets of preset test conditions are tested, the wafer test is completed. Whether the bare die in the wafer is qualified needs to be further judged based on the normal or abnormal situation of each bare die under multiple sets of preset test conditions after each bare die is tested and sampled under multiple sets of preset test conditions.

[0118] The following is an explanation of the overall workflow of the technical solution disclosed in this disclosure. Figure 6 As shown, Figure 6 This is a schematic diagram of a wafer testing method according to an exemplary embodiment of the present disclosure. The wafer testing method according to this embodiment includes multiple sets of preset test conditions. For each set of preset test conditions, the wafer testing method according to this embodiment includes the following steps:

[0119] S1. Obtain wafer batch information and multiple sets of preset test conditions.

[0120] S2. Based on each set of preset test conditions, a preset number of dies in the same batch of wafers are tested separately.

[0121] S3: Wait for a first preset time period.

[0122] S4. Perform write and read operations on each of the preset number of bare chips at intervals of a second preset time length to collect test information.

[0123] S5. Determine whether the test information meets the preset conditions;

[0124] If so, it means that the test information meets the preset conditions, indicating that the bare chip corresponding to the test information is normal, and the process goes to S8; if not, the process goes to S6.

[0125] S6. Record the number of times the test information fails to meet the preset conditions.

[0126] S7, determining whether the cumulative test duration reaches a third preset duration;

[0127] If so, it indicates that the accumulated test time has reached the third preset time, and the die is abnormal, and S15 is executed; if not, S4 is continued to be executed.

[0128] S8. Stop testing, the die is normal.

[0129] S9. Calculate the product of the number of times the test information fails to meet the preset condition and the second preset time length, and use the sum of the product and the first preset time length as reference time information.

[0130] S10: Obtain period information corresponding to test information that meets preset conditions, and use the sum of a preset multiple of the period information and reference information as target sampling information.

[0131] S11. Under each set of preset test conditions, the remaining bare dies in the same batch of wafers are tested according to the target sampling time points corresponding to the preset test conditions.

[0132] S12. Obtain sampling information of each die.

[0133] S13, determining whether the sampling information meets the preset conditions;

[0134] If so, it indicates that the die corresponding to the sampling information is normal, and the process goes to S14; if not, the process goes to S15.

[0135] S14. Stop testing, the die is normal.

[0136] S15. Stop testing, the die is abnormal.

[0137] The present disclosure exemplarily provides a wafer testing device, referring to Figure 7 As shown, Figure 7 is a structural block diagram of a wafer testing device, which is configured to be able to perform the wafer testing method in the above embodiment of the present disclosure, and the wafer testing device includes:

[0138] An acquisition module 100 is configured to acquire wafer batch information and multiple sets of preset test conditions;

[0139] The first testing module 200 is configured to test a preset number of dies in the same batch of wafers based on each set of preset test conditions, and obtain a target sampling time point corresponding to each set of preset test conditions;

[0140] The second testing module 300 is configured to test the remaining dies in the same batch of wafers according to each set of preset testing conditions and their corresponding target sampling time points.

[0141] In some possible implementations, the first testing module 200 includes:

[0142] The collection device 210 is configured to perform write and read operations on each of the preset number of dies under each set of preset test conditions to collect test information of the dies;

[0143] The first determining module 220 is configured to stop the test and obtain the time information of the test stopping moment as reference time information when the test information meets the preset condition;

[0144] The second determining module 230 is configured to determine the target sampling time point corresponding to each set of preset test conditions according to the reference time information.

[0145] In some possible implementations, the second testing module 300 includes:

[0146] The third test module 310 is configured to test the remaining dies under each set of preset test conditions according to the target sampling time points corresponding to the preset test conditions;

[0147] The third determination module 320 is configured to obtain sampling information of each of the remaining dies, and if each sampling information satisfies a preset condition, the remaining dies are normal;

[0148] The fourth determining module 330 is configured to determine that the die corresponding to the sampling information that does not meet the preset condition is abnormal if the sampling information among the remaining dies does not meet the preset condition.

[0149] Regarding the wafer testing device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0150] Figure 8 1 is a block diagram of a wafer testing device according to an exemplary embodiment, namely, a wafer testing device 800. The wafer testing device 800 may be the ATE device in the above exemplary embodiments of the present disclosure. For example, the wafer testing device 800 may be provided as a terminal device. Figure 8The wafer testing device 800 includes a processor 801, and the number of processors 801 can be set to one or more as needed. The wafer testing device 800 also includes a memory 802 for storing instructions executable by the processor 801, such as application programs. The number of memories 802 can be set to one or more as needed. The application programs stored therein can be one or more. The processor 801 is configured to execute instructions to perform the above-mentioned wafer testing method.

[0151] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, devices (equipment), or computer program products. Therefore, the present disclosure may take the form of a fully hardware embodiment, a fully software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code. Computer storage media include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data), including but not limited to RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVDs) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium.

[0152] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is provided, such as a memory 802 including instructions. The instructions can be executed by a processor 801 of a wafer testing device 800 to perform the above-described wafer testing method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.

[0153] In an exemplary embodiment of the present disclosure, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium can be set in a wafer testing device so that the wafer testing device can execute the wafer testing method provided by the exemplary embodiment of the present disclosure.

[0154] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, apparatus (devices) and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0155] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0156] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0157] In this disclosure, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of further limitations, an element defined by the phrase "comprising..." does not preclude the presence of additional identical elements in the article or device comprising the element.

[0158] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0159] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such modifications and variations.

Claims

1. A wafer testing method, characterized in that: The wafer testing method comprises: Obtain wafer batch information and multiple sets of preset test conditions; Based on each set of the preset test conditions, a preset number of dies in the same batch of wafers are tested respectively to obtain a target sampling time point corresponding to each set of the preset test conditions; Testing the remaining dies in the wafer batch according to each set of the preset test conditions and the corresponding target sampling time point; Each set of preset test conditions includes temperature information and multiple voltage information; Based on each set of the preset test conditions, a preset number of dies in the same batch of wafers are tested separately to obtain a target sampling time point corresponding to each set of the preset test conditions, including: Under each set of the preset test conditions, performing write and read operations on each of the preset number of the bare chips to collect test information of the bare chips; When the test information meets the preset conditions, the test is stopped and the time information of the test stopping moment is obtained as reference time information; The target sampling time point corresponding to each set of the preset test conditions is determined according to the reference time information.

2. The wafer testing method according to claim 1, wherein: The step of performing write and read operations on each of the preset number of dies under each set of the preset test conditions to collect test information of the dies includes: Start testing under the preset test conditions and wait for a first preset time period; After waiting for the first preset time period, a write / read operation is performed on each of the preset number of dies at intervals of a second preset time period, and test information corresponding to the write / read operation is collected.

3. The wafer testing method according to claim 2, wherein: The wafer testing method further includes: When the cumulative test duration of each die reaches a third preset duration since the start of the test, and all the obtained test information does not meet a preset condition, the test is stopped and it is determined that the die has an abnormality.

4. The wafer testing method according to claim 3, wherein: The wafer testing method further includes: If the collected test information does not meet the preset condition, the number of times the preset condition is not met is recorded, and the test is continued.

5. The wafer testing method according to claim 4, wherein: The test information includes sampled voltage information, and the preset condition includes a reference voltage value; The test information meets the preset conditions, including: The sampled voltage information is greater than the reference voltage value.

6. The wafer testing method according to claim 5, wherein: Determining, based on the reference time information, a target sampling time point corresponding to each set of the preset test conditions, including: Acquiring period information of the sampled voltage information; The sum of the preset multiple of the period information and the reference time information is used as the target sampling time point.

7. The wafer testing method according to claim 6, wherein: The method for determining the reference time information includes: Calculating the product of the number of times the test information fails to meet the preset condition and the second preset time length; The sum of the product and the first preset time length is used as the reference time information.

8. The wafer testing method according to claim 6, wherein: The preset multiple is one quarter to three quarters; and / or, The first preset time length is 4ns to 6ns; and / or, The second preset time length is 0.15ns to 0.25ns; The third preset time length is 14ns to 16ns.

9. The wafer testing method according to claim 1, wherein: Testing the remaining dies in the wafer batch according to the target sampling time point includes: Under each set of the preset test conditions, testing the remaining dies according to the target sampling time points corresponding to the preset test conditions; Acquire sampling information of each of the remaining dies, and if each of the sampling information satisfies the preset condition, the remaining dies are normal; If the sampling information in the remaining dies does not meet the preset condition, the die corresponding to the sampling information that does not meet the preset condition is abnormal.

10. A wafer testing device, characterized in that: The wafer testing device comprises: an acquisition module configured to acquire wafer batch information and multiple sets of preset test conditions; The first testing module is configured to test a preset number of dies in the same batch of wafers based on each set of preset test conditions, and obtain a target sampling time point corresponding to each set of preset test conditions; the second testing module is configured to test the remaining dies in the same batch of wafers based on each set of preset test conditions and the corresponding target sampling time point; The first test module includes: A collection device is configured to perform write and read operations on each of the preset number of the bare chips under each set of the preset test conditions to collect test information of the bare chips; A first determining module is configured to stop the test and obtain time information of the test stopping moment as reference time information when the test information meets a preset condition; The second determining module is configured to determine the target sampling time point corresponding to each set of the preset test conditions according to the reference time information.

11. The wafer testing device according to claim 10, wherein: The second test module includes: a third testing module configured to test the remaining dies under each set of the preset test conditions according to the target sampling time points corresponding to the preset test conditions; a third determining module configured to obtain sampling information of each of the remaining dies, and if each of the sampling information satisfies the preset condition, the remaining dies are normal; The fourth determining module is configured to determine that, if the sampling information in the remaining dies does not meet the preset condition, the die corresponding to the sampling information that does not meet the preset condition is abnormal.

12. A wafer testing device, characterized in that: The wafer testing equipment includes: processor; a memory for storing processor-executable instructions; Wherein, the processor is configured to execute the wafer testing method according to any one of claims 1 to 9.

13. A non-transitory computer-readable storage medium, characterized in that When the instructions in the storage medium are executed by a processor of a wafer testing device, the wafer testing device is enabled to perform the wafer testing method according to any one of claims 1 to 9.

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